CN102779480B - Display screen drive circuit and light-emitting diode display device - Google Patents
Display screen drive circuit and light-emitting diode display device Download PDFInfo
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Abstract
The invention discloses a display screen drive circuit which comprises a signal input unit, a data processing and shifting register, a data register, a state register, a counter and a pulse width modulation signal generating unit, wherein the signal input unit is used for inputting a serial data input signal, a gray scale clock signal, a data clock signal and a data control signal; the data processing and shifting register is used for responding the data clock signal and the data control signal and obtaining serial gray scale data and serial state data from the serial data input signal; the data register is used for receiving the serial gray scale data signal; the stage register is used for storing a preset state data and receiving the serial state data; the counter is used for generating a counting value according to the preset state data, the serial state data and the gray scale clock signal; and the pulse width modulation signal generating unit is used for generating a plurality of pulse width modulation signals according to the serial gray scale data obtained from the data register and the counting value of the counter, and outputting the pulse width modulation signals. The invention also provides a light emitting diode display device adopting the display screen drive circuit so that the high refreshing efficiency is realized.
Description
Technical field
The present invention relates to Display Driver field, particularly relate to a kind of display drive circuit and use the light emitting display device of described display drive circuit.
Background technology
Light emitting diode (LED) display screen is widely used in the places such as stadiums, square, building in recent years, in actual use, often there will be the situation of scanning ripple and image gray-scale level loss, cannot meet the needs of high-end market.For this reason, the light emitting diode (LED) display screen drive system of high refresh rate occurs it being the inevitable requirement of market and development in science and technology.
In general, about 30 width per second or higher moving image can be thought continuous print by human eye, that is under worst condition, human eye only needs the refresh rate of 30Hz.Higher refresh rate can make image more aobvious continuously and stable, if reach the refresh rate of more than 50Hz per second, and human eye just imperceptible obvious difference.But out of doors in practical application, in order to removal of images flicker, generally the refreshing frequency of full color display should be not less than 240Hz; Brightness is more than 4000cd/m
2the refresh rate of full color display should be not less than 400Hz; For the image of more high brightness, the refreshing frequency of display screen will reach 800-1000Hz.
In traditional light emitting diode (LED) display screen drive system, when the frequency of gray scale clock signal input GCLK is 20MHz, if light emitting diode (LED) display screen is applied in static screen system, control if driving chip is 16 rank pulse-length modulation GTGs, then the refresh rate of light emitting diode (LED) display screen is about 305Hz; If be applied in the dynamic screen of 1/8 line scanning, then the refresh rate of light emitting diode (LED) display screen is about 38Hz.
In order to improve the refresh rate of light emitting diode (LED) display screen, some chip design producer pulse width modulating signals to driving chip are split, and by the pulse-length modulation grayscale signal on 16 rank, are divided into the pulse width modulating signal on 64 10 rank.Carried out such improvement, in the application of static state screen, the refresh rate of light emitting diode (LED) display screen can be brought up to and be about 19531Hz.But, nonetheless, if said method is applied in the screen of 1/8 line scanning, then only within the sweep time of oneself, just can understand open circuit, namely, after other 7 row complete 16 rank images because of light emitting diode, just again can be lit, therefore cannot improve the refresh rate of dynamic screen.
Summary of the invention
In order to solve the problems of the technologies described above, the embodiment of the present invention provides a kind of display drive circuit and adopts the light emitting display device of described display drive circuit.
According to one embodiment of the invention, provide a kind of display drive circuit, described display drive circuit comprises: signal input unit, for input serial data input signal, gray scale clock signal, data clock signal and data controlling signal; Data processing and shift register, be coupled to described signal input unit, for responding described data clock signal and data controlling signal and obtaining serial gray scale data and serial state data from described input serial data signal; Data register, is coupled to described data processing and shift register, for receiving described serial gray scale data signal; Status register, is coupled to described data processing and shift register, for storing a predetermined status data and receiving described serial state data; Counter, is coupled to described status register, for producing a count value according to described predetermined status data, described serial state data and described gray scale clock signal; And pulse width modulating signal generation unit, be coupled to described data register and described counter, for the count value according to the serial gray scale data sum counter obtained from described data register, produce multiple pulse width modulating signal and export.
Wherein, serial gray scale data is divided into 2 by pulse width modulating signal generation unit
lthe pulse width modulating signal on individual H rank, wherein, the high-order exponent number of H indicating impulse bandwidth modulation signals, the low order exponent number of L indicating impulse bandwidth modulation signals.
Wherein, described counter is according to formula: (2
h× T
gCLK+ T) × S × 2
lcalculate the time that the complete image with S the number of scanning lines completes dynamic scan needs, wherein, the high-order exponent number of H indicating impulse bandwidth modulation signals, the low order exponent number of L indicating impulse bandwidth modulation signals, T
gCLK× 2
hrepresent export each divided after time of needing of pulse width modulating signal, T represents line scanning switching time, and S represents the number of scanning lines.
Wherein, when counter carries out scan period counting to piece image, first first time 2 is carried out
hcounting, then interval (2
h× T
gCLK+ T) × time of (S-1), continue second time 2
hcounting, and then one (2, interval
h× T
gCLK+ T) × time of (S-1) ... circulate successively, until complete 2
lsecondary 2
hcounting.
Wherein, the output time completing a line pulse width modulating signal has been more than or equal to the input time of next line serial gray scale data to be scanned.
Wherein, the state of described status register also for supplying user to set driving circuit, to obtain described predetermined status data.
Wherein, described display drive circuit comprises the driving chip of multiple cascade, and each driving chip comprises described signal input unit, data processing and a shift register, data register, status register, counter and pulse width modulating signal generation unit.
Wherein, described signal input unit comprises serial data input, GTG input end of clock, data clock input end and data controlling signal input end, is respectively used to transmit described input serial data signal, gray scale clock signal, data clock signal and data controlling signal.
According to another embodiment of the present invention, a kind of light emitting display device is provided, it at least comprises: light emitting diode (LED) display screen and above-mentioned display drive circuit, this display drive circuit is coupled to described light emitting diode (LED) display screen, shows image to drive described light emitting diode (LED) display screen.
Wherein, the output of described pulse width modulating signal generation unit is coupled to a constant current output passage, and pulse width modulating signal is input to described light emitting diode (LED) display screen from described constant current output passage.
The present invention modulates luma data due to input pulse width and have employed segmentation form, and the counter of driving chip produces count value and interval time according to predetermined requirement, then the width complete image data exported just can be regarded as and the gray scale data signal of input is converted into 2
lthe pulse width modulating signal of individual segmentation group.And the pulse width modulating signal of each segmentation group, contain the pulse width modulating signal from the first row to S capable often row H rank, the time that often row switches is T.The time completing the pulse width modulating signal of an output segmentation group is like this (2
h× T
gCLK+ T) × S, thus the refresh rate of display screen can be promoted about 2
ldoubly.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the high-level schematic functional block diagram of the display drive circuit that the embodiment of the present invention provides;
Fig. 2 is the sequential chart of the input serial data signal (SDI) of display drive circuit for Fig. 1, data clock signal (DCLK) and data controlling signal (LE);
Fig. 3 is the schematic diagram of the pulse width modulating signal that the display drive circuit of Fig. 1 exports;
Fig. 4 is the structured flowchart of the light emitting display device of the display drive circuit of employing Fig. 1 that the embodiment of the present invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The display drive circuit that the present invention proposes, is applicable to dynamic display screen and static state display screen system to drive light emitting diode (LED) display screen.What exist for prior art cannot meet the problem obtaining higher refresh rate under high display precision, the cascade of input display data are split by the display drive circuit that the embodiment of the present invention provides, and according to the display data after segmentation, under the control of count value, generate pulse-length modulation (PWM) signal in order to adjustment display effect, thus higher screen refresh rate can be obtained in dynamic screen scanning system.
The functional module structure figure of the display drive circuit 100 that Fig. 1 provides for the embodiment of the present invention, for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention.
In the present embodiment, described display drive circuit 100 comprises the driving chip of multiple cascade.In order to for simplicity, Fig. 1 is only described for first order driving chip wherein.Concrete, the display drive circuit 100 of the present embodiment comprises: signal input unit 10, data processing and shift register 20, data register 30, status register 40, counter 50 and pulse-length modulation (hereinafter referred to as PWM) signal generation unit 60.Data processing and shift register 20 are coupled to the output terminal of signal input unit 10, data register 30 and status register 40 are all coupled to data processing and shift register 20, counter 50 is coupled to status register 40, the input of PWM signal generation unit 60 is coupled to data register 30 and counter 50, and the output of PWM signal generation unit 60 is coupled to a constant current output passage 70.Pwm signal is input to light emitting diode (LED) display screen 102 (referring to Fig. 4) from constant current output passage 70, shows to control light emitting diode (LED) display screen 102.
Described signal input unit 10 comprises serial data input, GTG input end of clock, data clock input end and data controlling signal input end, is respectively used to transmit the input serial data signal (SDI), gray scale clock signal (GCLK), data clock signal (DCLK) and the data controlling signal (LE) that receive from single-chip microcomputer (MCU).Wherein, data clock signal (DCLK) is input in described data processing and shift register 20 for controlling input serial data signal (SDI), and data clock signal (DCLK) coordinates data controlling signal (LE) to be transferred in data register 30 by the input serial data signal (SDI) in data processing and shift register 20 simultaneously.The clock signal that gray scale clock signal (GCLK) is counter.Data controlling signal (LE) then comprises the number of different data clock signal (DCLK) rising edges, and rate control command and STATUS control commands are carried out in representative.Such as, data controlling signal (LE) comprises the rising edge of 1 data clock signal (DCLK), rate control command is carried out in representative, that is, at the negative edge of this data controlling signal (LE), input serial data signal (SDI) can be stored in data register 30; If data controlling signal (LE) comprises the rising edge of 2 data clock signals (DCLK), then STATUS control commands is carried out in representative, and now, input serial data signal (SDI) can be stored in status register 40.In addition, in the present embodiment, the signal that described signal input unit 10 inputs is cascade signal.Described input serial data signal (SDI) inputs according to the quantity of the driving chip of cascade, such as, supposes a cascade M driving chip, then need input M group input serial data signal (SDI).
Described data processing and shift register 20 are for receiving described data clock signal, data controlling signal and described input serial data signal, and respond described data clock signal and data controlling signal, to obtain serial gray scale data and serial state data from described at least one group of input serial data signal, and the signal representing serial gray scale data can be outputted to described data register 30, and the signal representing serial state data is outputted to status register 40.
Described data register 30, for when receiving the data command of data controlling signal (LE), receives described serial gray scale data signal.
Described status register 40, for when receiving the status command of data controlling signal (LE), receives described serial state data.Described status register 40 can also preset the state of driving circuit for user, such as set the grayscale mode (16 grayscale mode, 14 grayscale mode or 12 grayscale mode etc.) of driving circuit by how much advance line scanning, passage, thus obtain a predetermined status data and store.
Described counter 50 is for producing a count value according to the data of described predetermined status data, gray scale clock signal (GCLK) and described status register 40.In the present embodiment, described counter 50 is according to formula: (2
h× T
gCLK+ T) × S × 2
lcalculate the time that the complete image with S the number of scanning lines completes dynamic scan needs, wherein, the high-order exponent number of H indicating impulse bandwidth modulation signals, the low order exponent number of L indicating impulse bandwidth modulation signals, T
gCLK× 2
hrepresent that the time that segmentation High Order Impulsive bandwidth modulation signals needs, T represent line scanning switching time, S represents the number of scanning lines.The specific works process of counter 50 will be introduced in detail in following examples.
Described pulse-length modulation (calling PWM in the following text) signal generation unit 60, for the count value exported according to described gray scale clock signal, the serial gray scale data sum counter 50 that obtains from described data register 30, produces multiple pulse width modulating signal and is exported.PWM signal generation unit 60 is input to after in data register 30 in serial gray scale data, from data register 30, obtain described serial gray scale data, and carries out the segmentation of pwm signal under the control of count value, and is exported by the pwm signal after segmentation.
It should be noted that, the first order driving chip of described display drive circuit 100 also can export an output signal SDO, using the input serial data signal (SDI) as next stage cascade driving chip, and the data controlling signal (LE) of cascade driving chip at different levels, data clock signal (DCLK), gray scale clock signal (GCLK) are all corresponding identical with first order driving chip.
Fig. 2 is that input serial data signal (SDI) and data controlling signal (LE) coordinate data clock signal (DCLK) to complete the time diagram of input, so that the signal input process of display drive circuit 100 to be described.As can be known from Fig. 2, if display drive circuit 100 comprises the cascade of M chips, and serial date transfer 1 signal (SDI) is at the edge serial input of data clock signal (DCLK), then after input completes M group input serial data signal (SDI), according to the control of data controlling signal (LE) and data clock signal (DCLK), luma data of connecting is sent in data register 30 with shift register 20 by data processing, thus completes a line scan-data input of display drive circuit 100.If need to carry out S line scanning, then the signal of S × M group input serial data signal (SDI) has been needed to input.It should be noted that, after each input complete M group signal, all need under the control of data controlling signal (LE) and data clock signal (DCLK), driving chip to correspondence sends the order that data have inputted, and then the serial gray scale data of data processing and shift register 20 is sent in data register 30.
As mentioned above, status register 40 can by presetting, export data to counter 50 according to the information of the number of scanning lines and the gray level information of luma data, make luma data jointly coordinate with count value and produce the pwm signal of segmentation, and allow system obtain high refresh rate.
For example, if driving circuit cascade M driving chip, the output channel number of every driving chip is C, the number of scanning lines is S, line scanning switching time (blanking time) is set as T, simultaneously the GTG of the output data of driving chip is controlled as P rank (its high-order is H rank, and low order is L rank, and H+L=P).Then according to the count value of counter 50, the pwm signal on P rank can be divided into 2 in PWM signal generation unit 60
lthe pwm signal on individual H rank.And if input serial data signal (SDI) only enters driving chip at the edging trigger of data clock signal (DCLK), then the time inputting the luma data of the driving chip of M cascade is T
dCLK× C × M × P.When the P rank luma data inputted carries out being divided into pwm signal, the time that splitting a H rank pwm signal needs is T
gCLK× 2
h.Within the time completing the H rank pwm signal exported in one's own profession, need the input of the luma data of next line cascade, for preventing the data of input imperfect, demand fulfillment T
dCLK× C × M × P≤T
gCLK× 2
h.Moreover if the number of scanning lines is S, then counter 50 is when starting to carry out cycle count to image, first carries out first time 2
hcounting, then interval (2
h× T
gCLK+ T) × time of (S-1), continue second time 2
hcounting, and then one (2, interval
h× T
gCLK+ T) × time of (S-1) ... circulate successively, until complete 2
lsecondary 2
hcounting, just terminate the counting of an image complete cycle, the entire cycle time of an image is (2
h× T
gCLK+ T) × S × 2
l.
Fig. 3 be display drive circuit 100 in S line scanning situation, complete a width complete image pwm signal export waveform schematic diagram, to show that display drive circuit 100 carries out the driving process of data scanning and output.Wherein, in figure 3, for the number of scanning lines 1, whole section of original PWM waveform partition is become 2 by PWM signal generation unit 60
lindividual width is T
gCLK× 2
hpWM waveform.Equally, for the number of scanning lines 2, also whole section of original PWM waveform partition is become 2
lindividual width is T
gCLK× 2
hpWM waveform.By that analogy, until during number of scanning lines S, also whole section of original PWM waveform partition is become 2
lindividual width is T
gCLK× 2
hpWM waveform.First width in each scan line is T
gCLK× 2
hpWM waveform occur successively, the time interval (blanking time) that often between row, divided PWM waveform occurs is T.(2
h× T
gCLk+T), after × S time, first width completing all row is T
gCLK× 2
hthe array output of pwm signal.According to identical principle, second width carrying out all row is T
gCLK× 2
hthe array output of pwm signal, until carry out the 2nd of all row the
lindividual width is T
gCLK× 2
hthe array output of pwm signal terminate, just complete the complete output of piece image.In the present embodiment, the piece image data of display screen are the luma data value of input serial data signal (SDI) in driving circuit, and that is, the information being representative luma data value in image, when luma data value is larger, then represents brighter; Luma data is less, then represent darker.
The course of work of display drive circuit 100 of the present invention is described with specific embodiment below, but not to limit category of the present invention anyways.
In the present embodiment, setting data clock signal (DCLK) equals gray scale clock signal (GCLK), i.e. T
gCLKequal T
dCLK, and carry out 8 line scannings, line scanning interval time is T, and often row cascade 4 driving chip, every driving chip has 16 output channels, and input luma data is 16 rank.It can thus be appreciated that, in the present embodiment, because input luma data is 16 rank (high-order is 10, and low order is 6), then need the pwm signal on 16 rank to be divided into 64 1024 × T
gCLKgrayscale signal.Therefore, each output channel of driving chip needs to be set as 16 rank patterns, namely needs 16 luma data, and has 16 output channels due to every driving chip, then a driving chip needs input 256 luma data.Simultaneously every row cascade 4 driving chip, then, when line scanning, often row needs input 1024 luma data.The luma data of input serial data signal (SDI) carries out displacement input at the rising edge of data clock signal (DCLK), then the time that completing a line scanning t test needs is 1024 × T
dCLK, the time that completing 8 line scannings needs is 1024 × T
dCLK× 8.
Be appreciated that input serial data signal (SDI) also at the negative edge of data clock signal (DCLK), or can input at rising edge and negative edge simultaneously.
Introduce the course of work of counter 50 below.After 1024 serial gray scale data signal are input to the driving chip of 4 cascades by signal input unit 10, every cascade driving chip all needs to obtain 256 gray scale data signal, that is, the passage of each cascade driving chip obtains the luma data on 16 rank.Described 4 cascade driving chip, according to the data in status register 40, are determined that driving chip will carry out 8 line scannings, and the luma data on these 16 rank are divided into 64 1024 × T
gCLKpWM waveform.Therefore, counter 50 cycle of producing be 1024 counter 50 be worth, complete first time 1024 counting after, one the 8 × (1024 × T in interval
gCLK+ T) time, then to carry out the second time cycle be the counting of 1024, one the 8 × (1024 × T in interval more subsequently
gCLK+ T) time ..., the like, until completing the 64th cycle is the counting of 1024.
When carrying out the first row scanning, signal input unit 10 first completes the input of 1024 gray scale data signal of the first row, then carries out the scanning output of the first row by PWM signal generation unit 60, and namely carrying out the first row Data Segmentation is many groups 1024 × T
gCLK, and to first group of 1024 × T
gCLKcarry out the operation exported.While carrying out scan-data output, signal input unit 10 then inputs 1024 gray scale data signal of the second row.First group of 1024 × T is completed in the first row
gCLKsegmentation and be expert at sweep spacing time T after, start the scanning carrying out the second row, namely carry out first group of 1024 × T in the second row data cutting operation
gCLKoperation.By that analogy, until complete the input of 1024 gray scale data signal of eighth row in the 7th line scanning output procedure, then first group of 1024 × T is completed at the 7th row
gCLKwhen segmentation and line scanning interval after T, carrying out the scanning of eighth row, is also carry out first group of 1024 × T in the operation of eighth row Data Segmentation
gCLKoperation, just complete the output of assembled pulse width signal of 8 row segmentations after the time T of one, last interval.Owing to completing the input of 8 line scanning one width complete image luma data, next again carry out the scanning of the first row, carry out second group of 1024 × T in the operation of the first row Data Segmentation specifically
gCLKoperation, after having split, after interval time T, then carry out the scanning of the second row, and only carry out second group of 1024 × T in the second row data cutting operation
gCLKoperation ... until again carry out the scanning of eighth row, only carry out second group of 1024 × T in the operation of eighth row Data Segmentation
gCLKoperation, finally, after the time T of one, interval, namely complete the output of assembled pulse width signal of second time 8 row segmentation.According to this order, until complete 64 8 line scannings, the display of a width complete image just can be completed.According to explanation above, completing 8 line scannings needs input 1024 × 8 input serial data signals (SDI) altogether; And at 1024 × T
gCLKtime in, the data that needed next line to scan input, and this data entry time needs 1024 × T
dCLK, therefore, correct in order to ensure the input of data, require 1024 × T
gCLK>=1024 × T
dCLK.
Adopt the partition type pwm signal of 8 line scannings, the combination PWM time completing the segmentation of output 8 row is 8 × (1024+T) × T
gCLKif the frequency of gray scale clock signal (GCLK) is 20MHz, then screen refresh rate is about 2441Hz.Under the same conditions, adopt existing pwm signal driving chip, its screen refresh rate is about 38Hz.Can find out, the present invention significantly can improve the screen refresh rate of system when dynamic scan.
Be appreciated that and have employed 8 line scannings in the present embodiment, and in other embodiments, also can be any amount line scanning.Such as, if be 16 line scannings, then the refresh rate of screen is about 1220Hz.In light emitting diode (LED) display screen drive system, due to the significantly raising of system refresh rate, even if the number of scanning lines increases to some extent, also limited on the refresh rate impact of system.Meanwhile, due to the increase of the number of scanning lines, can increase by a chips and drive more light emitting diode number.
Generally speaking, the data of every piece image of light emitting display device are all input to display drive circuit 100 with serial data mode, display drive circuit 100 is by data controlling signal, and control data process and shift register 20 pass data in data register 30 and status register 40.Counter 50, under the status data of status register 40 controls, exports count value exactly and exports the pulse width modulating signal of segmentation according to count value.The time that completing a complete image in traditional dynamic scan screen system needs is (2
p× T
gCLK+ T) × S, then the refresh rate of screen is
the present invention have employed segmentation form owing to inputting PWM luma data, and the counter 50 of driving chip produces count value and interval time according to predetermined requirement, then the PWM gray scale data signal that the width complete image data exported just can regard input as is converted into 2
lthe pwm signal of individual segmentation group.And the pwm signal of each segmentation group, contain the pwm signal on often row H rank from the first row is capable to S, the time that often row switches is T, and like this, the time completing the pwm signal of an output segmentation group is (2
h× T
gCLK+ T) × S, that is the refresh rate of display screen system is
therefore, it is possible to the refresh rate of display screen is promoted about 2
ldoubly.
Refer to Fig. 4, it is the light emitting display device 200 that use 1 driving chip carries out driving, and described light emitting display device 200 separately comprises switchgear 101 and light emitting diode (LED) display screen 102.Light emitting diode (LED) display screen 102 needs to use under the cooperation of switchgear 101.Illustrate, light emitting diode (LED) display screen 102 can be divided into the first row light emitting diode, the second row light emitting diode ... and the capable light emitting diode of S.Switchgear 101 circulates the light emitting diode of conducting the first row successively, the second row light emitting diode ... light emitting diode capable of S, and the time interval often between row conducting is T.
When switchgear 101 be switched to S capable time, a driving chip of driving circuit 100 can export the drive singal of the capable light emitting diode of S, until during the capable signal end of output of S, all row are just closed by switchgear 101, described driving chip also stops output drive signal simultaneously, and this interval time is T.The principle of work of other each row is identical therewith.And in this cascade system, the driving circuit of rear class is identical with the first order with the principle of work of display screen.
Display drive circuit 100 of the present invention and adopt the light emitting display device 200 of described display drive circuit 100, take full advantage of the relation between the data transmission period of display drive circuit 100 and the pwm signal of segmentation, realize the refresh rate of elevator system while fine scanning data effectively input, and without the need to internal memory storing driver information, reduce cost and power consumption.
Above disclosedly be only a kind of preferred embodiment of the present invention, certainly can not limit the interest field of the present invention with this, therefore according to the equivalent variations that the claims in the present invention are done, still belong to the scope that the present invention is contained.
Claims (1)
1. a display drive circuit, it comprises:
Signal input unit, for input serial data input signal, gray scale clock signal, data clock signal and data controlling signal;
Data processing and shift register, be coupled to described signal input unit, for responding described data clock signal and data controlling signal and obtaining serial gray scale data and serial state data from described input serial data signal;
Data register, is coupled to described data processing and shift register, for receiving described serial gray scale data;
Status register, is coupled to described data processing and shift register, for storing a predetermined status data and receiving described serial state data;
Counter, is coupled to described status register, for producing a count value according to described predetermined status data, described serial state data and described gray scale clock signal; And
Pulse width modulating signal generation unit, is coupled to described data register and described counter, for the count value according to the serial gray scale data sum counter obtained from described data register, serial gray scale data is divided into
the pulse width modulating signal on individual H rank, wherein, the high-order exponent number of H indicating impulse bandwidth modulation signals, the low order exponent number of L indicating impulse bandwidth modulation signals also exports.
2. display drive circuit as claimed in claim 1, is characterized in that: described counter is according to formula:
calculate the time that the complete image with S the number of scanning lines completes dynamic scan needs, wherein,
represent export each divided after time of needing of pulse width modulating signal, T represents line scanning switching time, and S represents the number of scanning lines.
3. display drive circuit as claimed in claim 2, is characterized in that: when counter carries out scan period counting to piece image, first carry out first time
counting, then interval
time, continue second time
counting, and then one, interval
time, continue third time
counting, and to circulate successively, until complete
secondary
counting.
4. display drive circuit as claimed in claim 3, is characterized in that: the output time completing a line pulse width modulating signal has been more than or equal to the input time of next line serial gray scale data to be scanned.
5. display drive circuit as claimed in claim 1, is characterized in that: the state of described status register also for supplying user to set driving circuit, to obtain described predetermined status data.
6. display drive circuit as claimed in claim 1, it is characterized in that: described display drive circuit comprises the driving chip of multiple cascade, each driving chip comprises described signal input unit, data processing and a shift register, data register, status register, counter and pulse width modulating signal generation unit.
7. display drive circuit as claimed in claim 1, it is characterized in that: described signal input unit comprises serial data input, GTG input end of clock, data clock input end and data controlling signal input end, be respectively used to transmit described input serial data signal, gray scale clock signal, data clock signal and data controlling signal.
8. a light emitting display device, it at least comprises: light emitting diode (LED) display screen and the display drive circuit as described in any one of claim 1-7 item, this display drive circuit is coupled to described light emitting diode (LED) display screen, shows image to drive described light emitting diode (LED) display screen.
9. light emitting display device as claimed in claim 8, it is characterized in that: the output of described pulse width modulating signal generation unit is coupled to a constant current output passage, and pulse width modulating signal is input to described light emitting diode (LED) display screen from described constant current output passage.
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| CN102779480A (en) | 2012-11-14 |
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