CN102778910A - High voltage reference - Google Patents
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- CN102778910A CN102778910A CN2011101279352A CN201110127935A CN102778910A CN 102778910 A CN102778910 A CN 102778910A CN 2011101279352 A CN2011101279352 A CN 2011101279352A CN 201110127935 A CN201110127935 A CN 201110127935A CN 102778910 A CN102778910 A CN 102778910A
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- 239000003990 capacitor Substances 0.000 claims description 48
- 230000000694 effects Effects 0.000 claims description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
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- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000003139 buffering effect Effects 0.000 claims description 2
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Abstract
The invention provides a generation circuit of a high voltage reference, in particular to a generation circuit through a reference voltage with a feedback loop, wherein through the obtainment of the offset voltage (VOS) of an operational amplifier in the loop in advance, the feedback loop enables the gain through the feedback loop not to be affected by the VOS of the operational amplifier, so that the precision of output voltage is improved; and when a band-gap reference is used as the reference voltage, the high voltage reference with high precision can be obtained.
Description
Technical field
The present invention relates to the generation circuit of high voltage benchmark.Especially, it relates to a kind of generation circuit of the reference voltage with feedback control loop, offset voltage (Offset Voltage, the V of this feedback control loop through obtaining operational amplifier in this loop in advance
OS), make the offset voltage V that does not receive operational amplifier through the gain of this feedback control loop
OSInfluence, thereby improve the precision of output voltage, when adopting band-gap reference voltage for referencial use, can obtain the high-accuracy high voltage benchmark.
Background technology
As everyone knows, during band-gap reference voltage for referencial use, about 1.25V, in the plurality of applications occasion, this reference voltage is too little, can not satisfy most of demands usually for its output voltage.
The offset voltage V of operational amplifier
OSChange along with technology, voltage, temperature variation, therefore, because offset voltage V
OSExistence, the precision of the bandgap voltage reference Vout of output is had a strong impact on.
Summary of the invention:
The present invention proposes in order to solve aforementioned this problem, the present invention proposes a kind of offset voltage V that suppresses operational amplifier
OS, again through operational amplifier being connected into the method for negative-feedback amplifier, and, improve the output voltage range of band-gap reference with band-gap reference voltage for referencial use, realize the high voltage reference voltage generator that a kind of precision is high.High voltage benchmark provided by the invention comprises three kinds of basic structures, and first kind of basic structure comprises:
K switch 1A, its path terminal links to each other with input signal Vbg;
K switch 2A, its path terminal links to each other with input signal GND, and its another path terminal links to each other with another path terminal of K switch 1A;
Capacitor C 1, its battery lead plate links to each other with the path terminal that K switch 1A links to each other with K switch 2A;
Operational amplifier OPAM1, its right negative input end of difference input links to each other with another battery lead plate of capacitor C 1, and its right positive input terminal of difference input links to each other with input reference signal Vref;
K switch 1B, its path terminal links to each other with the right negative input end of difference input of operational amplifier OPAM1, and its another path terminal links to each other with the output terminal V0 of operational amplifier OPAM1;
Capacitor C 2, its battery lead plate links to each other with the right negative input end of difference input of operational amplifier OPAM1;
K switch 2B, its path terminal links to each other with the another one battery lead plate of capacitor C 2, and its another path terminal links to each other with the output terminal V0 of operational amplifier OPAM1;
K switch 1C, its path terminal links to each other with the another one battery lead plate of capacitor C 2, and links to each other with the path terminal of K switch 2B, and its another path terminal links to each other with input signal GND;
K switch 2c, its path terminal links to each other with the output terminal V0 of operational amplifier OPAM1;
Resistance R 0, its end links to each other with another path terminal of K switch 2c, and its other end links to each other with output signal VrefH0; Operational amplifier OPAM2, the right positive input terminal of its difference input links to each other with output signal VrefH0, and its right negative input end of difference input links to each other with the output terminal of itself, and links to each other with output signal VrefH1;
Capacitor C 3, its battery lead plate links to each other with output signal VrefH0, and its another one battery lead plate links to each other with input signal GND.
In first kind of basic structure of high voltage benchmark provided by the invention; Said K switch 1A, K switch 2A, K switch 1B, K switch 2B, K switch 1C, K switch 2C are by two inversion clocks or the clock control that do not overlap; Wherein said K switch 1A, K switch 1B, K switch 1C are one group of in-phase clock control; Said K switch 2A, K switch 2B, K switch 2C are other one group of in-phase clock control, and these two groups is two inversion clocks or the clock control that do not overlap; Its course of work is: said K switch 1A, K switch 1B, K switch 1C closed conducting under clock control, and said K switch 2A, K switch 2B, K switch 2C break off under another clock control, and the voltage at said capacitor C 1 two ends is (Vref+V
OS1-Vbg), V wherein
OS1Be the offset voltage between two differential input ends of said operational amplifier OPAM1, the voltage at said capacitor C 2 two ends is (Vref+V
OS1); Follow said K switch 1A, K switch 1B, K switch 1C and under clock control, break off, said K switch 2A, K switch 2B, K switch 2C closed conducting under another clock control, the voltage at said capacitor C 1 two ends is (Vref+V
OS1), the voltage at said capacitor C 2 two ends is (Vref+V
OS1-V0), obtaining V0=Vbg*C1/C2 this moment according to law of conservation of charge, simultaneously said capacitor C 3 samplings are the voltage of said operational amplifier OPAM1 output terminal V0 at this moment, and give output signal VrefH0 as output voltage; In order effectively to drive late-class circuit; Said operational amplifier OPAM2 outputs to signal VrefH1 as follower with said signal VrefH0 buffering; But voltage on the said signal VrefH0 and the voltage on the said signal VrefH1 have difference at this moment; Voltage on the said signal VrefH0 is Vbg*C1/C2, and the voltage on the said signal VrefH1 is (Vbg*C1/C2+V
OS2), V wherein
OS2Be the offset voltage between two differential input ends of said operational amplifier OPAM2, certainly compared with Vbg*C1/C2, V in most cases
OS2The error of introducing can be tolerated; Therefore, said signal Vbg is exaggerated and becomes Vbg*C1/C2, has amplified C1/C2 doubly, thereby makes the magnitude of voltage of reference voltage (band-gap reference or other reference voltage) improve C1/C2 doubly, and is only relevant with the value of C1/C2, and irrelevant with other factors.
Second kind of basic structure comprises:
Operational amplifier OPAM3, it comprises: single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K12, differential pair, single-pole double-throw switch (SPDT) K21, single-pole double-throw switch (SPDT) K22, first order load, second level amplifier OPAMb; Its right positive input terminal of difference input links to each other with a path of the double-throw end of single-pole double-throw switch (SPDT) K11, and its right negative input end of difference input links to each other with another path of the double-throw end of single-pole double-throw switch (SPDT) K11;
Single-pole double-throw switch (SPDT) K11, its hilted broadsword end links to each other with input voltage Vbg;
Single-pole double-throw switch (SPDT) K12; Its hilted broadsword end links to each other with node Vref2; A path of its double-throw end links to each other with the right negative input end of difference input of operational amplifier OPAM3, and another path of its double-throw end links to each other with the right positive input terminal of the difference of operational amplifier OPAM3 input;
Single-pole double-throw switch (SPDT) K21, its hilted broadsword end links to each other with an output terminal of differential pair;
Single-pole double-throw switch (SPDT) K22, its hilted broadsword end links to each other with another output terminal of differential pair;
First order load; Its input end links to each other with a path of the double-throw end of single-pole double-throw switch (SPDT) K21; And also link to each other with a path of the double-throw end of single-pole double-throw switch (SPDT) K22; Its another input end links to each other with another path of the double-throw end of single-pole double-throw switch (SPDT) K21, and also links to each other with another path of the double-throw end of single-pole double-throw switch (SPDT) K22;
Second level amplifier OPAMb, its positive input terminal links to each other with an output terminal of first order load, and its negative input end links to each other with another output terminal of first order load, and its output terminal links to each other with the output terminal of operational amplifier OPAM3;
Resistance R 1, its end links to each other with the output terminal V0 of operational amplifier OPAM3, and its other end links to each other with node Vref2;
Resistance R 2, its end links to each other with input signal GND, and its other end links to each other with node Vref2;
Resistance R 3, its end links to each other with the output terminal V0 of operational amplifier OPAM3, and its other end links to each other with output signal VrefH3;
Capacitor C 4, its battery lead plate links to each other with output signal VrefH3, and its other end links to each other with input signal GND.
In second kind of basic structure of high voltage benchmark provided by the invention, said first order load, its output terminal can be two, also can two be merged into an output terminal, determines according to application need; Said single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K21 and single-pole double-throw switch (SPDT) K12, single-pole double-throw switch (SPDT) K22 are by two inversion clocks or the clock control that do not overlap; Its course of work is: said single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K21 are the closed conducting of a path of its hilted broadsword end and double-throw end between high period at the clock period signal; And be connected respectively to the negative input end of described differential pair and an input end of said first order load; And the path closure conducting of said single-pole double-throw switch (SPDT) K12, single-pole double-throw switch (SPDT) K22 its hilted broadsword end and double-throw end under clock control simultaneously; And be connected respectively to the positive input terminal of said differential pair and another input end of said first order load; At the clock period signal is between low period; Its hilted broadsword end of said single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K21, single-pole double-throw switch (SPDT) K12, single-pole double-throw switch (SPDT) K22 breaks off with a path of the current double-throw end that links to each other; And link to each other with its another path of double-throw end; Because two input ends and two output terminals of said differential pair change simultaneously, substantial variation does not take place for the input of said first order load, thereby the output terminal of amplifier is not changed; The next clock period then; Get back to original state again, go round and begin again, yet in the state that this goes round and begins again; The offset voltage that offset voltage that said differential pair is introduced and said first order load are introduced all is cancelled; Can be to the output voltage generation effect of said operational amplifier OPAM3, and (gain of first order amplifier all surpasses more than the 20dB usually) more than at least 10 times dwindled in the gain of the first order amplifier OPAMa that the offset voltage that said second level amplifier OPAMb introduces has been formed by said differential pair and said first order load, thus contribute the offset voltage of whole said operational amplifier OPAM3 is not tangible.Like this not do not introduce receive two inversion clocks or said single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K21 and the single-pole double-throw switch (SPDT) K12 of the clock control that do not overlap, single-pole double-throw switch (SPDT) K22 before, the output voltage of said operational amplifier OPAM3 is V0=(1+R1/R2) (Vbg+V
OS3), V wherein
OS3It is the offset voltage of said operational amplifier OPAM3; And introducing receive two inversion clocks or said single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K21 and single-pole double-throw switch (SPDT) K12, the single-pole double-throw switch (SPDT) K22 of the clock control that do not overlap after; The output voltage of said operational amplifier OPAM3 is V0=(1+R1/R2) Vbg, wherein V
OS3Be the offset voltage of said operational amplifier OPAM3, significantly, output voltage V 0 precision of said operational amplifier OPAM3 has improved (1+R1/R2) V
OS3Voltage amplitude.
A concrete example of second kind of basic structure comprises:
P type metal oxide silicon MOS transistor (claiming the PMOS pipe later on) M1, its source electrode links to each other with node VDD, and its drain electrode links to each other with node IB, and its grid also links to each other with node IB;
PMOS manages M2, and its source electrode links to each other with node VDD, and its grid also links to each other with node IB;
PMOS manages M3, and its source electrode links to each other with node VDD, and its grid also links to each other with node IB;
Capacitor C 5, its end links to each other with node VDD, and its other end links to each other with node IB;
PMOS manages M4, and its source electrode links to each other with the drain electrode of PMOS pipe M2;
PMOS manages M5, and its source electrode links to each other with the drain electrode of PMOS pipe M2;
N type metal oxide silicon MOS transistor (claiming the NMOS pipe later on) NMOS manages M6, and its source electrode links to each other with the grid of PMOS pipe M4, and its drain electrode links to each other with input voltage Vbg, and its grid links to each other with input voltage O2;
NMOS manages M7, and its source electrode links to each other with the grid of PMOS pipe M5, and its drain electrode links to each other with input voltage Vbg, and its grid links to each other with input voltage O1;
NMOS manages M8, and its source electrode links to each other with the grid of PMOS pipe M4, and its drain electrode links to each other with input voltage Vref2, and its grid links to each other with input voltage O1;
NMOS manages M9, and its source electrode links to each other with the grid of PMOS pipe M5, and its drain electrode links to each other with input voltage Vref2, and its grid links to each other with input voltage O2;
NMOS manages M10, and its source electrode links to each other with the drain electrode of PMOS pipe M4, and its grid links to each other with input voltage O2;
NMOS manages M11, and its source electrode links to each other with the drain electrode of PMOS pipe M5, and its drain electrode links to each other with the drain electrode of NMOS pipe M10, and its grid links to each other with input voltage O1;
NMOS manages M12, and its source electrode links to each other with the drain electrode of PMOS pipe M4, and its grid links to each other with input voltage O1;
NMOS manages M13, and its source electrode links to each other with the drain electrode of PMOS pipe M5, and its drain electrode links to each other with the drain electrode of NMOS pipe M12, and its grid links to each other with input voltage O2;
NMOS manages M14, and its source electrode links to each other with node GND, and its drain electrode links to each other with the drain electrode of NMOS pipe M4, and its grid links to each other with the drain electrode of NMOS pipe M12, and the drain electrode of NMOS pipe M13 links to each other;
NMOS manages M15, and its source electrode links to each other with node GND, and its drain electrode links to each other with the drain electrode of NMOS pipe M5, and its grid links to each other with the drain electrode of NMOS pipe M12, and the drain electrode of NMOS pipe M13 links to each other;
NMOS manages M16, and its source electrode links to each other with node GND, and its grid links to each other with the drain electrode of NMOS pipe M10, and the drain electrode of NMOS pipe M11 is continuous, and its drain electrode links to each other with the drain electrode of PMOS pipe M3;
Resistance R c, its end links to each other with the drain electrode of NMOS pipe M10, and the drain electrode of NMOS pipe M11 links to each other;
Capacitor C c, its end links to each other with the other end of resistance R c, and its other end links to each other with the drain electrode of NMOS pipe M16, and links to each other with the drain electrode of PMOS pipe M3;
Resistance R 1, its end links to each other with node GND, and its other end links to each other with input voltage Vref2;
Resistance R 2, its end links to each other with the drain electrode of NMOS pipe M16, and its other end links to each other with input voltage Vref2;
Resistance R 3, its end links to each other with the drain electrode of NMOS pipe M16, and its other end links to each other with output voltage V refH3;
Capacitor C 4, its end links to each other with node GND, and its other end links to each other with output voltage V refH3.
In the concrete example of second kind of basic structure of high voltage benchmark provided by the invention; The voltage of said input signal O1 and O2 is by two inversion clocks or the clock control that do not overlap; When the voltage of input signal O1 when being high, the voltage of input signal O2 is low, and NMOS pipe M6, NMOS pipe M9, NMOS pipe M10, NMOS pipe M13 turn-off; NMOS pipe M7, NMOS pipe M8, NMOS pipe M11, NMOS pipe M12 conducting; Voltage Vbg is input to the grid that PMOS manages M5 through NMOS pipe M7, and voltage Vref2 is input to the grid that PMOS manages M4 through NMOS pipe M8, simultaneously; The drain electrode of NMOS pipe M15 is connected to the grid of NMOS pipe M16 through NMOS pipe M11; And link to each other with resistance R c, the drain electrode of NMOS pipe M14 is connected to the grid of NMOS pipe M14 through NMOS pipe M12, and links to each other with the grid of NMOS pipe M15; At this moment; The grid of PMOS pipe M5 is imported right positive input terminal as difference, and the grid of PMOS pipe M4 is as the right negative input end of difference input, and PMOS pipe M2, PMOS pipe M3, PMOS manage output voltage V 0=(1+R2/R1) Vref2=(the 1+R2/R1) (Vbg-V of the operational amplifier of M4, PMOS pipe M5, PMOS pipe M14, PMOS pipe M15, PMOS pipe M16, resistance R c, capacitor C c composition
OS), V wherein
OSOffset voltage for operational amplifier;
When the voltage of input signal O1 when low, the voltage of input signal O2 be high, NMOS pipe M6, NMOS pipe M9, NMOS pipe M10, NMOS manage the M13 conducting; NMOS pipe M7, NMOS pipe M8, NMOS pipe M11, NMOS pipe M12 turn-off; Voltage Vbg is input to the grid that PMOS manages M4 through NMOS pipe M6, and voltage Vref2 is input to the grid that PMOS manages M5 through NMOS pipe M9, simultaneously; The drain electrode of NMOS pipe M14 is connected to the grid of NMOS pipe M16 through NMOS pipe M10; And link to each other with resistance R c, the drain electrode of NMOS pipe M15 is connected to the grid of NMOS pipe M15 through NMOS pipe M13, and links to each other with the grid of NMOS pipe M14; At this moment; The grid of PMOS pipe M4 is imported right positive input terminal as difference, and the grid of PMOS pipe M5 is as the right negative input end of difference input, and PMOS pipe M2, PMOS pipe M3, PMOS manage output voltage V 0=(1+R2/R1) Vref2=(1+R2/R1) (Vbg-(V of the operational amplifier of M4, PMOS pipe M5, PMOS pipe M14, PMOS pipe M15, PMOS pipe M16, resistance R c, capacitor C c composition
OS)), V wherein
OSOffset voltage for operational amplifier; In one-period, if the dutycycle of input voltage O1 and input voltage O2 is near 50%, and the cycle is identical, then the output voltage V 0=of operational amplifier (1+R2/R1) (Vbg+V
OS(Vbg-(the V of)+(1+R2/R1)
OS))=1+R2/R1) Vbg, wherein V
OSBe the offset voltage of operational amplifier, promptly the output voltage V 0 of operational amplifier is directly proportional with input voltage Vbg, and irrelevant with the offset voltage of operational amplifier; When input voltage is the bandgap voltage reference in the integrated circuit, then the output voltage V 0 of operational amplifier also be bandgap voltage reference (1+R2/R1) doubly, only relevant, and have nothing to do with other factors with the value of R2/R1.
The third basic structure comprises:
K switch 7A, its a path termination node voltage Vref3
K switch 8A, its a path termination input voltage Vbg, another path terminal of its another path termination K switch 7A;
Capacitor C 6, its a terminated nodes voltage Vref3;
Operational amplifier OPAM4, its positive input terminal connects that path terminal that K switch 7A links to each other with K switch 8A, and its negative input end links to each other with the other end of capacitor C 6;
K switch 7B, the negative input end of its a path termination operational amplifier OPAM4, the output terminal of its another path termination operational amplifier OPAM4;
K switch 8B, the output terminal of its a path termination operational amplifier OPAM4;
Resistance R 4, another path terminal of its a termination K switch 8B, its another terminated nodes V1;
Capacitor C 7, its a terminated nodes voltage GND, its another terminated nodes V1;
NMOS manages MN, its source termination output voltage V refH4, and its drain terminal meets node VDD, and its grid meets node V1;
Resistance R 5, its a termination output voltage V refH4, its another terminated nodes Vref3;
Resistance R 6, its a terminated nodes GND, its another terminated nodes Vref3.
In the third basic structure of high voltage benchmark provided by the invention; Said K switch 7A, K switch 7B are by same clock control; Said K switch 8A, K switch 8B are by same other clock control; These two clocks are the inversion clock or the clock that do not overlap, and its course of work is: said K switch 7A, K switch 7B conducting under the clock effect, and said K switch 8A, K switch 8B break off under the clock effect simultaneously; Said operational amplifier OPAM4 is connected into the form of closed loop follower, and said capacitor C 6 voltage differences are the offset voltage V of said operational amplifier OPAM4
OS4When said K switch 7A, K switch 7B break off under the clock effect; Said K switch 8A, K switch 8B conducting under the clock effect simultaneously; The filtering circuit that said operational amplifier OPAM4 constitutes through said resistance R 4 and said capacitor C 7 drives said NMOS pipe MN; The source termination output voltage V refH4 of said NMOS pipe MN; Drive the dividing potential drop backfeed loop that said resistance R 5 and said resistance R 6 are connected into, the dividing potential drop Vref3 on the backfeed loop is connected to an end of said capacitor C 6, and said capacitor C 6 voltage differences are the offset voltage V of operational amplifier OPAM4
OS4And can not suddenly change, the voltage of the negative input end of said like this operational amplifier OPAM4 becomes Vref3+V
OS4, when loop stability was got off, the negative input end of said operational amplifier OPAM4 and positive input voltage difference were V
OS4, Vref3=Vbg is then arranged, thereby can obtain:
VrefH4=(1+R5/R6) Vref3=(1+R5/R6) Vbg; Be output voltage be input voltage Vbg (1+R5/R6) doubly; When input voltage is the bandgap voltage reference in the integrated circuit; Then the output voltage V refH4 of operational amplifier also be bandgap voltage reference (1+R5/R6) doubly, only relevant, and have nothing to do with other factors with the value of R5/R6.
High voltage benchmark according to claim 1; It is characterized in that; First kind of basic structure of said high voltage benchmark, second kind of basic structure, the third basic structure can be formed with discrete component; Also can form, can constitute, only need that appropriate section is done the general modification of industry and get final product by the integrated circuit of CMOS integrated circuit, Bipolar integrated circuit, BiCMOS integrated circuit, BCD integrated circuit and other kind by IC design; PMOS pipe wherein and NMOS pipe can be transformed into the transistor of igbt transistor, Bipolar transistor, DMOS transistor and other kind and their any combination, the respective change that corresponding Partial Jobs circle can be known.
Description of drawings
Will be better appreciated by following disclosed the present invention with reference to accompanying drawing, wherein:
Fig. 1 is first kind of basic structure circuit theory diagrams of high voltage benchmark
Fig. 2 is second kind of basic structure circuit theory diagrams of high voltage benchmark
Fig. 3 is concrete example circuit theory diagrams of second kind of basic structure of high voltage benchmark
Fig. 4 is the third basic structure circuit theory diagrams of high voltage benchmark
Embodiment
Investigate accompanying drawing now, Fig. 1 is for showing first kind of basic structure circuit theory diagrams of high voltage benchmark of the present invention.As shown in Figure 1; Said K switch 1A among the figure, K switch 2A, K switch 1B, K switch 2B, K switch 1C, K switch 2C are replaced with the NMOS pipe, and wherein the conduction terminal of switch is replaced by the source drain terminal of NMOS pipe, and control end is replaced by the grid of NMOS pipe; Two inversion clocks or the clock that do not overlap are controlled the grid of NMOS pipe respectively; When causing the NMOS pipe conducting of said K switch 1A, K switch 1B, K switch 1C correspondence, the NMOS pipe of said K switch 2A, K switch 2B, K switch 2C correspondence ends, and Vref1 can get (VDD-VSS)/2; This has just formed a kind of high voltage benchmark, and its value is Vbg*C1/C2.
Fig. 2 is for showing second kind of basic structure circuit theory diagrams of high voltage benchmark of the present invention, and Fig. 3 is for showing concrete example circuit theory diagrams of second kind of basic structure of high voltage benchmark of the present invention.As shown in Figure 3; NMOS pipe M6, NMOS pipe M9 form the said single-pole double-throw switch (SPDT) K11 of Fig. 2; NMOS pipe M7, NMOS pipe M8 form the said single-pole double-throw switch (SPDT) K12 of Fig. 2; NMOS pipe M10, NMOS pipe M13 form the said single-pole double-throw switch (SPDT) K21 of Fig. 2, and NMOS pipe M11, NMOS pipe M12 form the said single-pole double-throw switch (SPDT) K22 of Fig. 2.
Fig. 4 is for showing the third basic structure circuit theory diagrams of high voltage benchmark of the present invention.As shown in Figure 4; Said K switch 7A among the figure, K switch 7B, K switch 8A, K switch 8B are replaced with the NMOS pipe; Wherein the conduction terminal of switch is replaced by the source drain terminal of NMOS pipe, and control end is replaced by the grid of NMOS pipe, and two inversion clocks or the clock that do not overlap are controlled the grid of NMOS pipe respectively; When causing the NMOS pipe conducting of said K switch 7A, K switch 7B correspondence; Said K switch 8A, the NMOS pipe that K switch 8B is corresponding end, and this has just formed a kind of high voltage benchmark, and its value is Vbg* (1+R5/R6).
In addition; According to this instructions and Figure of description, and the general knowledge of this area, each functional circuit module of the present invention all has many circuit forms and structure; Their combination can form a lot of practical implementation examples; This instructions is no longer specifically enumerated at this, but as long as adopt system architecture of the present invention, just belongs to the scope that right of the present invention comprises.
As stated; The described three kinds of basic structure circuit of high voltage benchmark of the present invention; All exported the magnitude of voltage that is directly proportional with band-gap reference Vbg; The precision of these values is only relevant with the ratio of the ratio of electric capacity or resistance, under the relatively more significant situation of technology, voltage, temperature variation, realizes very high high voltage reference precision.
Claims (7)
1. a high voltage benchmark comprises three kinds of basic structures, and first kind of basic structure comprises:
K switch 1A, its path terminal links to each other with input signal Vbg;
K switch 2A, its path terminal links to each other with input signal GND, and its another path terminal links to each other with another path terminal of K switch 1A;
Capacitor C 1, its battery lead plate links to each other with the path terminal that K switch 1A links to each other with K switch 2A;
Operational amplifier OPAM1, its right negative input end of difference input links to each other with another battery lead plate of capacitor C 1, and its right positive input terminal of difference input links to each other with input reference signal Vref;
K switch 1B, its path terminal links to each other with the right negative input end of difference input of operational amplifier OPAM1, and its another path terminal links to each other with the output terminal V0 of operational amplifier OPAM1;
Capacitor C 2, its battery lead plate links to each other with the right negative input end of difference input of operational amplifier OPAM1;
K switch 2B, its path terminal links to each other with the another one battery lead plate of capacitor C 2, and its another path terminal links to each other with the output terminal V0 of operational amplifier OPAM1;
K switch 1C, its path terminal links to each other with the another one battery lead plate of capacitor C 2, and links to each other with the path terminal of K switch 2B, and its another path terminal links to each other with input signal GND;
K switch 2c, its path terminal links to each other with the output terminal V0 of operational amplifier OPAM1;
Resistance R 0, its end links to each other with another path terminal of K switch 2c, and its other end links to each other with output signal VrefH0; Operational amplifier OPAM2, the right positive input terminal of its difference input links to each other with output signal VrefH0, and its right negative input end of difference input links to each other with the output terminal of itself, and links to each other with output signal VrefH1;
Capacitor C 3, its battery lead plate links to each other with output signal VrefH0, and its another one battery lead plate links to each other with input signal GND;
Second kind of basic structure comprises:
Operational amplifier OPAM3, it comprises: single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K12, differential pair, single-pole double-throw switch (SPDT) K21, single-pole double-throw switch (SPDT) K22, first order load, second level amplifier OPAMb; Its right positive input terminal of difference input links to each other with a path of the double-throw end of single-pole double-throw switch (SPDT) K11, and its right negative input end of difference input links to each other with another path of the double-throw end of single-pole double-throw switch (SPDT) K11;
Single-pole double-throw switch (SPDT) K11, its hilted broadsword end links to each other with input voltage Vbg;
Single-pole double-throw switch (SPDT) K12; Its hilted broadsword end links to each other with node Vref2; A path of its double-throw end links to each other with the right negative input end of difference input of operational amplifier OPAM3, and another path of its double-throw end links to each other with the right positive input terminal of the difference of operational amplifier OPAM3 input;
Single-pole double-throw switch (SPDT) K21, its hilted broadsword end links to each other with an output terminal of differential pair;
Single-pole double-throw switch (SPDT) K22, its hilted broadsword end links to each other with another output terminal of differential pair;
First order load; Its input end links to each other with a path of the double-throw end of single-pole double-throw switch (SPDT) K21; And also link to each other with a path of the double-throw end of single-pole double-throw switch (SPDT) K22; Its another input end links to each other with another path of the double-throw end of single-pole double-throw switch (SPDT) K21, and also links to each other with another path of the double-throw end of single-pole double-throw switch (SPDT) K22;
Second level amplifier OPAMb, its positive input terminal links to each other with an output terminal of first order load, and its negative input end links to each other with another output terminal of first order load, and its output terminal links to each other with the output terminal of operational amplifier OPAM3;
Resistance R 1, its end links to each other with the output terminal V0 of operational amplifier OPAM3, and its other end links to each other with node Vref2;
Resistance R 2, its end links to each other with input signal GND, and its other end links to each other with node Vref2;
Resistance R 3, its end links to each other with the output terminal V0 of operational amplifier OPAM3, and its other end links to each other with output signal VrefH3;
Capacitor C 4, its battery lead plate links to each other with output signal VrefH3, and its other end links to each other with input signal GND; The third basic structure comprises:
K switch 7A, its a path termination node voltage Vref3;
K switch 8A, its a path termination input voltage Vbg, another path terminal of its another path termination K switch 7A;
Capacitor C 6, its a terminated nodes voltage Vref3;
Operational amplifier OPAM4, its positive input terminal connects that path terminal that K switch 7A links to each other with K switch 8A, and its negative input end links to each other with the other end of capacitor C 6;
K switch 7B, the negative input end of its a path termination operational amplifier OPAM4, the output terminal of its another path termination operational amplifier OPAM4;
K switch 8B, the output terminal of its a path termination operational amplifier OPAM4;
Resistance R 4, another path terminal of its a termination K switch 8B, its another terminated nodes V1;
Capacitor C 7, its a terminated nodes voltage GND, its another terminated nodes V1;
NMOS manages MN, its source termination output voltage V refH4, and its drain terminal meets node VDD, and its grid meets node V1;
Resistance R 5, its a termination output voltage V refH4, its another terminated nodes Vref3;
Resistance R 6, its a terminated nodes GND, its another terminated nodes Vref3.
2. according to the said high voltage benchmark of claim 1; It is characterized in that; In first kind of basic structure of high voltage benchmark provided by the invention; Said K switch 1A, K switch 2A, K switch 1B, K switch 2B, K switch 1C, K switch 2C are by two inversion clocks or the clock control that do not overlap; Wherein said K switch 1A, K switch 1B, K switch 1C are one group of in-phase clock control, and said K switch 2A, K switch 2B, K switch 2C are other one group of in-phase clock control, and these two groups is two inversion clocks or the clock control that do not overlap; Its course of work is: said K switch 1A, K switch 1B, K switch 1C closed conducting under clock control, and said K switch 2A, K switch 2B, K switch 2C break off under another clock control, and the voltage at said capacitor C 1 two ends is (Vref+V
OS1-Vbg), V wherein
OS1Be the offset voltage between two differential input ends of said operational amplifier OPAM1, the voltage at said capacitor C 2 two ends is (Vref+V
OS1); Follow said K switch 1A, K switch 1B, K switch 1C and under clock control, break off, said K switch 2A, K switch 2B, K switch 2C closed conducting under another clock control, the voltage at said capacitor C 1 two ends is (Vref+V
OS1), the voltage at said capacitor C 2 two ends is (Vref+V
OS1-V0), obtaining V0=Vbg*C1/C2 this moment according to law of conservation of charge, simultaneously said capacitor C 3 samplings are the voltage of said operational amplifier OPAM1 output terminal V0 at this moment, and give output signal VrefH0 as output voltage; In order effectively to drive late-class circuit; Said operational amplifier OPAM2 outputs to signal VrefH1 as follower with said signal VrefH0 buffering; But voltage on the said signal VrefH0 and the voltage on the said signal VrefH1 have difference at this moment; Voltage on the said signal VrefH0 is Vbg*C1/C2, and the voltage on the said signal VrefH1 is (Vbg*C1/C2+V
OS2), V wherein
OS2Be the offset voltage between two differential input ends of said operational amplifier OPAM2, certainly compared with Vbg*C1/C2, V in most cases
OS2The error of introducing can be tolerated; Therefore, said signal Vbg is exaggerated and becomes Vbg*C1/C2, has amplified C1/C2 doubly, thereby makes the magnitude of voltage of reference voltage (band-gap reference or other reference voltage) improve C1/C2 doubly, and is only relevant with the value of C1/C2, and irrelevant with other factors.
3. according to the said high voltage benchmark of claim 1, it is characterized in that, in second kind of basic structure of high voltage benchmark provided by the invention; Said first order load; Its output terminal can be two, also can two be merged into an output terminal, determines according to application need; Said single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K21 and single-pole double-throw switch (SPDT) K12, single-pole double-throw switch (SPDT) K22 are by two inversion clocks or the clock control that do not overlap; Its course of work is: said single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K21 are the closed conducting of a path of its hilted broadsword end and double-throw end between high period at the clock period signal; And be connected respectively to the negative input end of described differential pair and an input end of said first order load; And the path closure conducting of said single-pole double-throw switch (SPDT) K12, single-pole double-throw switch (SPDT) K22 its hilted broadsword end and double-throw end under clock control simultaneously; And be connected respectively to the positive input terminal of said differential pair and another input end of said first order load; At the clock period signal is between low period; Its hilted broadsword end of said single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K21, single-pole double-throw switch (SPDT) K12, single-pole double-throw switch (SPDT) K22 breaks off with a path of the current double-throw end that links to each other; And link to each other with its another path of double-throw end; Because two input ends and two output terminals of said differential pair change simultaneously, substantial variation does not take place for the input of said first order load, thereby the output terminal of amplifier is not changed; The next clock period then; Get back to original state again, go round and begin again, yet in the state that this goes round and begins again; The offset voltage that offset voltage that said differential pair is introduced and said first order load are introduced all is cancelled; Can be to the output voltage generation effect of said operational amplifier OPAM3, and (gain of first order amplifier all surpasses more than the 20dB usually) more than at least 10 times dwindled in the gain of the first order amplifier OPAMa that the offset voltage that said second level amplifier OPAMb introduces has been formed by said differential pair and said first order load, thus contribute the offset voltage of whole said operational amplifier OPAM3 is not tangible; Like this not do not introduce receive two inversion clocks or said single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K21 and the single-pole double-throw switch (SPDT) K12 of the clock control that do not overlap, single-pole double-throw switch (SPDT) K22 before, the output voltage of said operational amplifier OPAM3 is V0=(1+R1/R2) (Vbg+V
OS3), V wherein
OS3It is the offset voltage of said operational amplifier OPAM3; And introducing receive two inversion clocks or said single-pole double-throw switch (SPDT) K11, single-pole double-throw switch (SPDT) K21 and single-pole double-throw switch (SPDT) K12, the single-pole double-throw switch (SPDT) K22 of the clock control that do not overlap after; The output voltage of said operational amplifier OPAM3 is V0=(1+R1/R2) Vbg, wherein V
OS3Be the offset voltage of said operational amplifier OPAM3, significantly, output voltage V 0 precision of said operational amplifier OPAM3 has improved (1+R1/R2) V
OS3Voltage amplitude.
4. according to the said high voltage benchmark of claim 1, it is characterized in that a concrete example of said second kind of basic structure comprises:
P type metal oxide silicon MOS transistor (claiming the PMOS pipe later on) M1, its source electrode links to each other with node VDD, and its drain electrode links to each other with node IB, and its grid also links to each other with node IB;
PMOS manages M2, and its source electrode links to each other with node VDD, and its grid also links to each other with node IB;
PMOS manages M3, and its source electrode links to each other with node VDD, and its grid also links to each other with node IB;
Capacitor C 5, its end links to each other with node VDD, and its other end links to each other with node IB;
PMOS manages M4, and its source electrode links to each other with the drain electrode of PMOS pipe M2;
PMOS manages M5, and its source electrode links to each other with the drain electrode of PMOS pipe M2;
N type metal oxide silicon MOS transistor (claiming the NMOS pipe later on) NMOS manages M6, and its source electrode links to each other with the grid of PMOS pipe M4, and its drain electrode links to each other with input voltage Vbg, and its grid links to each other with input voltage O2;
NMOS manages M7, and its source electrode links to each other with the grid of PMOS pipe M5, and its drain electrode links to each other with input voltage Vbg, and its grid links to each other with input voltage O1;
NMOS manages M8, and its source electrode links to each other with the grid of PMOS pipe M4, and its drain electrode links to each other with input voltage Vref2, and its grid links to each other with input voltage O1;
NMOS manages M9, and its source electrode links to each other with the grid of PMOS pipe M5, and its drain electrode links to each other with input voltage Vref2, and its grid links to each other with input voltage O2;
NMOS manages M10, and its source electrode links to each other with the drain electrode of PMOS pipe M4, and its grid links to each other with input voltage O2;
NMOS manages M11, and its source electrode links to each other with the drain electrode of PMOS pipe M5, and its drain electrode links to each other with the drain electrode of NMOS pipe M10, and its grid links to each other with input voltage O1;
NMOS manages M12, and its source electrode links to each other with the drain electrode of PMOS pipe M4, and its grid links to each other with input voltage O1;
NMOS manages M13, and its source electrode links to each other with the drain electrode of PMOS pipe M5, and its drain electrode links to each other with the drain electrode of NMOS pipe M12, and its grid links to each other with input voltage O2;
NMOS manages M14, and its source electrode links to each other with node GND, and its drain electrode links to each other with the drain electrode of NMOS pipe M4, and its grid links to each other with the drain electrode of NMOS pipe M12, and the drain electrode of NMOS pipe M13 links to each other;
NMOS manages M15, and its source electrode links to each other with node GND, and its drain electrode links to each other with the drain electrode of NMOS pipe M5, and its grid links to each other with the drain electrode of NMOS pipe M12, and the drain electrode of NMOS pipe M13 links to each other;
NMOS manages M16, and its source electrode links to each other with node GND, and its grid links to each other with the drain electrode of NMOS pipe M10, and the drain electrode of NMOS pipe M11 is continuous, and its drain electrode links to each other with the drain electrode of PMOS pipe M3;
Resistance R c, its end links to each other with the drain electrode of NMOS pipe M10, and the drain electrode of NMOS pipe M11 links to each other;
Capacitor C c, its end links to each other with the other end of resistance R e, and its other end links to each other with the drain electrode of NMOS pipe M16, and links to each other with the drain electrode of PMOS pipe M3;
Resistance R 1, its end links to each other with node GND, and its other end links to each other with input voltage Vref2;
Resistance R 2, its end links to each other with the drain electrode of NMOS pipe M16, and its other end links to each other with input voltage Vref2;
Resistance R 3, its end links to each other with the drain electrode of NMOS pipe M16, and its other end links to each other with output voltage V refH3;
Capacitor C 4, its end links to each other with node GND, and its other end links to each other with output voltage V refH3.
5. according to the said high voltage benchmark of claim 1, it is characterized in that, in the concrete example of second kind of basic structure of said high voltage benchmark provided by the invention; The voltage of said input signal O1 and O2 is by two inversion clocks or the clock control that do not overlap; When the voltage of input signal O1 when being high, the voltage of input signal O2 is low, and NMOS pipe M6, NMOS pipe M9, NMOS pipe M10, NMOS pipe M13 turn-off; NMOS pipe M7, NMOS pipe M8, NMOS pipe M11, NMOS pipe M12 conducting; Voltage Vbg is input to the grid that PMOS manages M5 through NMOS pipe M7, and voltage Vref2 is input to the grid that PMOS manages M4 through NMOS pipe M8, simultaneously; The drain electrode of NMOS pipe M15 is connected to the grid of NMOS pipe M16 through NMOS pipe M11; And link to each other with resistance R c, the drain electrode of NMOS pipe M14 is connected to the grid of NMOS pipe M14 through NMOS pipe M12, and links to each other with the grid of NMOS pipe M15; At this moment; The grid of PMOS pipe M5 is imported right positive input terminal as difference, and the grid of PMOS pipe M4 is as the right negative input end of difference input, and PMOS pipe M2, PMOS pipe M3, PMOS manage output voltage V 0=(1+R2/R1) Vref2=(the 1+R2/R1) (Vbg-V of the operational amplifier of M4, PMOS pipe M5, PMOS pipe M14, PMOS pipe M15, PMOS pipe M16, resistance R c, capacitor C c composition
OS), V wherein
OSOffset voltage for operational amplifier;
When the voltage of input signal O1 when low, the voltage of input signal O2 be high, NMOS pipe M6, NMOS pipe M9, NMOS pipe M10, NMOS manage the M13 conducting; NMOS pipe M7, NMOS pipe M8, NMOS pipe M11, NMOS pipe M12 turn-off; Voltage Vbg is input to the grid that PMOS manages M4 through NMOS pipe M6, and voltage Vref2 is input to the grid that PMOS manages M5 through NMOS pipe M9, simultaneously; The drain electrode of NMOS pipe M14 is connected to the grid of NMOS pipe M16 through NMOS pipe M10; And link to each other with resistance R c, the drain electrode of NMOS pipe M15 is connected to the grid of NMOS pipe M15 through NMOS pipe M13, and links to each other with the grid of NMOS pipe M14; At this moment; The grid of PMOS pipe M4 is imported right positive input terminal as difference, and the grid of PMOS pipe M5 is as the right negative input end of difference input, and PMOS pipe M2, PMOS pipe M3, PMOS manage output voltage V 0=(1+R2/R1) Vref2=(1+R2/R1) (Vbg-(V of the operational amplifier of M4, PMOS pipe M5, PMOS pipe M14, PMOS pipe M15, PMOS pipe M16, resistance R c, capacitor C c composition
OS)), V wherein
OSOffset voltage for operational amplifier; In one-period, if the dutycycle of input voltage O1 and input voltage O2 is near 50%, and the cycle is identical, then the output voltage V 0=of operational amplifier (1+R2/R1) (Vbg+V
OS(Vbg-(the V of)+(1+R2/R1)
OS))=1+R2/R1) Vbg, wherein V
OSBe the offset voltage of operational amplifier, promptly the output voltage V 0 of operational amplifier is directly proportional with input voltage Vbg, and irrelevant with the offset voltage of operational amplifier; When input voltage is the bandgap voltage reference in the integrated circuit, then the output voltage V 0 of operational amplifier also be bandgap voltage reference (1+R2/R1) doubly, only relevant, and have nothing to do with other factors with the value of R2/R1.
6. according to the said high voltage benchmark of claim 1; It is characterized in that in the third basic structure of high voltage benchmark provided by the invention, said K switch 7A, K switch 7B are by same clock control; Said K switch 8A, K switch 8B are by same other clock control; These two clocks are the inversion clock or the clock that do not overlap, and its course of work is: said K switch 7A, K switch 7B conducting under the clock effect, and said K switch 8A, K switch 8B break off under the clock effect simultaneously; Said operational amplifier OPAM4 is connected into the form of closed loop follower, and said capacitor C 6 voltage differences are the offset voltage V of said operational amplifier OPAM4
OS4When said K switch 7A, K switch 7B break off under the clock effect; Said K switch 8A, K switch 8B conducting under the clock effect simultaneously; The filtering circuit that said operational amplifier OPAM4 constitutes through said resistance R 4 and said capacitor C 7 drives said NMOS pipe MN; The source termination output voltage V refH4 of said NMOS pipe MN; Drive the dividing potential drop backfeed loop that said resistance R 5 and said resistance R 6 are connected into, the dividing potential drop Vref3 on the backfeed loop is connected to an end of said capacitor C 6, and said capacitor C 6 voltage differences are the offset voltage V of operational amplifier OPAM4
OS4And can not suddenly change, the voltage of the negative input end of said like this operational amplifier OPAM4 becomes Vref3+V
OS4, when loop stability was got off, the negative input end of said operational amplifier OPAM4 and positive input voltage difference were V
OS4, Vref3=Vbg is then arranged, thereby can obtain:
VrefH4=(1+R5/R6) Vref3=(1+R5/R6) Vbg; Be output voltage be input voltage Vbg (1+R5/R6) doubly; When input voltage is the bandgap voltage reference in the integrated circuit; Then the output voltage V refH4 of operational amplifier also be bandgap voltage reference (1+R5/R6) doubly, only relevant, and have nothing to do with other factors with the value of R5/R6.
7. high voltage benchmark according to claim 1; It is characterized in that; First kind of basic structure of said high voltage benchmark, second kind of basic structure, the third basic structure can be formed with discrete component; Also can form, can constitute, only need that appropriate section is done the general modification of industry and get final product by the integrated circuit of CMOS integrated circuit, Bipolar integrated circuit, BiCMOS integrated circuit, BCD integrated circuit and other kind by IC design; PMOS pipe wherein and NMOS pipe can be transformed into the transistor of igbt transistor, Bipolar transistor, DMOS transistor and other kind and their any combination, the respective change that corresponding Partial Jobs circle can be known.
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| CN104460803A (en) * | 2014-12-01 | 2015-03-25 | 无锡中星微电子有限公司 | Band-gap reference voltage generating circuit |
| CN109643139A (en) * | 2018-11-16 | 2019-04-16 | 深圳市汇顶科技股份有限公司 | A kind of impedance adjustment circuit, chip and generating circuit from reference voltage |
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Application publication date: 20121114 |