CN102749779B - Pixel array substrate, display panel, contact window structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a pixel array substrate, a display panel, a contact window structure and a manufacturing method thereof. The contact window structure includes a first conductor layer, a first insulation layer, a second insulation layer and a second conductor layer. The first insulation layer covers the first conductor layer and a substrate, and has a first contact window. The second insulation layer covers the first insulation layer and has a second contact window. The second conductor layer covers the first contact window and the second contact window, and contacts the portion of the first conductor layer exposed to the first contact window. The first insulating layer and the second insulating layer are made of different materials. For the same etching liquid, the etching rate of the first insulating layer is greater than the etching rate of the second insulating layer. The etching rate of the portion of the second insulating layer close to the first insulating layer is greater than the etching rate of the portion of the second insulating layer far away from the first insulating layer. To sum up, the present invention can improve the yield of the contact window structure and ensure the integrity of the subsequently formed material layer, thereby improving the reliability of the product.

Description

Pixel array substrate, display panel, contact window structure and manufacturing method thereof

technical field

The invention relates to a pixel array substrate, a display panel, a contact window structure and a manufacturing method thereof, in particular to a pixel array substrate, a display panel, a contact window structure and a manufacturing method thereof with good yield.

Background technique

In the semiconductor process, it is often necessary to form a contact window (Contact Window) structure in an insulating insulating layer to connect the upper and lower conductive layers, or to connect the semiconductor substrate and the lower conductive layer.

FIG. 1 is a known contact window structure. In order to enable the first conductive layer 140 and the second conductive layer 170 to be electrically connected, after the first conductive layer 140 is covered with the first insulating layer 150 and the second insulating layer 160 in sequence, contact windows are formed by etching. 100A. After that, the second conductive layer 170 is covered. However, the first insulating layer 150 and the second insulating layer 160 are made of different materials, so the etching rate of the first insulating layer 150 is greater than that of the second insulating layer 160 in the etching process. In this way, because the first insulating layer 150 is etched quickly, a part of the second insulating layer 160 covering it has not been etched yet, and this part will hang above the first insulating layer 150 . Therefore, the subsequently formed second conductive layer 170 cannot completely cover the contact window 100A, causing problems in the reliability of the second conductive layer 170 .

In addition, the second conductive layer 170 may be covered with another two conductive layers and an insulating layer to serve as capacitors. However, the floating part of the second insulating layer 160 will cause the same problem of floating in the subsequent covered insulating layer, resulting in the conduction of the two conductive layers that should be insulated from each other as the upper and lower electrodes of the capacitor, and finally making the capacitor invalid.

Contents of the invention

In order to overcome the defects of the prior art, the present invention provides a contact window structure, which can solve the problem that the insulating layer is suspended.

The invention provides a pixel array substrate and a display panel, which can solve the problem of poor yield.

The invention provides a method for manufacturing a contact window structure, which can solve the problem that the insulating layer is suspended.

The invention provides a contact window structure, which includes a first conductor layer, a first insulation layer, a second insulation layer and a second conductor layer. The first conductive layer is configured on a substrate. The first insulating layer covers the first conductive layer and the substrate, and has a first contact window. Wherein a part of the first conductor layer is exposed to the first contact window. The second insulating layer covers the first insulating layer and has a second contact window, wherein the first contact window is exposed to the second contact window. The material of the first insulating layer is different from that of the second insulating layer. For the same etchant, the etching rate of the first insulating layer is greater than that of the second insulating layer, and the etching rate of the part of the second insulating layer close to the first insulating layer is greater than that of the part of the second insulating layer far away from the first insulating layer is etched rate. The second conductive layer covers the first contact hole and the second contact hole, and contacts the portion of the first conductive layer exposed to the first contact hole.

The present invention provides a pixel array substrate, which includes the aforementioned contact window structure.

The present invention provides a display panel, which includes a pair of facing substrates, a display medium and the aforementioned pixel array substrate. The display medium is disposed between the opposite substrate and the pixel array substrate.

In an embodiment of the present invention, the material of the first insulating layer of the contact window structure is silicon oxide.

In an embodiment of the present invention, the material of the second insulating layer of the above-mentioned contact window structure is silicon nitride, and the nitrogen-silicon ratio of the part of the second insulating layer close to the first insulating layer is greater than that of the second insulating layer farther away from the first insulating layer. Nitrogen-silicon ratio of part of the layer.

In an embodiment of the present invention, in the above-mentioned contact window structure, for the same etchant, the etching rate of the second insulating layer changes gradually from a portion close to the first insulating layer to a portion far away from the first insulating layer.

In an embodiment of the present invention, in the above-mentioned contact window structure, for the same etchant, the etching rate of the second insulating layer changes in two stages from a portion close to the first insulating layer to a portion far away from the first insulating layer.

In an embodiment of the present invention, the above-mentioned contact window structure further includes a first transparent conductive layer, a second transparent conductive layer, and a third insulating layer. The first transparent conductive layer covers and contacts the second conductive layer. The third insulating layer is disposed between the first transparent conductive layer and the second transparent conductive layer to form a capacitor.

In an embodiment of the present invention, the above-mentioned pixel array substrate further includes a plurality of pixel driving units. Each pixel driving unit includes a pixel electrode and a pair of counter electrodes. The pixel electrode has a plurality of first strip patterns, the opposite electrode has a plurality of second strip patterns, and the first strip patterns and the second strip patterns are arranged alternately. The opposite electrode and the pixel electrode are electrically insulated from each other.

In an embodiment of the present invention, the pixel electrode and the counter electrode of the pixel driving unit of the above-mentioned pixel array substrate are located on the same plane.

In an embodiment of the present invention, the pixel electrode and the counter electrode of the pixel driving unit of the above-mentioned pixel array substrate are located on different planes.

In an embodiment of the present invention, the above-mentioned pixel array substrate further includes a plurality of pixel driving units, and each pixel driving unit includes a pixel electrode and a pair of counter electrodes. The pixel electrode has a plurality of first strip patterns and is located on the same plane, the opposite electrode is located below the pixel electrode, and the pixel electrode and the opposite electrode are electrically insulated from each other.

The invention provides a method for manufacturing a contact window structure, which includes the following steps. Firstly, a first conductor layer is formed on a substrate. Then a first insulating layer is formed to cover the first conductor layer and the substrate. After that, a second insulating layer is formed to cover the first insulating layer. Wherein, the material of the first insulating layer is different from that of the second insulating layer. For the same etchant, the etching rate of the first insulating layer is greater than that of the second insulating layer. In the second insulating layer, a portion close to the first insulating layer is etched at a rate greater than a portion far from the first insulating layer. After forming the first insulating layer and the second insulating layer, etching the first insulating layer and the second insulating layer to form a first contact window in the first insulating layer and a second contact window in the second insulating layer . Wherein, a part of the first conductor layer is exposed to the first contact window, and the first contact window is exposed to the second contact window. Finally, a second conductive layer is formed to cover the first contact hole and the second contact hole, and to contact the part of the first conductive layer exposed to the first contact hole.

In an embodiment of the present invention, in the method for manufacturing the above-mentioned contact window structure, the method for forming the second insulating layer includes performing a chemical vapor deposition process using silane and ammonia gas, and reducing the amount of ammonia during the chemical vapor deposition process. The ratio of gas to silane.

In one embodiment of the present invention, in the above-mentioned manufacturing method of the contact window structure, during the chemical vapor deposition process, the ratio of ammonia gas to silane in the first stage is seven to one, and the ratio of ammonia gas to silane in the second stage is The ratio is three to one.

In an embodiment of the present invention, in the above method of manufacturing the contact window structure, during the chemical vapor deposition process, the ratio of ammonia gas to silane is lowered gradually.

In an embodiment of the present invention, in the above method of manufacturing the contact window structure, the method of etching the first insulating layer and the second insulating layer includes first performing dry etching and then performing wet etching.

In an embodiment of the present invention, the above-mentioned method for manufacturing the contact window structure further includes performing the following steps after forming the second conductor layer. A first transparent conductive layer is formed to cover and contact the second conductive layer. A third insulating layer is formed to cover the first transparent conductive layer. A second transparent conductive layer is formed on the third insulating layer to form a capacitor.

Based on the above, in the pixel array substrate, display panel, contact window structure and manufacturing method thereof of the present invention, the etching rate of the second insulating layer of the contact window structure near the first insulating layer is relatively similar to that of the first insulating layer . In this way, the yield of the contact structure can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a known contact window structure.

FIG. 2 is a schematic cross-sectional view of a display panel according to the first embodiment of the present invention.

FIG. 3 is a partial top view of the pixel array substrate in FIG. 2 .

Fig. 4 is a cross-sectional view of the pixel array substrate in Fig. 3 along line AA'.

5A to 5F are schematic cross-sectional flow charts of the manufacturing method of the contact window structure of FIG. 4 .

FIG. 6 is a schematic cross-sectional view of a display panel according to a second embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a display panel according to a third embodiment of the present invention.

FIG. 8 is a partial top view of the pixel array substrate of FIG. 7 .

Wherein, the reference signs are explained as follows:

100A: contact window

100, 231: contact window structure

110, 2311: Substrate

120: buffer layer

130, 2319: third insulating layer

140, 2316: first conductor layer

150, 2315: first insulating layer

160, 2317: second insulating layer

170, 2318: second conductor layer

200, 300, 400: display panel

210: opposite substrate

220: display media

230, 330, 430: pixel array substrate

2312: The first buffer layer

2313: Second buffer layer

2314: fourth insulating layer

2315a: first contact window

2317a: Second contact window

231a: first transparent conductive layer

231b: second transparent conductive layer

232, 432: pixel drive unit

2321, 3321, 4321: pixel electrodes

2321a, 4321a: first bar pattern

2322, 3322, 4322: Counter electrode

2322a: Second bar pattern

Detailed ways

FIG. 2 is a schematic cross-sectional view of a display panel according to the first embodiment of the present invention. Some components are omitted in FIG. 2 to clarify the drawing. Please refer to Figure 2 first. The display panel 200 includes a facing substrate 210 , a display medium 220 , and a pixel array substrate 230 . The display medium 220 is, for example, liquid crystal molecules, and is disposed between the opposite substrate 210 and the pixel array substrate 230 . The opposite substrate 210 is, for example, a color filter, a color filter substrate with red, green and blue color filter films (not shown in FIG. 2 ) or a colorless transparent glass substrate.

FIG. 3 is a partial top view of the pixel array substrate in FIG. 2 . Fig. 4 is a cross-sectional view of the pixel array substrate in Fig. 3 along line AA'. As shown in FIG. 3 , the pixel array substrate 230 includes a contact window structure 231 . Please refer to FIG. 4 , the contact structure 231 includes a first conductive layer 2316 , a first insulating layer 2315 , a second insulating layer 2317 and a second conductive layer 2318 . The first conductive layer 2316 is disposed on a substrate 2311 . The first insulating layer 2315 covers the first conductive layer 2316 and the substrate 2311, and has a first contact window 2315a. Wherein, a part of the first conductive layer 2316 is exposed to the first contact window 2315a. The second insulating layer 2317 covers the first insulating layer 2315 and has a second contact window 2317a. The first contact window 2315a is exposed to the second contact window 2317a. The second conductive layer 2318 covers the first contact window 2315a and the second contact window 2317a, and contacts the portion of the first conductive layer 2316 exposed to the first contact window 2315a.

The material of the first insulating layer 2315 is different from that of the second insulating layer 2317 . For the same etchant, the etching rate of the first insulating layer 2315 is greater than that of the second insulating layer 2317 . In the second insulating layer 2317 , the etched rate of the portion close to the first insulating layer 2315 is greater than the etched rate of the portion of the second insulating layer 2317 far from the first insulating layer 2315 . In other words, compared to the etching rate of the portion of the second insulating layer 2317 far away from the first insulating layer 2315, the etching rate of the portion of the second insulating layer 2317 close to the first insulating layer 2315 will be closer to the etching rate of the first insulating layer 2315. rate. Therefore, after etching the first insulating layer 2315 and the second insulating layer 2317, the junction of the first insulating layer 2315 and the second insulating layer 2317 will be more continuous after being etched, and the reduced part of the second insulating layer 2317 is suspended above the first insulating layer. The opportunity above the layer 2315 ensures that the second conductive layer 2318 completely and continuously covers the first contact window 2315a and the second contact window 2317a.

In this embodiment, the material of the first insulating layer 2315 is silicon oxide (SiOx), and the material of the second insulating layer 2317 is silicon nitride (SiNx), but the present invention is not limited thereto. The nitrogen-to-silicon ratio of the portion of the second insulating layer 2317 close to the first insulating layer 2315 is greater than that of the portion of the second insulating layer 2317 away from the first insulating layer 2315 . Therefore, when the first insulating layer 2315 and the second insulating layer 2317 are etched with the same etchant, although the etching rate of the first insulating layer 2315 is greater than that of the second insulating layer 2317, the part far away from the first insulating layer 2315 The etched rate is greater than the etched rate of the portion near the first insulating layer 2315 , so the etched rate of the portion near the first insulating layer 2315 is similar to the etched rate of the first insulating layer 2315 . In this way, the cross-sectional profiles of the first contact window 2315 a and the second contact window 2317 a with relatively continuous slope changes can be obtained after etching. The etchant used in this embodiment is, for example, hydrofluoric acid (HF acid).

In this embodiment, for the same etchant, the etching rate of the second insulating layer 2317 changes in two stages from a portion close to the first insulating layer 2315 to a portion far away from the first insulating layer 2315 . In another embodiment, for the same etchant, the etching rate of the second insulating layer 2317 changes gradually from a portion close to the first insulating layer 2315 to a portion far away from the first insulating layer 2315 . Certainly, the etching rate of the second insulating layer 2317 may also be changed in more than three stages.

The contact window structure 231 of this embodiment further includes a first transparent conductive layer 231 a , a second transparent conductive layer 231 b and a third insulating layer 2319 . The first transparent conductive layer 231a covers and contacts the second conductive layer 2318, and the third insulating layer 2319 is disposed between the first transparent conductive layer 231a and the second transparent conductive layer 231b, so that the first transparent conductive layer 231a and the second transparent conductive layer A capacitor is formed between the conductive layers 231b. Since the second conductive layer 2318 in this embodiment can completely and continuously cover the first contact window 2315a and the second contact window 2317a, the subsequent first transparent conductive layer 231a and the second transparent conductive layer 231b can be properly replaced by the third The insulation layer 2319 is electrically insulated. In this way, the yield of the capacitors formed can be improved.

In this embodiment, there may be other material layers between the substrate 2311 and the first conductive layer 2316 . A first buffer layer 2312 , a second buffer layer 2313 and a fourth insulating layer 2314 are further included between the substrate 2311 and the first conductive layer 2316 in sequence. The material of the first buffer layer 2312 is, for example, silicon oxide (SiOx), and the material of the second buffer layer 2313 is, for example, silicon nitride (SiNx). The first buffer layer 2312 and the second buffer layer 2313 can prevent impurities contained in the substrate 2311 from diffusing to other upper material layers and causing damage. The fourth insulating layer 2314 disposed under the first conductive layer 2316 can provide an insulating effect, so that the first conductive layer 2316 can be insulated from other conductive materials below.

5A to 5F are schematic cross-sectional flow charts of the manufacturing method of the contact window structure of FIG. 4 . Referring to FIG. 5A first, a first buffer layer 2312 , a second buffer layer 2313 and a fourth insulating layer 2314 are sequentially formed on the substrate 2311 . The material of the substrate 2311 can be glass, quartz or other similar materials. The method for forming the three-layer structure may be chemical vapor deposition (Chemical Vapor Deposition, CVD), but is not limited thereto, and other suitable process methods may also be used, and the present invention is not limited thereto.

Next, referring to FIG. 5B , a first conductive layer 2316 is formed, and the first conductive layer 2316 is a patterned structure on the fourth insulating layer 2314 . Next, as shown in FIG. 5C , a first insulating layer 2315 is formed to cover the first conductive layer 2316 and the substrate 2311 . Referring again to FIG. 5D , a second insulating layer 2317 is formed to cover the first insulating layer 2315 . Wherein, the first insulating layer 2315 and the second insulating layer 2317 can electrically insulate the first conductor layer 2316 from other conductor layers formed subsequently. In addition, the material of the first insulating layer 2315 is different from that of the second insulating layer 2317 . For the same etchant, the etching rate of the first insulating layer 2315 is greater than that of the second insulating layer 2317 . The etching rate of the portion of the second insulating layer 2317 close to the first insulating layer 2315 is greater than the etching rate of the portion of the second insulating layer 2317 away from the first insulating layer 2315 .

Please refer to FIG. 5E . In the step of FIG. 5E , the first insulating layer 2315 and the second insulating layer 2317 are etched. In this step, a first contact window 2315 a is etched in the first insulating layer 2315 , and a second contact window 2317 a is etched in the second insulating layer 2317 . The first contact window 2315a is exposed to the second contact window 2317a. The etched first insulating layer 2315 and the second insulating layer 2317 will expose a part of the first conductive layer 2316 to the first contact window 2315a.

Next, please refer to FIG. 5F, after the etching step, a second conductive layer 2318 is formed to cover the first contact window 2315a and the second contact window 2317a. The second conductive layer 2318 contacts the portion of the first conductive layer 2316 exposed on the first contact window 2315a. Therefore, the contact portion of the second conductor layer 2318 and the first conductor layer 2316 can be electrically connected.

In this embodiment, the material of the first insulating layer 2315 is silicon oxide, which can be prepared by chemical vapor deposition process. The material of the second insulating layer 2317 is silicon nitride, so silicon nitride can be formed by chemical vapor deposition process of silane (SiH ₄ ) and ammonia gas (NH ₃ ). Silane provides the source of silicon in silicon nitride, and ammonia provides the source of nitrogen in silicon nitride. In order to make the etching rate of the second insulating layer 2317 near the first insulating layer 2315 greater than the etching rate of the second insulating layer 2317 away from the first insulating layer 2315, during the chemical vapor deposition process, Gradually reduce the ratio of ammonia to silane, so that the nitrogen-to-silicon ratio (N/Si) of the silicon nitride layer formed in the chemical vapor deposition process gradually decreases. In this embodiment, the ratio of ammonia gas to silane in the early stage of deposition is adjusted to 7:1, and the ratio of ammonia gas to silane in the later stage is adjusted to 3:1.

Since the second insulating layer 2317 covers the first insulating layer 2315 during the deposition process, the silicon nitride formed by the ratio of ammonia gas to silane in the previous stage is seven to one (larger ratio of silicon nitride) will be deposited more easily. close to the first insulating layer 2315 . The ratio of ammonia gas to silane in the latter stage is three to one to form silicon nitride (the ratio of nitrogen to silicon is small), which will then be deposited on the silicon nitride deposited in the previous stage. Therefore, in the second insulating layer 2317, the nitrogen-to-silicon ratio of the portion close to the first insulating layer 2315 will be greater than that of the portion of the second insulating layer 2317 far away from the first insulating layer 2315, thereby adjusting the etching rate of the second insulating layer 2317. rate.

Adjusting the ratio of ammonia gas to silane in the process makes the deposited silicon nitride have different ratios of nitrogen to silicon, so that in the subsequent etching step, the part of the second insulating layer 2317 close to the first insulating layer 2315 can be compared with the first insulating layer 2315 The etched rate is relatively similar. In addition, in the etching step, the method of forming the first contact window 2315a of the first insulating layer 2315 and the second contact window 2317a of the second insulating layer 2317 may be to perform dry etching first, and then perform wet etching.

However, the manner of adjusting the ratio of ammonia to silane during the chemical vapor deposition process is not limited to the above methods. In another embodiment, during the chemical vapor deposition process, the ratio of ammonia gas to silane is lowered gradually, which can also make the second insulating layer 2317 close to the first insulating layer 2315. The nitrogen-to-silicon ratio of the part will be greater than the nitrogen-to-silicon ratio of the part of the second insulating layer 2317 far away from the first insulating layer 2315, so that the etching rate of the part of the second insulating layer 2317 close to the first insulating layer 2315 in the subsequent etching step is relatively far away from it. The portions are large.

Please refer to FIG. 4 again. In this embodiment, after the second conductive layer 2318 is formed through the steps in FIG. 5F , a first transparent conductive layer 231 a may be formed to cover and contact the second conductive layer 2318 . Next, a third insulating layer 2319 is formed to cover the first transparent conductive layer 231a, and then a second transparent conductive layer 231b is formed on the third insulating layer 2319. The first transparent conductive layer 231a and the second transparent conductive layer 231b form a capacitor. The structure of the contact window structure 231 formed by the preparation process of FIG. 5A to FIG. 5F and the steps of forming the first transparent conductive layer 231 a , the third insulating layer 2319 and the second transparent conductive layer 231 b will be shown in FIG. 4 .

Please refer to FIG. 2 and FIG. 3 next. The pixel array substrate 230 of the display panel 200 in this embodiment further includes a plurality of pixel driving units 232 , only one of which is schematically shown in FIG. 3 . Each pixel driving unit 232 includes a pixel electrode 2321 and a pair of counter electrodes 2322 . The pixel electrode 2321 has a plurality of first strip patterns 2321a. The opposite electrode 2322 has a plurality of second strip patterns 2322a. The first strip pattern 2321a and the second strip pattern 2322a are arranged alternately, and the opposite electrode 2322 and the pixel electrode 2321 are electrically insulated from each other. In other words, the display panel 200 of this embodiment is a so-called in-plane switching (In-Plane Switching, IPS) type display panel, those skilled in the art can also make equivalent design changes as shown in Figure 2, the pixel electrode 2321 and the opposite electrode 2322 are located on different planes.

Please refer to Figure 6 next. 6 is a schematic cross-sectional view of a display panel according to a second embodiment of the present invention. The display panel 300 includes a pair of facing substrates 210 , a display medium 220 , and a pixel array substrate 330 . Since the present embodiment is substantially similar to the first embodiment, the same reference numerals are used to designate the same or similar elements. In the pixel array substrate 330, the contact window structure 231 shown in FIG. 4 is also used. The main difference between this embodiment and the foregoing first embodiment is that in the display panel 300 of this embodiment, the pixel electrodes 3321 and the opposite electrodes 3322 are located on the same plane, wherein the plurality of opposite electrodes 3322 and the first The conductive layer 2316, the second conductive layer 2318 and the first transparent conductive layer 231a are electrically connected, and the pixel electrode 3321 is electrically connected to the second transparent conductive layer 231b. The display panel 300 of this embodiment is also a coplanar switching display panel.

Please refer to Figure 7 again. FIG. 7 is a schematic cross-sectional view of a display panel according to a third embodiment of the present invention. FIG. 8 is a partial top view of the pixel array substrate of FIG. 7 . The display panel 400 includes a pair of facing substrates 210 , a display medium 220 , and a pixel array substrate 430 . This embodiment is substantially similar to the first embodiment, so the same reference numerals are used to denote the same or similar elements, and the contact window structure 231 shown in FIG. 4 is also used in the pixel array substrate 430 . Please refer to FIG. 7 and FIG. 8 at the same time. Specifically, the main difference between this embodiment and the aforementioned first embodiment is that in this embodiment, in the pixel driving unit 432 of the pixel array substrate 430 of the display panel 400, each The pixel driving unit 432 includes a pixel electrode 4321 and a pair of counter electrodes 4322 . The pixel electrode 4321 has a plurality of first strip patterns 4321a and the aforementioned first strip patterns 4321a are located on the same plane. The opposite electrode 4322 is located below the pixel electrode 4321 , and the pixel electrode 4321 and the opposite electrode 4322 are electrically insulated from each other. In other words, the display panel 400 of this embodiment is described by taking a Fringe Field Switching (FFS) type display panel as an example, and those skilled in the art can also make equivalent design changes. In addition, in the third embodiment, the configurations, manufacturing methods and materials of other components are similar to those in the first embodiment, so no more details are given here.

To sum up, in the contact window structure and its manufacturing method of the present invention, the etching rate of the second insulating layer near the first insulating layer is similar to that of the first insulating layer. This can prevent the second insulating layer from being suspended above the etched first insulating layer below due to the slow etching rate, thereby ensuring the integrity of the subsequently formed material layer and improving the reliability of the product. The contact window structure can be applied on the pixel array substrate, and the aforementioned pixel array substrate can be used in the display panel.

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications to the structure of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined by the appended claims.

Claims (32)

1. a contact structure, comprising:

One first conductor layer, is configured on a substrate;

One first insulation course, covers this first conductor layer and this substrate, and has one first contact hole, and wherein a part for this first conductor layer is exposed to this first contact hole, and this first insulation course is contacted with this first conductor layer;

One second insulation course, cover this first insulation course, and there is one second contact hole, this second insulation course is contacted with this first insulation course, wherein this first contact hole is exposed to this second contact hole, the material of this first insulation course is different from the material of this second insulation course, for same etch liquid, this the first insulation course be greater than by etch-rate this second insulation course by etch-rate, this second insulation course near this first insulation course part be greater than by etch-rate this second insulation course away from this first insulation course part by etch-rate; And

One second conductor layer, covers this first contact hole with this second contact hole and contacts the part that this first conductor layer is exposed to this first contact hole.

2. contact structure as claimed in claim 1, wherein the material of this first insulation course is monox.

3. contact structure as claimed in claim 2, wherein the material of this second insulation course is silicon nitride, and this second insulation course near the nitrogen silicon of the part of this first insulation course than being greater than the nitrogen silicon ratio of this second insulation course away from the part of this first insulation course.

4. contact structure as claimed in claim 1, wherein for same etch liquid, this etching solution is hydrofluorite, and this second insulation course is gradual change from the part near this first insulation course to the part away from this first insulation course by etch-rate.

5. contact structure as claimed in claim 1, wherein for same etch liquid, this etching solution is hydrofluorite, and this second insulation course is two benches change by etch-rate from the part near this first insulation course to the part away from this first insulation course.

6. contact structure as claimed in claim 1, also comprises:

One first transparency conducting layer, covers and contacts this second conductor layer;

One second transparency conducting layer; And

One the 3rd insulation course, is configured between this first transparency conducting layer and this second transparency conducting layer, to form an electric capacity.

7. an image element array substrates, comprises a contact structure, and wherein this contact structure comprises:

One first conductor layer, is configured on a substrate;

One first insulation course, covers this first conductor layer and this substrate, and has one first contact hole, and wherein a part for this first conductor layer is exposed to this first contact hole, and this first insulation course is contacted with this first conductor layer;

One second insulation course, cover this first insulation course, and there is one second contact hole, this second insulation course is contacted with this first insulation course, wherein this first contact hole is exposed to this second contact hole, the material of this first insulation course is different from the material of this second insulation course, for same etch liquid, this the first insulation course be greater than by etch-rate this second insulation course by etch-rate, this second insulation course near this first insulation course part be greater than by etch-rate this second insulation course away from this first insulation course part by etch-rate; And

One second conductor layer, covers this first contact hole with this second contact hole and contacts the part that this first conductor layer is exposed to this first contact hole.

8. image element array substrates as claimed in claim 7, wherein the material of this first insulation course is monox.

9. image element array substrates as claimed in claim 8, wherein the material of this second insulation course is silicon nitride, and this second insulation course near the nitrogen silicon of the part of this first insulation course than being greater than the nitrogen silicon ratio of this second insulation course away from the part of this first insulation course.

10. image element array substrates as claimed in claim 7, wherein for same etch liquid, this etching solution is hydrofluorite, and this second insulation course is gradual change from the part near this first insulation course to the part away from this first insulation course by etch-rate.

11. image element array substrates as claimed in claim 7, wherein for same etch liquid, this etching solution is hydrofluorite, this second insulation course near this first insulation course part to the part away from this first insulation course by etch-rate be two benches change.

12. image element array substrates as claimed in claim 7, wherein this contact structure also comprises:

One first transparency conducting layer, covers and contacts this second conductor layer;

One second transparency conducting layer; And

One the 3rd insulation course, is configured between this first transparency conducting layer and this second transparency conducting layer, to form an electric capacity.

13. image element array substrates as claimed in claim 7, also comprise multiple pixel drive unit, each pixel drive unit comprises a pixel electrode and a counter electrode, described multiple pixel electrode has multiple first strip pattern, described multiple counter electrode and described multiple pixel electrode are electrically insulated mutually, described multiple counter electrode has multiple second strip pattern, and described multiple first strip pattern and described multiple second strip pattern are alternately arranged.

14. image element array substrates as claimed in claim 13, wherein said multiple pixel electrode and described multiple counter electrode in the same plane.

15. image element array substrates as claimed in claim 13, wherein said multiple pixel electrode and described multiple counter electrode are positioned in Different Plane.

16. image element array substrates as claimed in claim 7, also comprise multiple pixel drive unit, each pixel drive unit comprises a pixel electrode and a counter electrode, described multiple pixel electrode has multiple first strip pattern and in the same plane, described multiple counter electrode is positioned at below described multiple pixel electrode, and described multiple pixel electrode and described multiple counter electrode are electrically insulated mutually.

17. 1 kinds of display panels, comprising:

One subtend substrate;

One display medium;

One image element array substrates, comprises a contact structure, and wherein this display medium is configured between this subtend substrate and this image element array substrates, and this contact structure comprises:

One first conductor layer, is configured on a substrate;

One first insulation course, covers this first conductor layer and this substrate, and has one first contact hole, and wherein a part for this first conductor layer is exposed to this first contact hole, and this first insulation course is contacted with this first conductor layer;

One second insulation course, cover this first insulation course, and there is one second contact hole, this second insulation course is contacted with this first insulation course, wherein this first contact hole is exposed to this second contact hole, the material of this first insulation course is different from the material of this second insulation course, for same etch liquid, this the first insulation course be greater than by etch-rate this second insulation course by etch-rate, this second insulation course near this first insulation course part be greater than by etch-rate this second insulation course away from this first insulation course part by etch-rate; And

One second conductor layer, covers this first contact hole with this second contact hole and contacts the part that this first conductor layer is exposed to this first contact hole.

18. display panels as claimed in claim 17, wherein the material of this first insulation course is monox.

19. display panels as claimed in claim 18, wherein the material of this second insulation course is silicon nitride, and this second insulation course near the nitrogen silicon of the part of this first insulation course than being greater than the nitrogen silicon ratio of this second insulation course away from the part of this first insulation course.

20. display panels as claimed in claim 17, wherein for same etch liquid, this etching solution is hydrofluorite, and this second insulation course is from being gradual change to the part away from this first insulation course by etch-rate near the part of this first insulation course.

21. display panels as claimed in claim 17, wherein for same etch liquid, this etching solution is hydrofluorite, this second insulation course near this first insulation course part to the part away from this first insulation course by etch-rate be two benches change.

22. display panels as claimed in claim 17, wherein this contact structure also comprises:

One first transparency conducting layer, covers and contacts this second conductor layer;

One second transparency conducting layer; And

One the 3rd insulation course, is configured between this first transparency conducting layer and this second transparency conducting layer, to form an electric capacity.

23. display panels as claimed in claim 17, wherein this image element array substrates also comprises multiple pixel drive unit, each pixel drive unit comprises a pixel electrode and a counter electrode, described multiple pixel electrode has multiple first strip pattern, described multiple counter electrode and described multiple pixel electrode are electrically insulated mutually, described multiple counter electrode has multiple second strip pattern, and described multiple first strip pattern and described multiple second strip pattern are alternately arranged.

24. display panels as claimed in claim 23, wherein said multiple pixel electrode and described multiple counter electrode in the same plane.

25. display panels as claimed in claim 23, wherein said multiple pixel electrode and described multiple counter electrode are positioned in Different Plane.

26. display panels as claimed in claim 17, wherein this image element array substrates also comprises multiple pixel drive unit, each pixel drive unit comprises a pixel electrode and a counter electrode, described multiple pixel electrode has multiple first strip pattern and in the same plane, described multiple counter electrode is positioned at below described multiple pixel electrode, and described multiple pixel electrode and described multiple counter electrode are electrically insulated mutually, wherein said multiple counter electrode and this first conductor layer are electrically connected.

The manufacture method of 27. 1 kinds of contact structures, comprising:

Form one first conductor layer on a substrate;

Form one first insulation course to cover this first conductor layer and this substrate, this first insulation course is contacted with this first conductor layer;

Form one second insulation course to cover this first insulation course, wherein this second insulation course is contacted with this first insulation course, the material of this first insulation course is different from the material of this second insulation course, for same etch liquid, this the first insulation course be greater than by etch-rate this second insulation course by etch-rate, this second insulation course near this first insulation course part be greater than by etch-rate this second insulation course away from this first insulation course part by etch-rate;

Etch this first insulation course and this second insulation course, to form one first contact hole in this first insulation course, and form one second contact hole in this second insulation course, wherein a part for this first conductor layer is exposed to this first contact hole, and this first contact hole is exposed to this second contact hole; And

Form one second conductor layer to cover this first contact hole and this second contact hole, and contact the part that this first conductor layer is exposed to this first contact hole.

The manufacture method of 28. contact structures as claimed in claim 27, the method wherein forming this second insulation course comprises and uses silane and ammonia to carry out chemical vapor deposition method, and in the process of carrying out chemical vapor deposition method, turn down the ratio of ammonia to silane.

The manufacture method of 29. contact structures as claimed in claim 28, wherein carry out in the process of chemical vapor deposition method, ammonia during leading portion is seven to one to the ratio of silane, and ammonia during back segment is three to one to the ratio of silane.

The manufacture method of 30. contact structures as claimed in claim 28, wherein carries out in the process of chemical vapor deposition method, and turning down the mode of ammonia to the ratio of silane is progressive turning down.

The manufacture method of 31. contact structures as claimed in claim 27, the method wherein etching this first insulation course and this second insulation course comprises first carries out dry-etching and carries out Wet-type etching again.

The manufacture method of 32. contact structures as claimed in claim 27, wherein also comprises after this second conductor layer of formation:

Form one first transparency conducting layer to cover and to contact this second conductor layer;

Form one the 3rd insulation course to cover this first transparency conducting layer; And

Form one second transparency conducting layer on the 3rd insulation course, to form an electric capacity.