CN111952250B - Manufacturing method of array substrate and array substrate - Google Patents

Abstract

The invention provides a manufacturing method of an array substrate and the array substrate, wherein a first insulating layer and an active layer film which cover a first metal layer are sequentially formed on a substrate, the etching rate of the active layer film is larger than that of the first insulating layer, the active layer film and the first insulating layer are overlapped up and down, the active layer film is used as a guide layer of the first insulating layer when the active layer film is opened, the active layer film and the first insulating layer are opened at positions corresponding to the first contact holes, the first contact holes penetrating through the active layer film and the first insulating layer from top to bottom can be formed, and due to the fact that the etching rates of the active layer film and the first insulating layer are different, the active layer film is guided when the active layer film is opened, good taper angles can be obtained at the positions of the first contact holes while the undercut problem of the first insulating layer below is avoided, the second metal layer which is subsequently filled into the first contact holes avoids the risk of broken lines, the yield of products is effectively improved, and new photomask is not needed, and the cost is saved.

Description

Manufacturing method of array substrate and array substrate

technical field

The present invention relates to the field of display technology, in particular to a method for manufacturing an array substrate and the array substrate.

Background technique

Liquid crystal display devices have the advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing costs. They dominate the field of flat panel displays and are widely used in LCD TVs, mobile phones, In electronic devices such as personal digital assistants (PDAs), digital cameras, computer screens, or laptop screens. The liquid crystal display device includes an opposite color filter substrate (Color Filter, CF) and a thin film transistor array substrate (TFT array) and a liquid crystal layer (LC layer) sandwiched between them.

In the traditional manufacturing process of thin film transistor array substrates, it is sometimes necessary to open a through hole on the insulating layer, which includes a composite single layer or a multi-layer structure independently stacked, because the insulating layer cannot be added Taper film and the density of the upper part and the lower part are inconsistent, so the undercut phenomenon will occur at the opening of the insulating layer during etching, and the taper on the side wall of the insulating layer is arc-shaped (that is, curved. ) or in a right-angle state, the side wall of the insulating layer tends to present a sharp angle, and the thickness of the insulating layer is relatively thick, such as reaching As mentioned above, due to the limitation of production capacity, it is easy to have abnormal hole opening at this time, resulting in poor contact. Undercutting may lead to disconnection when subsequent layers of other film layers are filled in the hole, which in turn affects the display panel. display function.

Contents of the invention

The object of the present invention is to provide a method for manufacturing an array substrate and the array substrate, which can improve the undercut of the insulating layer and prevent the film layers of subsequent layers from being disconnected.

The present invention provides a method for manufacturing an array substrate, the method comprising:

providing a substrate, the substrate including a display area and a non-display area located at the periphery of the display area;

forming a first metal layer on the substrate, and patterning the first metal layer in the non-display area to form a first lead;

forming a first insulating layer covering the first metal layer on the substrate;

An active layer thin film covering the first insulating layer is formed on the first insulating layer, and a first contact hole is formed through the active layer thin film and the first insulating layer, and the first contact hole is located at Above the first lead, the etching rate of the active layer film is greater than the etching rate of the first insulating layer;

forming a second metal layer on the first insulating layer, and patterning the second metal layer in the non-display area to form a second lead, the second lead filling the first contact The hole is electrically connected to the first lead.

Further, after the step of forming the first contact hole penetrating through the active layer film and the first insulating layer, the active layer film is patterned to form a For silicon islands, the thin film of the active layer is removed corresponding to the regions other than the silicon islands.

Further, before the step of forming the first contact hole penetrating through the active layer film and the first insulating layer, the active layer film is patterned to form a silicon an island, forming an etching guide in the non-display area, the etching guide corresponding to the position of the first contact hole.

Further, patterning is performed on the etching guide and the first insulating layer below the etching guide to form the first contact hole penetrating through the etching guide and the first insulating layer.

Further, the second lead covers the etching guide, and the facing area of the second lead on the substrate is larger than the facing area of the etching guiding part on the substrate.

Further, the first insulating layer is formed by chemical vapor deposition, and the reaction gases used in the chemical vapor deposition include silane, ammonia and nitrogen.

Further, the first insulating layer controls the flow rate range of the silane to 1860-2100 sccm in the high-speed film-forming state, and the flow rate range of the ammonia gas to 15400-17300 sccm; The flow rate range of the silane is 600-700 sccm, and the flow rate range of the ammonia gas is 7600-9000 sccm.

Further, the first contact hole is formed by an etching process, and when the active layer film is etched at the position corresponding to the first contact hole, the gas introduced into the etching process includes sulfur hexafluoride gas, helium gas and chlorine, the flow range of the sulfur hexafluoride is 310sccm-500sccm, the flow range of the helium is 100sccm-300sccm, the flow range of the chlorine gas is 2100sccm-2200sccm, the etching process The range of pressure used is 40-50mTorr, and the range of power used by the etching process is 5000-6000W; when etching the first insulating layer at the position corresponding to the first contact hole, the etching process The feeding gas includes sulfur hexafluoride gas, oxygen and helium, the flow rate range of the sulfur hexafluoride is 510sccm-600sccm, the flow rate range of the helium is 600sccm to 1000sccm, the etching process adopts The range of pressure is 160-170mTorr.

Further, the method further includes: before the step of forming the first metal layer on the substrate, forming a third metal layer on the substrate, for the third metal layer in the non-display area. patterning the metal layer to form a third lead;

forming a second insulating layer covering the third lead on the substrate, the third lead and the second insulating layer being formed between the first metal layer and the substrate;

The first insulating layer and the active layer thin film are formed on the second insulating layer, and the active layer thin film, the first insulating layer and the second insulating layer in the non-display area The insulating layer is patterned to form a second contact hole penetrating through the active layer film, the first insulating layer and the second insulating layer, and the etching rate of the second insulating layer is less than or equal to that of the first insulating layer. Etching rate of an insulating layer;

The second lead is filled into the second contact hole and electrically connected with the third lead.

The present invention also provides an array substrate, which is manufactured by the above method for manufacturing an array substrate.

In the manufacturing method of the array substrate and the array substrate provided by the present invention, the first insulating layer covering the first metal layer and the thin film of the active layer are sequentially formed on the substrate, wherein the etching rate of the thin film of the active layer is higher than that of the first insulating layer, and The active layer thin film and the first insulating layer are stacked up and down, and the active layer thin film is used as the guide layer of the first insulating layer when the hole is opened, and the active layer thin film and the first insulating layer are opened at the position corresponding to the first contact hole. The hole can form a first contact hole penetrating through the active layer film and the first insulating layer from top to bottom. Due to the different etching rates of the active layer film and the first insulating layer, the active layer film is guided through the active layer film when the hole is opened. , while avoiding the undercut problem of the first insulating layer below, a good taper angle can be obtained at the position of the first contact hole, so that the second metal layer subsequently filled into the first contact hole avoids the risk of disconnection, The yield rate of the product is effectively improved, and there is no need to use a new photomask, which saves the cost.

Description of drawings

FIG. 1 is a schematic plan view of an array substrate in Embodiment 1 of the present invention;

2 is a schematic structural diagram of a first contact hole of an array substrate in Embodiment 1 of the present invention;

3a to 3l are schematic diagrams of the manufacturing process of the array substrate in Embodiment 1 of the present invention;

4 is a schematic structural diagram of a second contact hole of the array substrate in Embodiment 1 of the present invention;

5a to 5l are schematic diagrams of the manufacturing process of the array substrate in Embodiment 2 of the present invention.

Detailed ways

The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

Embodiment one

The manufacturing method of the array substrate according to Embodiment 1 of the present invention includes: as shown in FIG. 1 to FIG. 31 ,

A substrate 10 is provided. The substrate 10 includes a display area 101 and a non-display area 102 located on the periphery of the display area 101 . The array substrate is fabricated on the substrate 10 at the same time. Specifically, the substrate 10 is a transparent substrate 10, for example made of glass.

A first metal layer (not shown) is formed on the substrate 10, and the first metal layer is patterned to form gates 111 and scan lines (not shown) in the display area 101, and form The first lead 113 of the area 102 is electrically connected to the scan line. Specifically, the material of the first metal layer is made of stacked Mo (molybdenum), Al (aluminum), and Mo (molybdenum), and the first metal layer is exposed, developed and etched, thereby forming the gate 111, scanning wire and the first lead 113.

A first insulating layer 12 covering the first metal layer is formed on the substrate 10 , that is, the first insulating layer 12 covers the gate 111 , the scan line and the first lead 113 .

An active layer thin film 13 covering the first insulating layer 12 is formed on the first insulating layer 12, and the active layer thin film 13 and the first insulating layer 12 are stacked up and down to form a composite structure layer. The active layer film 13 is, for example, an amorphous silicon (a-Si) layer, but not limited thereto.

The active layer film 13 and the first insulating layer 12 in the non-display area 102 are patterned to form a first contact hole 120 penetrating through the active layer film 13 and the first insulating layer 12, and the first contact hole 120 is located at the Above the first lead 113 , the first lead 113 is exposed by the first contact hole 120 , and the etching rate (ER, Etch Rate) of the active layer thin film 13 is greater than the etching rate of the first insulating layer 12 . The active layer film 13 is the upper film layer of the first insulating layer 12, and the active layer film 13 is used as the guide layer of the first insulating layer 12 when the hole is opened, and the active layer film 13 is aligned at the position corresponding to the first contact hole 120. Opening holes with the first insulating layer 12 can form a first contact hole 120 penetrating through the active layer thin film 13 and the first insulating layer 12 from top to bottom.

Specifically, the step of forming the first contact hole 120 penetrating through the active layer film 13 and the first insulating layer 12 includes:

As shown in FIG. 3 a , a first photoresist layer 21 is formed on the active layer film 13 .

As shown in FIG. 3b, the first photoresist layer 21 is exposed and developed through a photomask to form a patterned photoresist layer. The first photoresist layer 21 includes an opaque region and a light-transmitting region other than the opaque region. The opaque area is the remaining photoresist material, the light-transmitting area is the area where the photoresist material is removed after development, the light-transmitting area corresponds to the position where the active layer film 13 and the first insulating layer 12 need to be removed, and the active layer film 13 emerges from the light-transmitting area.

As shown in FIG. 3 c , the active layer film 13 and the first insulating layer 12 under the light-transmitting region are removed by etching. Specifically, dry etching is used for this etching, and the thickness of the active layer film 13 is smaller than that of the first insulating layer 12. When the active layer film 13 is etched through, the first insulating layer 12 is exposed from the active layer film 13, Immediately, the etching of the first insulating layer 12 starts.

It should be noted that etching is anisotropic, and the vertical etching force on the substrate 10 is greater than the horizontal etching force. Since the etching rate of the active layer film 13 and the first insulating layer 12 are different, the etching rate of the active layer film 13 is relatively fast. When the active layer film 13 is etched through, the first contact hole 120 is initially reserved At the etching position, the sidewall of the corresponding hole of the active layer film 13 acts as a guide or transition for etching the first insulating layer 12, and then when the first insulating layer 12 is etched, the active layer film 13 above is also gradually retreating, using The film layer with a smaller etching rate acts as a guide layer to make up for the lateral etching force.

And the density of the first insulating layer 12 is relatively large, so the etching time of the first exposed part is relatively long, and the upper surface of the first insulating layer 12 is in contact with the active layer film 13, making it difficult for the etching gas to contact with the first insulating layer 12. The upper surface of the insulating layer 12 reacts. With the gradual retreat of the active layer film 13 and the further etching of the first insulating layer 12, the etching gas has to be etched obliquely downward under the guidance of the sidewall of the active layer film 13. Therefore, the first contact hole 120 penetrating through the active layer film 13 and the first insulating layer 12 is formed, and the sidewall of the first insulating layer 12 corresponding to the first contact hole 120 has a gentle slope, presenting a good taper angle (the inclination of the section after etching), and there is no undercut phenomenon.

As shown in FIG. 3 d , the opaque region of the first photoresist layer 21 is removed by an ashing process.

Further, the purpose of increasing the etching rate of the active layer thin film 13 or reducing the etching rate of the first insulating layer 12 can be achieved by changing the film forming and etching parameters. Specifically, the first insulating layer 12 is made of silicon nitride (SiNx) material and formed by chemical vapor deposition (CVD). The reaction gases used in chemical vapor deposition include silane (SH4), ammonia (NH3) and nitrogen (N2 ), the reactive gases used in the active layer film 13 include silane, hydrogen and phosphine (PH3).

Wherein, the first insulating layer 12 controls the flow rate range of silane to be 1860-2100 sccm (under standard conditions) in the high-speed film-forming state, and the flow rate range of ammonia gas is 15400-17300 sccm; in the low-speed film-forming state The lower control silane flow rate ranges from 600-700 sccm, and the ammonia gas flow rate ranges from 7600-9000 sccm, which effectively reduces the etching rate of the first insulating layer 12 and does not cause electrical changes. For the flow rates of other related gases, reference may be made to the prior art, which will not be repeated here. Specifically, in this embodiment, the flow rate of silane is 1860 sccm and the flow rate of ammonia gas is 17300 sccm in the high-speed film-forming state; the flow rate of silane gas is 600 sccm and the flow rate of ammonia gas is 9000 sccm in the low-speed film-forming state.

In order to have a good etching effect, the ECCP mode is used to etch the active layer film 13 , and when the active layer film 13 is etched through, the first insulating layer 12 is etched using the RIE mode immediately.

When etching the active layer thin film 13 at the position corresponding to the first contact hole 120, the feeding gas of the etching process includes sulfur hexafluoride (SF6) gas, helium (He) and chlorine gas (Cl2), the flow rate of sulfur hexafluoride The value range is 310sccm-500sccm, the flow rate range of helium is 100sccm-300sccm, which effectively increases the uniformity of plasma (plasma), the flow rate range of chlorine gas is 2100sccm-2200sccm, the pressure value used in the etching process The range is 40-50mTorr (mTorr), and the range of power used in the etching process is 5000-6000W. Since ECCP uses dual power sources, the power used is also dual power, which effectively improves the etching rate of the active layer film 13 . In this embodiment, the specific parameters of the etching process are, for example, a pressure of 50 mTorr, a power of 6000 W+6000 W, a flow rate of sulfur hexafluoride of 500 sccm, a flow rate of helium gas of 300 sccm, and a flow rate of chlorine gas of 2200 sccm.

When etching the first insulating layer 12 at the position corresponding to the first contact hole 120, the gas introduced into the etching process includes sulfur hexafluoride gas, oxygen and helium, the flow rate of sulfur hexafluoride is in the range of 510sccm-600sccm, helium The gas flow ranges from 600sccm to 1000sccm, which effectively increases the uniformity of the plasma, and the pressure used in the etching process ranges from 160-170mTorr. In this embodiment, the specific parameters of the etching process are, for example, a pressure of 170 mTorr, a flow rate of sulfur hexafluoride of 600 sccm, and a flow rate of helium gas of 1000 sccm.

Preferably, after etching the first contact hole 120 through the active layer film 13 and the first insulating layer 12, the taper angle on both sides of the first insulating layer 12 can be controlled at about 30°, or even lower than 30°, and The average critical dimension deviation (CD bias) after the active layer thin film 13 and the first insulating layer 12 are etched together is about 0.37um, which proves that the second etching of the first insulating layer 12 has a relatively small influence on the line width.

In this embodiment, as shown in FIG. 3e to FIG. 3g, after the step of forming the first contact hole 120 penetrating through the active layer film 13 and the first insulating layer 12, the second optical layer is coated on the active layer film. The resist layer 22 is used to expose, develop and etch the active layer film 13 to form a silicon island 131 located in the display area 101 , and the area of the active layer film 13 corresponding to the silicon island 131 is removed. As shown in FIG. 3h, the second photoresist layer 22 is removed.

Further, as shown in FIGS. 3i to 3l, a second metal layer 14 is formed on the first insulating layer 12 and the silicon island 131, a third photoresist layer 23 is coated on the second metal layer 14, and the second The metal layer 14 is exposed, developed and etched to form the source electrode 141, the drain electrode 142 and the data line (not shown) in the display area 101, and form the second lead 143 located in the non-display area 102, the second lead 143 fills in the first contact hole 120 and is electrically connected with the first lead 113 to realize conduction. Since the side wall of the first insulating layer 12 in contact with the second lead 143 is a smooth slope, the second lead 143 will not be broken. line risk. The third photoresist layer 23 is removed.

It is worth mentioning that, as shown in FIG. 4 , in order to obtain a narrower limit frame, the method further includes forming a third metal layer on the substrate 10 before the step of forming the first metal layer on the substrate 10, that is, A third metal layer is disposed under the first metal layer, and the third metal layer in the non-display area 102 is patterned to form a third lead 151 . The third lead 151 is connected to an external circuit to realize signal transmission.

The second insulating layer 16 covering the third lead 151 is formed on the substrate 10, the third lead 151 and the second insulating layer 16 are formed between the first metal layer and the substrate 10, the first metal layer and the third metal layer separated by the second insulating layer 16.

The first insulating layer 12 and the active layer film 13 are formed on the second insulating layer 16, and the active layer film 13, the first insulating layer 12 and the second insulating layer 16 in the non-display area 102 are patterned, Form the second contact hole 160 through the active layer film 13, the first insulating layer 12 and the second insulating layer 16, the etching rate of the second insulating layer 16 is less than or equal to the etching rate of the first insulating layer 12, to form a smooth The formation principle of the first contact hole 120 and the second contact hole 160 on the sidewall can refer to the aforementioned first contact hole 120 . It can be understood that after the first contact hole 120 and the second contact hole 160 are formed, the active layer film 13 above the contact hole needs to be removed, and only the silicon island 131 area in the display area 101 remains, but not limited thereto.

The second lead 143 is filled into the second contact hole 160 and electrically connected to the third lead 151 .

After the pattern of the second metal layer 14 is completed, follow-up processes, such as the formation of the common electrode (not shown in the figure) and the pixel electrode (not shown in the figure), can be referred to the prior art, and will not be repeated here.

Embodiment two

This embodiment is partly the same as Embodiment 1, and the same parts will not be repeated here. The difference is that, as shown in FIG. 5a to FIG. Before step 120, the active layer thin film 13 is patterned, silicon islands 131 are formed in the display area 101, and etching guides 132 are formed in the non-display area 102. The etching guides 132 correspond to the positions of the first contact holes 120 .

Specifically, as shown in FIGS. 5a to 5c, the fourth photoresist layer 24 is coated on the active layer film 13, and after exposure, development and etching, a part of the active layer remains at the position where the first contact hole 120 is formed. The thin film 13 serves as a guide or transition for subsequent etching, that is, the etching guide 132 . As shown in FIG. 5d, the fourth photoresist layer 24 is removed.

As shown in FIG. 5e, the fifth photoresist layer 25 is then coated on the etching guide part 132, and after exposure and development, the photoresist layer is removed at the place corresponding to the first contact hole 120, exposing the etching guide part 132; As shown in 5f, the etching guide 132 and the first insulating layer 12 below the etching guide 132 are etched to form a first contact hole 120 penetrating through the etching guide 132 and the first insulating layer 12, and the first contact hole 120 has The smooth side wall, that is, the taper angle is good, and the specific implementation method can refer to the description of the first embodiment. As shown in FIG. 5g, the fifth photoresist layer 25 is removed.

Further, as shown in FIG. 5 h , a second metal layer 14 covering the etching guide 132 and the silicon island 131 is formed on the substrate 10 .

As shown in FIG. 5 i , the sixth photoresist layer 26 is coated on the second metal layer 14 , and the photoresist layer is left above the corresponding first contact hole 120 and on the silicon island 131 through exposure and development.

After the wet etching process, as shown in FIG. 5j, a second lead 143 covering the etching guide 132 is formed in the non-display area 102, and the second lead 143 is filled in the first contact hole 120 to be electrically connected to the first lead 113. A source electrode 141 and a drain electrode 142 are formed in the display region 101 and are insulated and spaced apart from each other. It can be understood that, as shown in FIG. 5k , the silicon island 131 may also be etched continuously to etch away the doped amorphous silicon layer on the silicon island 131 to form a channel.

As shown in FIG. 5l, the sixth photoresist layer 26 is removed.

In this embodiment, the second lead 143 covers the etching guide 132, and the edge of the second lead 143 is much larger than the edge of the etching guide 132, that is, the facing area of the second lead 143 on the substrate 10 is larger than that of the etching guide 132. The facing area on the substrate 10 is to prevent the edge of the second lead 143 from being undercut due to trench etching, resulting in leakage during subsequent acid etching and missing the first lead 113 .

After the pattern of the second metal layer 14 is completed, the subsequent process, such as the formation of the common electrode and the pixel electrode, can be referred to the prior art, and will not be repeated here.

The present invention also provides an array substrate, which is manufactured by the above method for manufacturing an array substrate.

In the manufacturing method of the array substrate and the array substrate provided by the present invention, the first insulating layer 12 covering the first metal layer and the active layer thin film 13 are successively formed on the substrate 10, wherein the etching rate of the active layer thin film 13 is higher than that of the first The insulating layer 12, and the active layer film 13 and the first insulating layer 12 are stacked up and down, and the active layer film 13 is used as the guide layer of the first insulating layer 12 when the hole is opened, and there is a pair at the position corresponding to the first contact hole 120 The active layer film 13 and the first insulating layer 12 are opened to form a first contact hole 120 penetrating through the active layer film 13 and the first insulating layer 12 from top to bottom, because the active layer film 13 and the first insulating layer 12 have different etching rates. When the hole is opened, it is guided by the active layer thin film 13, avoiding the undercut problem of the first insulating layer 12 below, and at the same time, a good taper angle can be obtained at the position of the first contact hole 120. Even if the structure of the third metal layer and the second insulating layer 16 is added under the first metal layer, the second layer having a good taper angle and penetrating the active layer thin film 13, the first insulating layer 12 and the second insulating layer 16 can be formed. contact holes, so that the subsequent filling of the first contact hole 120 and/or the second metal layer 14 of the second contact hole avoids the risk of disconnection, effectively improves the yield of the product, and uses existing light when forming the contact hole Only a mask is needed, and there is no need to modify or produce a new mask, which saves costs.

As used herein, the terms "comprises", "comprises" or any other variation thereof are intended to cover a non-exclusive inclusion of elements other than those listed and also other elements not expressly listed.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (7)

1. A method for manufacturing an array substrate, characterized in that the method comprises: providing a substrate, the substrate including a display area and a non-display area located at the periphery of the display area; forming a first metal layer on the substrate, and patterning the first metal layer in the non-display area to form a first lead; forming a first insulating layer covering the first metal layer on the substrate; Forming an active layer film covering the first insulating layer on the first insulating layer, patterning the active layer film, forming silicon islands in the display area, and forming silicon islands in the non-display area Forming an etching guide part inside, patterning the etching guide part and the first insulating layer below the etching guide part, and forming a first contact hole penetrating through the etching guide part and the first insulating layer , the first contact hole is located above the first lead, and the etching rate of the active layer film is greater than the etching rate of the first insulating layer; forming a second metal layer on the first insulating layer, and patterning the second metal layer in the non-display area to form a second lead, the second lead filling the first contact The hole is electrically connected to the first lead; the second lead covers the etching guide, and the facing area of the second lead on the substrate is larger than that of the etching guide on the substrate of the facing area. 2. The method for manufacturing an array substrate according to claim 1, wherein after the step of forming a first contact hole penetrating through the active layer thin film and the first insulating layer, the active layer The thin film of the active layer is patterned to form silicon islands located in the display area, and the thin film of the active layer is removed corresponding to regions other than the silicon islands. 3 . The method for manufacturing the array substrate according to claim 1 , wherein the first insulating layer is formed by chemical vapor deposition, and the reaction gases used in the chemical vapor deposition include silane, ammonia and nitrogen. 4 . 4. The method for manufacturing an array substrate according to claim 3, wherein the first insulating layer controls the flow rate of the silane to range from 1860-2100 sccm under the state of high-speed film formation, and the flow rate of the ammonia gas The range of the flow rate is 15400-17300 sccm; the range of the flow rate of the silane is 600-700 sccm, and the range of the flow rate of the ammonia gas is 7600-9000 sccm under the low-speed film-forming state. 5. The method for manufacturing the array substrate according to claim 1, wherein the first contact hole is formed by an etching process, and when the active layer thin film is etched at a position corresponding to the first contact hole, the The feed gas of the etching process includes sulfur hexafluoride gas, helium and chlorine gas, the flow rate range of the sulfur hexafluoride is 310sccm-500sccm, and the flow rate range of the helium is 100sccm-300sccm, so The flow range of the chlorine gas is 2100sccm-2200sccm, the pressure range of the etching process is 40-50mTorr, and the power range of the etching process is 5000-6000W; corresponding to the first contact hole When etching the first insulating layer at the position, the gas introduced into the etching process includes sulfur hexafluoride gas, oxygen and helium gas, the flow rate of the sulfur hexafluoride is in the range of 510sccm-600sccm, and the helium The flow rate of the gas ranges from 600 sccm to 1000 sccm, and the pressure range of the etching process is 160-170 mTorr. 6. The method for manufacturing an array substrate according to any one of claims 1 to 5, further comprising: Before the step of forming the first metal layer on the substrate, a third metal layer is formed on the substrate, and the third metal layer in the non-display area is patterned to form a third metal layer. lead; forming a second insulating layer covering the third lead on the substrate, the third lead and the second insulating layer being formed between the first metal layer and the substrate; The first insulating layer and the active layer thin film are formed on the second insulating layer, and the active layer thin film, the first insulating layer and the second insulating layer in the non-display area The insulating layer is patterned to form a second contact hole penetrating through the active layer film, the first insulating layer and the second insulating layer, and the etching rate of the second insulating layer is less than or equal to that of the first insulating layer. Etching rate of an insulating layer; The second lead is filled into the second contact hole and electrically connected with the third lead. 7. An array substrate, characterized in that, the array substrate is manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 6.