CN102738062A - Method for manufacturing semiconductor device - Google Patents

Abstract

The invention discloses a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate and an intermediate metal layer formed on the semiconductor substrate; forming an etching stop layer of a top metal layer on the intermediate metal layer; Baking the semiconductor substrate; washing the etching stop layer with a rinse agent; forming a dielectric material layer on the etching stop layer. In the method of the present invention, by adding baking and rinsing steps in the process of forming the top metal layer, it can effectively prevent the etch stop layer from releasing stress to form a peeling source in the subsequent process of forming a dielectric material layer, thereby avoiding the formation of peeling sources in the dielectric material layer. The formation of peeling defects and possible peeling phenomena in the electrical material layer. Further, it can prevent the peeling defect and peeling phenomenon from affecting the subsequent process, thereby improving the yield rate of the chip.

Description

Method of making semiconductor device

technical field

The invention relates to a semiconductor device manufacturing process, in particular to a method for manufacturing a semiconductor device.

Background technique

Today's semiconductor device manufacturing technology is developing rapidly, semiconductor devices already have a deep submicron structure, and integrated circuits contain a huge number of semiconductor components. In such large-scale integrated circuits, high-performance, high-density connections between components are not only interconnected in a single interconnect layer, but also interconnected between multiple layers. Therefore, a multilayer interconnection structure is usually adopted, especially a multilayer interconnection structure formed by a dual-damascene process, which pre-forms trenches (trench) and holes (via) in the interlayer dielectric layer, The aforementioned trenches and holes are then filled with a conductive material such as copper (Cu). Finally, an aluminum wiring layer is formed on the top metal layer, so that interconnect structures in the device are all connected to the surface aluminum wiring layer.

FIG. 1A is a cross-sectional view of a conventional interconnection structure formed by a dual damascene process. As shown in FIG. 1A, the interconnection structure is formed in multiple interlayer dielectric layers 110, 130 and 150, which are sequentially deposited on a semiconductor substrate (not shown). The bottom metal layer 110b, the middle metal layer 130b and the top metal layer 150b are formed in the interlayer dielectric layers 120, 130 and 150, respectively. The interconnect structure may include a plurality of intermediate metal layers 130b and a plurality of interlayer dielectric layers 130 surrounding the intermediate metal layers 130b. The contact hole 110a formed in the interlayer dielectric layer 110 is used to connect the bottom metal layer 110b and an element (not shown) formed on the surface of the semiconductor substrate. Likewise, the via holes 130a and 150a formed in the interlayer dielectric layers 130 and 150 are used to connect the bottom metal layer 110b and the middle metal layer 130b and the middle metal layer 130b and the top metal layer 150b. When the interconnection structure includes multiple intermediate metal layers 130b, the via hole 130a is also used to connect two adjacent intermediate metal layers 130b. An aluminum wiring layer 170 is formed on the top metal layer 150b, and the aluminum wiring layer 170 includes passivation layers 171-174 and an aluminum pad (Al pad) 170a.

FIG. 1B shows a cross-sectional view during fabrication of the top metal layer 150b shown in FIG. 1A. As shown in FIG. 1B , first, a thinner etch stop layer 151 is first formed on the interlayer dielectric layer 130, and the material of the etch stop layer 151 is usually silicon nitride; A thicker dielectric material layer 152, the material of the dielectric material layer 152 is usually undoped silica glass (USG); then, a hard mask layer 153 is formed on the dielectric material layer 152, the hard mask The material of layer 153 is usually silicon oxynitride; finally, a patterned photoresist layer is formed on the hard mask layer 153, and vias and grooves are formed in the interlayer dielectric layer 150 through steps such as exposure and development. The vias and trenches are then filled with Cu to form a top metal layer (not shown).

In order to reduce the parasitic capacitance between interconnected metals, the interlayer dielectric layer 130 is usually made of a material with a low dielectric constant, for example, black diamond (black diamond, BD) and the like. However, due to the uneven stress distribution between the black diamond and the silicon nitride, the adhesion between the etch stop layer 151 and the interlayer dielectric layer 130 is poor. When a thicker dielectric material layer 152 is further formed on the etch stop layer 151 , the peeling source is easily formed in the etch stop layer 151 . In the subsequent process of forming the dielectric material layer 152, the etch stop layer 151 will peel off in the edge region of the entire semiconductor substrate, and the peeled particles will be further embedded in the dielectric material layer 152, and in the dielectric material layer 152 The formation of peeling defects may eventually lead to peeling of the dielectric material layer 152 . These peeling defects and peeling particles will have a great impact on subsequent processes and reduce the yield of chips.

Therefore, it is necessary to provide a method for making a semiconductor device, so as to avoid the formation of peeling defects or possible peeling phenomena in the interlayer dielectric layer in the process of forming the top metal layer, and prevent the peeling defects and peeling phenomena from affecting subsequent processes. Influence, and then improve the yield rate of the chip.

Contents of the invention

In order to avoid the formation of peeling defects or possible peeling phenomena in the interlayer dielectric layer during the formation of the top metal layer, the present invention proposes a method for manufacturing a semiconductor device, including: providing a semiconductor substrate and forming An intermediate metal layer on a semiconductor substrate; forming an etch stop layer of a top metal layer on the intermediate metal layer; performing a baking step on the semiconductor substrate; performing a rinse step on the etch stop layer using a rinse agent ; forming a dielectric material layer on the etch stop layer.

Preferably, said method further comprises the step of forming vias and a top metal layer in said layer of dielectric material.

Preferably, the baking temperature in the baking step is the same as the temperature for forming the dielectric material layer.

Preferably, the baking time of the baking step is the same as the forming time of the dielectric material layer.

Preferably, the material of the dielectric material layer is plasma-enhanced oxide.

Preferably, the plasma-enhanced oxide is undoped silica glass or fluorine-containing silica glass.

Preferably, the baking temperature is 350 ^° C-450 ^° C.

Preferably, the baking temperature is 380 ^° C-420 ^° C.

Preferably, the baking time is 50-250 seconds.

Preferably, the baking time is 100-200 seconds.

Preferably, the flushing agent is one or more of helium, argon and nitrogen.

Preferably, the flushing agent is nitrogen, and the flow rate of the nitrogen is 60-100 cubic centimeters per minute.

Preferably, the rinsing agent further includes deionized water, and the deionized water is sprayed out under the pressure of the nitrogen gas.

Preferably, after the rinsing step, the step of rotating the semiconductor substrate to dry the semiconductor substrate is also included.

Preferably, during said rinsing, said semiconductor substrate is rotated.

Preferably, the rotation speed of the semiconductor substrate is 400-600 rpm.

Preferably, the flushing time is 20-40 seconds.

Preferably, the flushing time is 25-35 seconds.

Preferably, the material of the etching stop layer is silicon nitride or silicon nitride containing carbon.

In the method of the present invention, by adding baking and rinsing steps in the process of forming the top metal layer, it can effectively prevent the etch stop layer from releasing stress to form a peeling source in the subsequent process of forming the dielectric material layer, thereby avoiding the formation of the peeling source in the dielectric material layer. The formation of peeling defects and possible peeling phenomena in the electrical material layer. Further, it can prevent the peeling defect and peeling phenomenon from affecting the subsequent process, thereby improving the yield rate of the chip.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention. In the attached picture,

FIG. 1A is a cross-sectional view of an existing interconnection structure formed by a dual damascene process;

Figure 1B shows a cross-sectional view during the fabrication of the top metal layer shown in Figure 1A;

FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to one aspect of the present invention;

Figure 3 is a cross-sectional view during fabrication of a top metal layer in accordance with one aspect of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

FIG. 2 is a flowchart of a method for fabricating a semiconductor device according to one aspect of the present invention, and FIG. 3 is a cross-sectional view during fabrication of a top metal layer according to one aspect of the present invention. The method for manufacturing a semiconductor device of the present invention will be described below with reference to FIG. 2 and FIG. 3 .

Step 201 is executed to provide a semiconductor substrate and an intermediate metal layer formed on the semiconductor substrate.

The above structure will be described in detail below with reference to FIG. 3 . First provide a semiconductor substrate (not shown), and then form a bottom metal layer 310b and an intermediate metal layer 330b on the semiconductor substrate, wherein the bottom metal layer 310b and the intermediate metal layer 330b are respectively formed on the interlayer dielectric layers 310 and 330 middle. It should be understood that although only one intermediate metal layer 330b is shown in FIG. The interlayer dielectric layer 330 of the metal layer 330b. A plurality of intermediate metal layers 330 b and an interlayer dielectric layer 330 are sequentially formed on the bottom metal layer 310 b and the interlayer dielectric layer 310 . In order to reduce the parasitic capacitance between interconnected metal layers, the interlayer dielectric layer 330 is usually made of a material with a small dielectric constant, such as black diamond (black diamond, BD) and the like.

A contact hole 310 a is formed in the interlayer dielectric layer 310 below the bottom metal layer 310 b, and the contact hole 310 a is used to connect the bottom metal layer 310 b with an element structure (not shown) formed on the surface of the semiconductor substrate. The element structure includes a gate, a source, a drain, a word line or a resistor and the like. A via hole 330a is formed in the interlayer dielectric layer 330 below the intermediate metal layer 330b, and the via hole 330a is used to connect the bottom metal layer 310b and the intermediate metal layer 330b. When the above structure includes a plurality of intermediate metal layers 330b, the via hole 330a is also used to connect two adjacent intermediate metal layers 330b.

Step 202 is executed to form an etch stop layer of the top metal layer on the middle metal layer.

Referring to FIG. 3 , an etch stop layer 351 is formed on the intermediate metal layer 330 b and the interlayer dielectric layer 330 , and the material of the etch stop layer 351 may be silicon nitride or silicon nitride containing carbon (NDC). The etch stop layer 351 can be used as an etch stop layer when the dielectric material layer (not shown) is subsequently etched. The etching stop layer 351 may be formed by chemical vapor deposition, physical vapor deposition or sputtering.

Step 203 is executed to bake the semiconductor substrate.

Preferably, the baking temperature in the baking step is the same as the temperature at which the dielectric material layer is formed later, so as to avoid affecting the formation process of the subsequent dielectric material layer and ensure the reliability of the subsequent process. According to an embodiment of the present invention, the material of the dielectric material layer is undoped silica glass (USG), or fluorine-containing silica glass (FSG). Usually, the deposition temperature of the dielectric material layer is 350 ^° C-450 ^° C, therefore, the baking temperature of the baking step is 350 ^° C-450 ^° C. Preferably, the baking temperature can be 380 ^° C-420 ^° C.

Preferably, the baking time of the baking step is the same as the subsequent forming time of the dielectric material layer. When the dielectric material layer is formed by chemical vapor deposition or physical vapor deposition, the formation time refers to the effective time used to deposit the dielectric material layer, excluding additional process time such as vacuuming, heating and cooling. When the dielectric material layer is formed by sputtering, the formation time refers to the effective time used for sputtering the dielectric material layer, excluding additional process time such as vacuuming, heating and cooling. According to one embodiment of the present invention, the material of the dielectric material layer is undoped silicon glass. Usually, the forming time of the dielectric material layer is 50-250 seconds, therefore, the baking time of the baking step is 50-250 seconds. Second. Preferably, the baking temperature may be 100-200 seconds.

Step 204 is executed, using a rinse agent to rinse the etch stop layer. Preferably, the semiconductor substrate is rotated during rinsing. Rotating the semiconductor substrate during the rinsing process can not only improve the uniformity of rinsing, but also prevent the rinsing agent from staying on the surface of the etching stop layer for a long time by rotating the semiconductor substrate, thereby preventing the rinsing agent from affecting the etching stop layer. Usually, the semiconductor substrate is fixed on the chassis, and the semiconductor substrate can be driven to rotate by rotating the chassis. Preferably, the rotation speed of the semiconductor substrate is 400-600 rpm. More preferably, the rotation speed of the semiconductor substrate is 450-550 rpm. Preferably, the flushing time is 20-40 seconds. More preferably, the flushing time is 25-35 seconds.

The flushing agent may be one or more of inert gases such as helium, argon and nitrogen. Considering the production cost, preferably, the flushing agent is nitrogen. During flushing, the flow rate of nitrogen gas may be 60-100 cubic centimeters per minute, preferably, the flow rate of nitrogen gas is 80 cubic centimeters per minute.

In order to improve the rinsing capability of the particles on the etch stop layer, preferably, the rinsing agent further includes deionized water, and the deionized water is sprayed out under the pressure of nitrogen gas. However, it should be noted that when the rinsing agent includes deionized water, it is usually suitable for the etch stop layer to be made of non-water-absorbing material. When the etch stop layer is made of a water-absorbing material, such as carbon-containing silicon nitride (NDC), it is usually selected that the rinse agent does not contain deionized water. In addition, when the rinsing agent includes deionized water, the rinsing step further includes a step of rotating the semiconductor substrate to dry the semiconductor substrate. the

Through the above baking step, the stress generated during the deposition of the etch stop layer can be released. Taking silicon nitride as the material of the etching stop layer as an example, excess nitrogen and silicon embedded in the silicon nitride lattice can be diffused to the surface of the etching stop layer through the baking step to form silicon nitride particles. Then, the silicon nitride particles on the surface of the etching stop layer are removed through the subsequent washing step. In this way, during the subsequent process of forming the dielectric material layer, the etch stop layer releases stress and forms a peeling source, thereby avoiding the formation of peeling defects or possible peeling phenomena in the dielectric material layer.

Step 205 is executed to form a dielectric material layer on the etching stop layer.

The material of the dielectric material layer may be plasma-enhanced oxide (PEOX), for example, undoped silica glass (USG) or fluorine-containing silica glass (FSG). The method for forming the dielectric material layer may be chemical vapor deposition, physical vapor deposition or sputtering.

In addition, the method for manufacturing a semiconductor device according to the present invention further includes the step of forming a via hole and a top metal layer in the dielectric material layer, the via hole being used to connect the middle metal layer and the top metal layer. Forming the via hole and the top metal layer can adopt common methods in the field. According to one embodiment of the present invention, a hard mask layer and a patterned photoresist layer are sequentially formed on the dielectric material layer; The layer is etched to form vias and trenches in the dielectric material layer; finally, the vias and trenches are filled with metal. It can be understood that this method is only an embodiment of the present invention, and does not constitute a limitation of the present invention.

In the method of the present invention, by adding baking and rinsing steps in the process of forming the top metal layer, it can effectively prevent the etch stop layer from releasing stress to form a peeling source in the subsequent process of forming a dielectric material layer, thereby avoiding the formation of peeling sources in the dielectric material layer. The formation of peeling defects and possible peeling phenomena in the electrical material layer. Further, it can prevent the peeling defect and peeling phenomenon from affecting the subsequent process, thereby improving the yield rate of the chip.

A semiconductor device manufactured according to the embodiments described above can be applied to various integrated circuits (ICs). An IC according to the invention is, for example, a memory circuit such as Random Access Memory (RAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Static RAM (SRAM), or Read Only Memory (ROM) or the like. An IC according to the invention may also be a logic device, such as a programmable logic array (PLA), an application specific integrated circuit (ASIC), a merged DRAM logic integrated circuit (buried DRAM), a radio frequency circuit or any other circuit device. The IC chip according to the present invention can be used in consumer electronic products such as personal computers, portable computers, game machines, cellular phones, personal digital assistants, video cameras, digital cameras, mobile phones, etc., especially in radio frequency products.

The present invention has been described through the above embodiments, but it should be understood that the above embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention within the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (19)

1. A method of making a semiconductor device, comprising: providing a semiconductor substrate and an intermediate metal layer formed on the semiconductor substrate; forming an etch stop layer of a top metal layer on the middle metal layer; performing a baking step on the semiconductor substrate; performing a rinsing step on the etch stop layer using a rinsing agent; A dielectric material layer is formed on the etch stop layer. 2. The method of claim 1, further comprising the step of forming vias and a top metal layer in the layer of dielectric material. 3. The method according to claim 1, wherein the baking temperature in the baking step is the same as the temperature for forming the dielectric material layer. 4. The method according to claim 1, wherein the baking time of the baking step is the same as the forming time of the dielectric material layer. 5. The method of claim 1, wherein the material of the dielectric material layer is a plasma-enhanced oxide. 6 . The method according to claim 5 , wherein the plasma-enhanced oxide is undoped silica glass or fluorine-containing silica glass. 7. The method according to claim 6, characterized in that, the baking temperature is 350 ^° C-450 ^° C. 8. The method according to claim 7, characterized in that, the baking temperature is 380 ^° C-420 ^° C. 9. The method according to claim 6, characterized in that, the baking time is 50-250 seconds. 10. The method according to claim 9, characterized in that, the baking time is 100-200 seconds. 11. The method according to claim 1, wherein the flushing agent is one or more of helium, argon and nitrogen. 12. The method according to claim 1, wherein the flushing agent is nitrogen, and the flow rate of the nitrogen is 60-100 cubic centimeters/min. 13. The method according to claim 12, wherein the flushing agent further comprises deionized water, and the deionized water is sprayed under the nitrogen pressure. 14. The method according to claim 13, further comprising a step of rotating the semiconductor substrate to dry the semiconductor substrate after the rinsing step. 15. The method of claim 1, wherein during the rinsing, the semiconductor substrate is rotated. 16. The method according to claim 15, wherein the rotation speed of the semiconductor substrate is 400-600 rpm. 17. The method according to claim 1, characterized in that, the flushing time is 20-40 seconds. 18. The method according to claim 17, characterized in that the flushing time is 25-35 seconds. 19. The method according to claim 1, wherein the etching stop layer is made of silicon nitride or silicon nitride containing carbon.

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