CN102723289A - Normal chip single-faced three-dimensional circuit manufacture method by encapsulation prior to etching and normal chip single-faced three-dimensional circuit encapsulation structure - Google Patents
Normal chip single-faced three-dimensional circuit manufacture method by encapsulation prior to etching and normal chip single-faced three-dimensional circuit encapsulation structure Download PDFInfo
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
Description
技术领域 technical field
本发明涉及一种芯片正装单面三维线路先封后蚀制造方法及其封装结构,属于半导体封装技术领域。 The invention relates to a method for manufacturing a single-sided three-dimensional circuit of a front-mounted chip by sealing first and then etching and the packaging structure thereof, belonging to the technical field of semiconductor packaging.
背景技术 Background technique
传统的高密度基板封装结构的制造工艺流程如下所示: The manufacturing process flow of the traditional high-density substrate package structure is as follows:
步骤一、参见图85,取一玻璃纤维材料制成的基板, Step 1, referring to Figure 85, take a substrate made of glass fiber material,
步骤二、参见图86,在玻璃纤维基板上所需的位置上开孔,
步骤三、参见图87,在玻璃纤维基板的背面披覆一层铜箔,
步骤四、参见图88,在玻璃纤维基板打孔的位置填入导电物质,
步骤五、参见图89,在玻璃纤维基板的正面披覆一层铜箔,
步骤六、参见图90,在玻璃纤维基板表面披覆光阻膜,
步骤七、参见图91,将光阻膜在需要的位置进行曝光显影开窗,
步骤八、参见图92,将完成开窗的部分进行蚀刻,
步骤九、参见图93,将基板表面的光阻膜剥除,
步骤十、参见图94,在铜箔线路层的表面进行防焊漆(俗称绿漆)的披覆,
步骤十一、参见图95,在防焊漆需要进行后工序的装片以及打线键合的区域进行开窗,
步骤十二、参见图96,在步骤十一进行开窗的区域进行电镀,相对形成基岛和引脚,
步骤十三、完成后续的装片、打线、包封、切割等相关工序。 Step thirteen, complete subsequent related processes such as film loading, wire bonding, encapsulation, and cutting.
上述传统高密度基板封装结构存在以下不足和缺陷: The above-mentioned traditional high-density substrate packaging structure has the following deficiencies and defects:
1、多了一层的玻璃纤维材料,同样的也多了一层玻璃纤维的成本; 1. There is an extra layer of glass fiber material, and also the cost of an extra layer of glass fiber;
2、因为必须要用到玻璃纤维,所以就多了一层玻璃纤维厚度约100~150μm的厚度空间; 2. Because glass fiber must be used, there is an extra layer of glass fiber thickness of about 100~150μm;
3、玻璃纤维本身就是一种发泡物质,所以容易因为放置的时间与环境吸入水分以及湿气,直接影响到可靠性的安全能力或是可靠性的等级; 3. Glass fiber itself is a kind of foaming material, so it is easy to absorb moisture and moisture due to the storage time and environment, which directly affects the safety capability or reliability level of reliability;
4、玻璃纤维表面被覆了一层约50~100μm的铜箔金属层厚度,而金属层线路与线路的蚀刻距离也因为蚀刻因子的特性只能做到50~100μm的蚀刻间隙(参见图97,最好的制作能力是蚀刻间隙约等同于被蚀刻物体的厚度),所以无法真正的做到高密度线路的设计与制造; 4. The surface of the glass fiber is covered with a copper foil metal layer thickness of about 50-100 μm, and the etching distance between the metal layer line and the line can only achieve an etching gap of 50-100 μm due to the characteristics of the etching factor (see Figure 97, The best production capacity is that the etching gap is approximately equal to the thickness of the etched object), so it is impossible to truly design and manufacture high-density circuits;
5、因为必须要使用到铜箔金属层,而铜箔金属层是采用高压粘贴的方式,所以铜箔的厚度很难低于50μm的厚度,否则就很难操作如不平整或是铜箔破损或是铜箔延展移位等等; 5. Because the copper foil metal layer must be used, and the copper foil metal layer is pasted by high pressure, so the thickness of the copper foil is difficult to be less than 50μm, otherwise it will be difficult to operate such as unevenness or copper foil damage Or the extension and displacement of copper foil, etc.;
6、也因为整个基板材料是采用玻璃纤维材料,所以明显的增加了玻璃纤维层的厚度100~150μm,无法真正的做到超薄的封装; 6. Also because the entire substrate material is made of glass fiber material, the thickness of the glass fiber layer is obviously increased by 100~150 μm, and it is impossible to achieve ultra-thin packaging;
7、传统玻璃纤维加贴铜箔的工艺技术因为材质特性差异很大(膨胀系数),在恶劣环境的工序中容易造成应力变形,直接的影响到元件装载的精度以及元件与基板粘着性与可靠性。 7. Due to the large difference in material properties (expansion coefficient), the traditional glass fiber plus copper foil technology is easy to cause stress deformation in the harsh environment process, which directly affects the accuracy of component loading and the adhesion and reliability of components and substrates. sex.
发明内容 Contents of the invention
本发明的目的在于克服上述不足,提供一种芯片正装单面三维线路先封后蚀制造方法及其封装结构,其工艺简单,不需使用玻璃纤维层,减少了制造成本,提高了封装体的安全性和可靠性,减少了玻璃纤维材料带来的环境污染,而且金属基板线路层采用的是电镀方法,能够真正做到高密度线路的设计和制造。 The object of the present invention is to overcome the above-mentioned shortcomings, and provide a method for manufacturing single-sided three-dimensional circuits of a chip, which is sealed first and then etched, and its packaging structure. Safety and reliability reduce the environmental pollution caused by glass fiber materials, and the metal substrate circuit layer adopts the electroplating method, which can truly achieve the design and manufacture of high-density circuits.
本发明的目的是这样实现的:一种芯片正装单面三维线路先封后蚀制造方法,它包括以下工艺步骤: The object of the present invention is achieved like this: a kind of chip positively mounted single-sided three-dimensional circuit first seals back etching manufacturing method, and it comprises the following process steps:
步骤一、取金属基板 Step 1. Take the metal substrate
步骤二、金属基板表面预镀铜材
在金属基板表面电镀一层铜材薄膜, Electroplate a layer of copper film on the surface of the metal substrate,
步骤三、绿漆披覆
在步骤二完成预镀铜材薄膜的金属基板正面及背面进行绿漆的被覆,
In
步骤四、金属基板正面去除部分绿漆
利用曝光显影设备在步骤三完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域;
Use the exposure and development equipment to complete the pattern exposure, development and window opening on the front of the metal substrate coated with green paint in
步骤五、电镀惰性金属线路层
将步骤四金属基板正面已完成开窗的图形区域电镀上惰性金属线路层,
Electroplate the inert metal circuit layer on the pattern area where the window has been opened on the front side of the metal substrate in
步骤六、电镀金属线路层
在步骤五中的惰性金属线路层表面镀上金属线路层, Metal circuit layer is plated on the surface of inert metal circuit layer in step five,
步骤七、绿漆披覆
在步骤六完成电镀金属线路层的金属基板正面再次进行绿漆的被覆,
In
步骤八、金属基板正面去除部分绿漆
利用曝光显影设备在步骤七完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域,
Use the exposure and development equipment to complete the pattern exposure, development and window opening on the front of the metal substrate coated with green paint in
步骤九、电镀金属线路层
将步骤八金属基板正面已完成开窗的图形区域电镀上金属线路层,
Electroplate the metal circuit layer on the pattern area where the window has been opened on the front of the metal substrate in
步骤十、绿漆披覆
在步骤九完成电镀金属线路层的金属基板正面再次进行绿漆的被覆,
In
步骤十一、金属基板正面去除部分绿漆
利用曝光显影设备在步骤十完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域, Use the exposure and development equipment to perform pattern exposure, development and window opening on the front of the metal substrate coated with green paint in step ten, so as to expose the pattern area on the front of the metal substrate that needs to be electroplated later,
步骤十二、覆上线路网板
在金属基板正面覆上线路网板, Cover the circuit board on the front of the metal substrate,
步骤十三、金属化前处理
对步骤十一金属基板正面已完成开窗的图形区域进行电镀金属线路层的金属化前处理,
Carry out pre-metallization treatment of the electroplated metal circuit layer on the graphic area where the window has been opened on the front side of the metal substrate in
步骤十四、移除线路网板
将步骤十二中金属基板正面覆上的线路网板移除,
Remove the circuit board covered on the front side of the metal substrate in
步骤十五、电镀金属线路层
将步骤十三金属基板正面完成电镀金属线路层前处理的区域电镀上金属线路层,所述金属线路层电镀完成后即在金属基板正面相对形成引脚或基岛和引脚或基岛、引脚和静电释放圈的上部,
The metal circuit layer is electroplated on the area where the metal circuit layer pretreatment is completed on the front side of the metal substrate in
步骤十六、涂覆粘结物质
当步骤十五仅相对形成引脚上部时,在引脚上部涂覆导电或是不导电的粘结物质;当步骤十五相对形成的基岛和引脚上部或基岛、引脚和静电释放圈上部时,在基岛上部正面涂覆导电或是不导电的粘结物质,
When only the upper part of the pin is relatively formed in
步骤十七、装片 Step seventeen, loading film
在步骤十六引脚或基岛上部正面涂覆的导电或不导电粘结物质上进行芯片的植入, Chip implantation is carried out on the conductive or non-conductive adhesive substance coated on the front surface of the sixteen pins or the base island,
步骤十八、金属线键合 Step 18. Wire Bonding
在芯片正面与引脚正面之间进行键合金属线作业, Wire bonding between the front side of the chip and the front side of the pins,
步骤十九、包封 Step nineteen, encapsulation
将步骤十八完成装片打线后的金属基板正面进行包封塑封料作业, Encapsulate the front side of the metal substrate after step 18 has completed chip loading and wiring,
步骤二十、金属基板背面去除部分绿漆 Step 20. Remove part of the green paint on the back of the metal substrate
利用曝光显影设备对金属基板背面披覆的绿漆进行图形曝光、显影以及开窗,以露出金属基板背面后续需要进行化学蚀刻的图形区域, Use exposure and development equipment to perform graphic exposure, development and window opening on the green paint coated on the back of the metal substrate to expose the pattern area on the back of the metal substrate that needs to be chemically etched later.
步骤二十一、化学蚀刻 Step 21. Chemical etching
将步骤二十中金属基板背面完成开窗的图形区域进行化学蚀刻, Perform chemical etching on the graphic area where the windows are opened on the back of the metal substrate in step 20,
步骤二十二、电镀金属线路层 Step 22: Electroplating the metal circuit layer
在步骤二十一完成化学蚀刻后露出的惰性金属线路层表面进行金属线路层的电镀,金属线路层电镀完成后即在金属基板背面相对形成引脚或基岛和引脚或基岛、引脚和静电释放圈的下部, The surface of the inert metal circuit layer exposed after the chemical etching is completed in step 21 is electroplated on the metal circuit layer. After the electroplating of the metal circuit layer is completed, pins or base islands and pins or base islands and pins are relatively formed on the back of the metal substrate. and the lower part of the ESD collar,
步骤二十三、绿漆披覆 Step 23, green paint coating
在步骤二十二完成电镀金属线路层的金属基板背面进行绿漆的被覆; In step 22, the backside of the metal substrate of the electroplated metal circuit layer is covered with green paint;
步骤二十四、绿漆表面开孔 Step 24. Open holes on the surface of the green paint
在步骤二十三金属基板背面披覆的绿漆表面进行后续要植金属球区域的开孔作业, On the surface of the green paint coated on the back of the metal substrate in step 23, carry out the subsequent drilling work in the area where the metal balls will be planted,
步骤二十五、清洗 Step twenty-five, cleaning
对步骤二十四金属基板背面绿漆开孔处进行清洗 Clean the green paint opening on the back of the metal substrate in step 24
步骤二十六、植球 Step twenty-six, planting the ball
在步骤二十五经过清洗的小孔内植入金属球, Insert a metal ball into the cleaned hole in step 25,
步骤二十七、切割成品 Step 27. Cut the finished product
将步骤二十六完成植球的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得芯片正装单面三维线路先封后蚀封装结构成品。 Cut the semi-finished products that have been ball-planted in step 26, so that the plastic package modules that were originally integrated in the form of an array assembly and contain chips are cut and separated one by one to obtain a single-sided three-dimensional circuit-first package for chip packaging The finished package structure is etched back.
一种芯片正装单面三维线路先封后蚀制造方法的封装结构,它包括引脚,所述引脚正面通过导电或不导电粘结物质设置有芯片,所述芯片正面与引脚正面之间用金属线相连接,所述引脚外围的区域、引脚与引脚之间的区域以及引脚下部的区域包封有绿漆,所述引脚上部的区域以及芯片和金属线外包封有塑封料,所述引脚下部的绿漆表面上开设有小孔,所述小孔与引脚背面相连通,所述小孔内设置有金属球,所述金属球与引脚背面相接触, A packaging structure of a single-sided three-dimensional circuit on a chip is sealed first and then etched. It includes pins, and the front of the pins is provided with a chip through a conductive or non-conductive adhesive substance. Connected with metal wires, the peripheral area of the pins, the area between the pins and the lower part of the pins are covered with green paint, and the upper part of the pins and the outer chip and metal wires are covered with green paint. Molding compound, the green paint surface of the lower part of the pin is provided with a small hole, the small hole communicates with the back of the pin, and a metal ball is arranged in the small hole, and the metal ball is in contact with the back of the pin.
所述步骤二十五对金属基板背面绿漆开孔处进行清洗同时进行金属保护层被覆。 In the twenty-fifth step, the green paint opening on the back of the metal substrate is cleaned and the metal protective layer is coated at the same time.
所述封装结构包括基岛,此时芯片通过导电或不导电粘结物质设置于基岛正面。 The packaging structure includes a base island, and at this time, the chip is arranged on the front surface of the base island through a conductive or non-conductive adhesive substance.
所述基岛有单个或多个。 There are single or multiple base islands.
所述基岛与引脚之间设置有静电释放圈,所述静电释放圈正面与芯片正面之间通过金属线相连接。 An electrostatic discharge ring is arranged between the base island and the pins, and the front of the electrostatic discharge ring is connected to the front of the chip by a metal wire. the
与现有技术相比,本发明具有以下有益效果: Compared with the prior art, the present invention has the following beneficial effects:
1、本发明不需要使用玻璃纤维层,所以可以减少玻璃纤维层所带来的成本; 1. The present invention does not need to use the glass fiber layer, so the cost brought by the glass fiber layer can be reduced;
2、本发明没有使用玻璃纤维层的发泡物质,所以可靠性的等级可以再提高,相对对封装体的安全性就会提高; 2. The present invention does not use the foaming material of the glass fiber layer, so the reliability level can be further improved, and the relative safety of the package will be improved;
3、本发明不需要使用玻璃纤维层物质,所以就可以减少玻璃纤维材料所带来的环境污染; 3. The present invention does not need to use glass fiber material, so the environmental pollution caused by glass fiber material can be reduced;
4、本发明的三维金属基板线路层所采用的是电镀方法,而电镀层的总厚度约在10~15μm,而线路与线路之间的间隙可以轻松的达到25μm以下的间隙,所以可以真正地做到高密度内引脚线路平铺的技术能力; 4. The circuit layer of the three-dimensional metal substrate of the present invention adopts the electroplating method, and the total thickness of the electroplating layer is about 10-15 μm, and the gap between the lines can easily reach a gap below 25 μm, so it can be truly The technical ability to achieve high-density internal pin line tiling;
5、本发明的三维金属基板因采用的是金属层电镀法,所以比玻璃纤维高压铜箔金属层的工艺来得简单,且不会有金属层因为高压产生金属层不平整、金属层破损以及金属层延展移位的不良或困惑; 5. The three-dimensional metal substrate of the present invention adopts the metal layer electroplating method, so it is simpler than the process of glass fiber high-voltage copper foil metal layer, and there will be no metal layer unevenness, metal layer damage and metal layer due to high pressure. Poor or confused layer extension and displacement;
6、本发明的三维金属基板线路层是在金属基材的表面进行金属电镀,所以材质特性基本相同,所以镀层线路与金属基材的内应力基本相同,可以轻松的进行恶劣环境的后工程(如高温共晶装片、高温锡材焊料装片以及高温被动元件的表面贴装工作)而不容易产生应力变形。 6. The three-dimensional metal substrate circuit layer of the present invention is metal electroplated on the surface of the metal substrate, so the material properties are basically the same, so the internal stress of the plating circuit and the metal substrate is basically the same, and the post-engineering in harsh environments can be easily carried out ( Such as high-temperature eutectic chip mounting, high-temperature tin solder chip mounting, and surface mount work of high-temperature passive components) are not prone to stress deformation.
附图说明 Description of drawings
图1~图27为本发明芯片正装单面三维线路先封后蚀制造方法实施例一的各工序示意图。 Figures 1 to 27 are schematic diagrams of each process in Embodiment 1 of the method for manufacturing a single-sided three-dimensional circuit on a front-mounted chip of the present invention, which is sealed first and then etched.
图28为本发明芯片正装单面三维线路先封后蚀封装结构实施例一的结构示意图。 Fig. 28 is a structural schematic diagram of Embodiment 1 of the chip front-mount single-sided three-dimensional circuit sealing first and then etching packaging structure of the present invention.
图29~图55为本发明芯片正装单面三维线路先封后蚀制造方法实施例二的各工序示意图。
29 to 55 are schematic diagrams of each process in
图56为本发明芯片正装单面三维线路先封后蚀封装结构实施例二的结构示意图。
Fig. 56 is a structural schematic diagram of
图57~图83为本发明芯片正装单面三维线路先封后蚀制造方法实施例三的各工序示意图。
57 to 83 are schematic diagrams of each process in
图84为本发明芯片正装单面三维线路先封后蚀封装结构实施例三的结构示意图。
Fig. 84 is a structural schematic diagram of
图85~图96为传统的高密度基板封装结构的制造工艺流程的各工序示意图。 85 to 96 are schematic diagrams of each process of the manufacturing process flow of the traditional high-density substrate packaging structure.
图97为玻璃纤维表面铜箔金属层的蚀刻状况示意图。 Fig. 97 is a schematic diagram of the etching status of the copper foil metal layer on the surface of the glass fiber.
其中: in:
金属基板1 Metal Substrate 1
铜材薄膜2
绿漆3
惰性金属线路层4
Inert
金属线路层5
线路网板6
金属化前处理层7
导电或不导电粘结物质8 Conductive or non-conductive bonding substances8
芯片9
金属线10
塑封料11
小孔12
金属保护层13
金属球14
引脚15
基岛16
静电释放圈17。
具体实施方式 Detailed ways
本发明芯片正装单面三维线路先封后蚀制造方法包括以下工艺步骤: The manufacturing method of the chip front-mounted single-sided three-dimensional circuit of the present invention is sealed first and then etched, including the following process steps:
实施例一、无基岛 Embodiment 1, no base island
步骤一、取金属基板 Step 1. Take the metal substrate
参见图1,取一片厚度合适的金属基板,所述金属基板的材质可以依据芯片的功能与特性进行变换,例如:铜材、铁材、镍铁材或锌铁材等; Referring to Figure 1, take a metal substrate with a suitable thickness. The material of the metal substrate can be changed according to the functions and characteristics of the chip, for example: copper, iron, nickel-iron or zinc-iron;
步骤二、金属基板表面预镀铜材
参见图2,在金属基板表面电镀一层铜材薄膜,目的是为后续电镀作基础,所述电镀的方式可以采用化学镀或是电解电镀; Referring to Figure 2, a layer of copper film is electroplated on the surface of the metal substrate, the purpose is to serve as the basis for subsequent electroplating, and the electroplating method can be electroless plating or electrolytic plating;
步骤三、绿漆披覆
参见图3,在步骤二完成预镀铜材薄膜的金属基板正面及背面进行绿漆的被覆,以保护后续的电镀金属层工艺作业;
Referring to Figure 3, in
步骤四、金属基板正面去除部分绿漆
参见图4,利用曝光显影设备在步骤三完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域;
Referring to Figure 4, use the exposure and development equipment to complete the pattern exposure, development and window opening on the front of the metal substrate coated with green paint in
步骤五、电镀惰性金属线路层
参见图5,将步骤四金属基板正面已完成开窗的图形区域电镀上惰性金属线路层,作为后续蚀刻作业的阻挡层,所述惰性金属线路层材料采用镍、钛或铜等,所述电镀方式采用化学镀或电解电镀方式; Referring to Fig. 5, an inert metal circuit layer is electroplated on the graphic area where the window has been opened on the front side of the metal substrate in step four, as a barrier layer for subsequent etching operations. The material of the inert metal circuit layer is nickel, titanium or copper, etc., and the electroplating The method adopts chemical plating or electrolytic plating;
步骤六、电镀金属线路层
参见图6,在步骤五中的惰性金属线路层表面镀上金属线路层,所述金属线路层可以是单层或多层,所述金属线路层材料采用银、铝、铜、镍金或镍钯金等,所述电镀方式可以是化学电镀也可以是电解电镀的方式; Referring to Fig. 6, a metal circuit layer is plated on the surface of the inert metal circuit layer in step five, and the metal circuit layer can be single-layer or multilayer, and the material of the metal circuit layer is silver, aluminum, copper, nickel gold or nickel Palladium, gold, etc., the electroplating method can be chemical plating or electrolytic plating;
步骤七、绿漆披覆
参见图7,在步骤六完成电镀金属线路层的金属基板正面再次进行绿漆的被覆,以保护后续的电镀金属层工艺作业;
Referring to Fig. 7, in
步骤八、金属基板正面去除部分绿漆
参见图8,利用曝光显影设备在步骤七完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域;
Referring to Figure 8, use the exposure and development equipment to complete the pattern exposure, development and window opening on the front of the metal substrate coated with green paint in
步骤九、电镀金属线路层
参见图9,将步骤八金属基板正面已完成开窗的图形区域电镀上金属线路层,所述金属线路层可以是单层或多层,所述金属线路层材料采用银、铝、铜、镍金或镍钯金等,所述电镀方式可以是化学电镀也可以是电解电镀的方式; Referring to Fig. 9, the metal circuit layer is electroplated on the graphic area where the window has been opened on the front side of the metal substrate in step eight. The metal circuit layer can be a single layer or multiple layers, and the metal circuit layer material is silver, aluminum, copper, nickel Gold or nickel-palladium-gold, etc., the electroplating method can be chemical electroplating or electrolytic electroplating;
步骤十、绿漆披覆
参见图10,在步骤九完成电镀金属线路层的金属基板正面再次进行绿漆的被覆,以保护后续的电镀金属层工艺作业;
Referring to FIG. 10 , in
步骤十一、金属基板正面去除部分绿漆
参见图11,利用曝光显影设备在步骤十完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域; Referring to Fig. 11, use the exposure and development equipment to perform pattern exposure, development and window opening on the front of the metal substrate coated with green paint in step ten, so as to expose the pattern area that needs to be electroplated on the front of the metal substrate;
步骤十二、覆上线路网板
参见图12,在金属基板正面覆上线路网板,线路网板覆盖后续不需要进行金属化的区域; Referring to Figure 12, the front of the metal substrate is covered with a circuit board, and the circuit board covers the area that does not need to be metallized in the future;
步骤十三、金属化前处理
参见图13,对步骤十一金属基板正面已完成开窗的图形区域进行电镀金属线路层的金属化前处理,所述金属化前处理方式可采用涂布、喷洒、印刷、淋涂或浸泡等方式;
Referring to Figure 13, perform metallization pre-treatment on the metallization circuit layer of the electroplated metal circuit layer on the graphics area on the front of the metal substrate in
步骤十四、移除线路网板
参见图14,将步骤十二中金属基板正面覆上的线路网板移除;
Referring to Figure 14, remove the circuit board covered on the front side of the metal substrate in
步骤十五、电镀金属线路层
参见图15,将步骤十三金属基板正面完成电镀金属线路层前处理的区域电镀上金属线路层,所述金属线路层电镀完成后即在金属基板正面相对形成引脚的上部,所述金属线路层可以是单层或多层,所述金属线路层材料采用银、铝、铜、镍金或镍钯金等,所述电镀方式可以是化学电镀也可以是电解电镀的方式;
Referring to Fig. 15, the metal circuit layer is electroplated on the area where the metal circuit layer pretreatment is completed on the front side of the metal substrate in
步骤十六、涂覆粘结物质
参见图16,在步骤十五相对形成的引脚上部正面涂覆导电或是不导电的粘结物质,目的是为后续芯片植入后与引脚的接合; Referring to Fig. 16, the upper surface of the upper part of the pins formed oppositely in step fifteen is coated with a conductive or non-conductive adhesive substance, the purpose of which is to bond with the pins after the subsequent chip implantation;
步骤十七、装片 Step seventeen, loading film
参见图17,在步骤十六引脚上部正面涂覆的导电或不导电粘结物质上进行芯片的植入; Referring to Fig. 17, chip implantation is carried out on the conductive or non-conductive bonding substance coated on the upper surface of the sixteen pins;
芯片植入可以有单个或多个,若植入的芯片为多个时,后续还要进行芯片正面与芯片正面之间的金属线键合作业; There can be one or more chips implanted. If there are multiple chips implanted, the metal wire bonding operation between the front of the chip and the front of the chip will be carried out later;
步骤十八、金属线键合 Step 18. Wire Bonding
参见图18,在芯片正面与引脚正面之间进行键合金属线作业,所述金属线的材料采用金、银、铜、铝或合金材料,金属线的形状可以是丝状也可以是带状; Referring to Figure 18, the metal wire bonding operation is carried out between the front side of the chip and the front side of the pin. The material of the metal wire is gold, silver, copper, aluminum or alloy materials, and the shape of the metal wire can be filament or ribbon. shape;
步骤十九、包封 Step nineteen, encapsulation
参见图19,将步骤十八完成装片打线后的金属基板正面进行包封塑封料作业,塑封料的包封方式可以采用模具灌胶方式、喷涂方式或刷胶方式,所述塑封料可以采用有填料物质或是无填料物质的环氧树脂; Referring to Figure 19, encapsulate the front of the metal substrate after step 18 has been loaded and wired. The encapsulation method of the plastic compound can be mold filling, spraying or brushing. The plastic compound can be Epoxy resins with or without fillers;
步骤二十、金属基板背面去除部分绿漆 Step 20. Remove part of the green paint on the back of the metal substrate
参见图20,利用曝光显影设备对金属基板背面披覆的绿漆进行图形曝光、显影以及开窗,以露出金属基板背面后续需要进行化学蚀刻的图形区域; Referring to Fig. 20, the green paint coated on the back of the metal substrate is exposed, developed, and opened with an exposure and developing device to expose the graphic area that needs to be chemically etched on the back of the metal substrate;
步骤二十一、化学蚀刻 Step 21. Chemical etching
参见图21,将步骤二十中金属基板背面完成开窗的图形区域进行化学蚀刻,化学蚀刻直至惰性金属线路层的位置为止,蚀刻药水可以采用氯化铜或是氯化铁; Referring to Fig. 21, chemically etch the graphic area where the window is opened on the back of the metal substrate in step 20, until the position of the inert metal circuit layer is chemically etched, and the etching solution can be copper chloride or ferric chloride;
步骤二十二、电镀金属线路层 Step 22: Electroplating the metal circuit layer
参见图22,在步骤二十一完成化学蚀刻后露出的惰性金属线路层表面进行金属线路层的电镀,金属线路层电镀完成后即在金属基板背面相对形成引脚的下部,所述金属线路层可以是单层或多层,所述金属线路层材料采用铜镍金、铜镍银、钯金、金或铜等,所述电镀方法可以是化学电镀或是电解电镀; Referring to FIG. 22, the surface of the inert metal circuit layer exposed after the chemical etching in step 21 is electroplated on the metal circuit layer. After the metal circuit layer is electroplated, the lower part of the pin is relatively formed on the back of the metal substrate. The metal circuit layer It can be single-layer or multi-layer, and the material of the metal circuit layer is copper-nickel-gold, copper-nickel-silver, palladium-gold, gold or copper, etc., and the electroplating method can be chemical plating or electrolytic plating;
步骤二十三、绿漆披覆 Step 23, green paint coating
参见图23,在步骤二十二完成电镀金属线路层的金属基板背面进行绿漆的被覆; Referring to FIG. 23 , in step 22, the backside of the metal substrate of the electroplated metal circuit layer is covered with green paint;
步骤二十四、绿漆表面开孔 Step 24. Open holes on the surface of the green paint
参见图24,在步骤二十三金属基板背面披覆的绿漆表面进行后续要植金属球区域的开孔作业,所述开孔方式可以采用干式激光烧结或是湿式化学腐蚀的方法; Referring to FIG. 24 , in step 23, the green paint surface coated on the back of the metal substrate is followed by opening operations in the area where metal balls are to be planted. The opening method can be dry laser sintering or wet chemical etching;
步骤二十五、清洗 Step twenty-five, cleaning
参见图25,对步骤二十四金属基板背面绿漆开孔处进行清洗以去除氧化物质或有机物质等,同时可进行金属保护层的被覆,金属保护层采用抗氧化剂; Referring to Figure 25, clean the openings of the green paint on the back of the metal substrate in step 24 to remove oxidized substances or organic substances, etc., and at the same time coat the metal protective layer, which uses an antioxidant;
步骤二十六、植球 Step twenty-six, planting the ball
参见图26,在步骤二十五经过清洗的小孔内植入金属球,金属球与引脚的背面相接触,所述植球方式可以采用常规的植球机或是采用金属膏印刷再经高温溶解之后即可形成球状体,金属球的材料可以是纯锡或锡合金; Referring to Figure 26, metal balls are implanted in the cleaned holes in step 25, and the metal balls are in contact with the back of the pins. The ball planting method can be a conventional ball planting machine or a metal paste printing process. Spheroids can be formed after high-temperature dissolution, and the material of the metal balls can be pure tin or tin alloy;
步骤二十七、切割成品 Step 27. Cut the finished product
参见图27,将步骤二十六完成植球的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得芯片正装单面三维线路先封后蚀封装结构成品。 Referring to Figure 27, the semi-finished product that has completed the ball planting in step 26 is cut, so that the plastic package modules that are originally integrated in the form of an array assembly and contain chips are cut and separated one by one, and the single-sided chip is obtained. The three-dimensional circuit is first sealed and then etched into the finished package structure.
实施例一的封装结构如下: The packaging structure of Embodiment 1 is as follows:
参见图28,本发明芯片正装单面三维线路先封后蚀封装结构,它包括引脚15,所述引脚15正面通过导电或不导电粘结物质8设置有芯片9,所述芯片9正面与引脚15正面之间用金属线10相连接,所述引脚15外围的区域、引脚15与引脚15之间的区域以及引脚15下部的区域包封有绿漆3,所述引脚15上部的区域以及芯片9和金属线10外包封有塑封料11,所述引脚15下部的绿漆3表面上开设有小孔12,所述小孔12与引脚15背面相连通,所述小孔12内设置有金属球14,所述金属球14与引脚15背面相接触,所述金属球14与引脚15背面之间设置有金属保护层13,所述金属保护层13为抗氧化剂。
Referring to Fig. 28, the present invention has a single-sided three-dimensional circuit packaging structure that is first sealed and then etched. It includes
实施例二、有基岛
步骤一、取金属基板 Step 1. Take the metal substrate
参见图29,取一片厚度合适的金属基板,所述金属基板的材质可以依据芯片的功能与特性进行变换,例如:铜材、铁材、镍铁材或锌铁材等; Referring to Figure 29, take a metal substrate with a suitable thickness. The material of the metal substrate can be changed according to the functions and characteristics of the chip, for example: copper, iron, nickel-iron or zinc-iron;
步骤二、金属基板表面预镀铜材
参见图30,在金属基板表面电镀一层铜材薄膜,目的是为后续电镀作基础,所述电镀的方式可以采用化学镀或是电解电镀; Referring to Figure 30, a layer of copper film is electroplated on the surface of the metal substrate, the purpose is to serve as the basis for subsequent electroplating, and the electroplating method can be electroless plating or electrolytic plating;
步骤三、绿漆披覆
参见图31,在步骤二完成预镀铜材薄膜的金属基板正面及背面进行绿漆的被覆,以保护后续的电镀金属层工艺作业;
Referring to Figure 31, in
步骤四、金属基板正面去除部分绿漆
参见图32,利用曝光显影设备在步骤三完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域;
Referring to Figure 32, use the exposure and development equipment to complete the pattern exposure, development and window opening on the front of the metal substrate coated with green paint in
步骤五、电镀惰性金属线路层
参见图33,将步骤四金属基板正面已完成开窗的图形区域电镀上惰性金属线路层,作为后续蚀刻作业的阻挡层,所述惰性金属线路层材料采用镍、钛或铜等,所述电镀方式采用化学镀或电解电镀方式;
Referring to Fig. 33, electroplating an inert metal circuit layer on the graphic area of the front of the metal substrate in
步骤六、电镀金属线路层
参见图34,在步骤五中的惰性金属线路层表面镀上金属线路层,所述金属线路层可以是单层或多层,所述金属线路层材料采用银、铝、铜、镍金或镍钯金等,所述电镀方式可以是化学电镀也可以是电解电镀的方式; Referring to Fig. 34, a metal circuit layer is plated on the surface of the inert metal circuit layer in step five, and the metal circuit layer can be a single layer or multiple layers, and the material of the metal circuit layer is silver, aluminum, copper, nickel gold or nickel Palladium, gold, etc., the electroplating method can be chemical plating or electrolytic plating;
步骤七、绿漆披覆
参见图35,在步骤六完成电镀金属线路层的金属基板正面再次进行绿漆的被覆,以保护后续的电镀金属层工艺作业; Referring to FIG. 35 , in step six, the front of the metal substrate on which the electroplating metal circuit layer is completed is coated with green paint again to protect the subsequent electroplating metal layer process operations;
步骤八、金属基板正面去除部分绿漆
参见图36,利用曝光显影设备在步骤七完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域;
Referring to Figure 36, use the exposure and development equipment to complete the pattern exposure, development and window opening on the front of the metal substrate covered with green paint in
步骤九、电镀金属线路层
参见图37,将步骤八金属基板正面已完成开窗的图形区域电镀上金属线路层,所述金属线路层可以是单层或多层,所述金属线路层材料采用银、铝、铜、镍金或镍钯金等,所述电镀方式可以是化学电镀也可以是电解电镀的方式; Referring to Fig. 37, electroplate the metal circuit layer on the graphic area where the window has been opened on the front side of the metal substrate in step eight. The metal circuit layer can be single-layer or multi-layer. The material of the metal circuit layer is silver, aluminum, copper, nickel Gold or nickel-palladium-gold, etc., the electroplating method can be chemical electroplating or electrolytic electroplating;
步骤十、绿漆披覆
参见图38,在步骤九完成电镀金属线路层的金属基板正面再次进行绿漆的被覆,以保护后续的电镀金属层工艺作业; Referring to FIG. 38 , in step nine, the front of the metal substrate on which the electroplating metal circuit layer is completed is coated with green paint again to protect the subsequent electroplating metal layer process operations;
步骤十一、金属基板正面去除部分绿漆
参见图39,利用曝光显影设备在步骤十完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域; Referring to Fig. 39, use the exposure and development equipment to perform graphic exposure, development and window opening on the front of the metal substrate coated with green paint in step ten, so as to expose the pattern area that needs to be electroplated on the front of the metal substrate;
步骤十二、覆上线路网板
参见图40,在金属基板正面覆上线路网板,线路网板覆盖后续不需要进行金属化的区域; Referring to Fig. 40, the circuit board is covered on the front of the metal substrate, and the circuit board covers the area that does not need to be metallized in the future;
步骤十三、金属化前处理
参见图41,对步骤十一金属基板正面已完成开窗的图形区域进行电镀金属线路层的金属化前处理,所述金属化前处理方式可采用涂布、喷洒、印刷或淋涂等方式;
Referring to Figure 41, perform metallization pre-treatment on the metallized circuit layer on the pattern area where the window has been opened on the front side of the metal substrate in
步骤十四、移除线路网板
参见图42,将步骤十二中金属基板正面覆上的线路网板移除;
Referring to Figure 42, remove the circuit board covered on the front side of the metal substrate in
步骤十五、电镀金属线路层
参见图43,将步骤十三金属基板正面完成电镀金属线路层前处理的区域电镀上金属线路层,所述金属线路层电镀完成后即在金属基板正面相对形成基岛和引脚的上部,所述金属线路层可以是单层或多层,所述金属线路层材料采用银、铝、铜、镍金或镍钯金等,所述电镀方式可以是化学电镀也可以是电解电镀的方式;
Referring to Fig. 43, the metal circuit layer is electroplated on the area where the pre-treatment of the metal circuit layer is electroplated on the front of the metal substrate in
步骤十六、涂覆粘结物质
参见图44,在步骤十五相对形成的基岛上部正面涂覆导电或是不导电的粘结物质,目的是为后续芯片植入后与引脚的接合; Referring to Fig. 44, a conductive or non-conductive adhesive substance is coated on the upper surface of the base island formed oppositely in step fifteen, for the purpose of bonding with the pins after subsequent chip implantation;
步骤十七、装片 Step seventeen, loading film
参见图45,在步骤十六基岛上部正面涂覆的导电或不导电粘结物质上进行芯片的植入; Referring to FIG. 45, chip implantation is carried out on the conductive or non-conductive adhesive substance coated on the upper surface of the sixteen base island in the step;
芯片植入可以有单个或多个,若植入的芯片为多个时,后续还要进行芯片正面与芯片正面之间的金属线键合作业; There can be one or more chips implanted. If there are multiple chips implanted, the metal wire bonding operation between the front of the chip and the front of the chip will be carried out later;
步骤十八、金属线键合 Step 18. Wire Bonding
参见图46,在芯片正面与引脚正面之间进行键合金属线作业,所述金属线的材料采用金、银、铜、铝或合金材料,金属线的形状可以是丝状也可以是带状; Referring to Figure 46, the metal wire is bonded between the front side of the chip and the front side of the pin. The material of the metal wire is gold, silver, copper, aluminum or an alloy material, and the shape of the metal wire can be filament or ribbon. shape;
步骤十九、包封 Step nineteen, encapsulation
参见图47,将步骤十八完成装片打线后的金属基板正面进行包封塑封料作业,塑封料的包封方式可以采用模具灌胶方式、喷涂方式或刷胶方式,所述塑封料可以采用有填料物质或是无填料物质的环氧树脂; Referring to Fig. 47, encapsulate the front side of the metal substrate after step 18 is finished with chip loading and wire bonding. The encapsulation method of the plastic compound can be mold filling, spraying or brushing. The plastic compound can be Epoxy resins with or without fillers;
步骤二十、金属基板背面去除部分绿漆 Step 20. Remove part of the green paint on the back of the metal substrate
参见图48,利用曝光显影设备对金属基板背面披覆的绿漆进行图形曝光、显影以及开窗,以露出金属基板背面后续需要进行化学蚀刻的图形区域; Referring to Fig. 48, the green paint coated on the back of the metal substrate is exposed, developed, and opened with an exposure and developing device to expose the pattern area that needs to be chemically etched on the back of the metal substrate;
步骤二十一、化学蚀刻 Step 21. Chemical etching
参见图49,将步骤二十中金属基板背面完成开窗的图形区域进行化学蚀刻,化学蚀刻直至惰性金属线路层的位置为止,蚀刻药水可以采用氯化铜或是氯化铁; Referring to Fig. 49, chemically etch the graphic area where the window is opened on the back of the metal substrate in step 20 until the position of the inert metal circuit layer is chemically etched. The etching solution can be copper chloride or ferric chloride;
步骤二十二、电镀金属线路层 Step 22: Electroplating the metal circuit layer
参见图50,在步骤二十一完成化学蚀刻后露出的惰性金属线路层表面进行金属线路层的电镀,金属线路层电镀完成后即在金属基板背面相对形成基岛和引脚的下部,所述金属线路层可以是单层或多层,所述金属线路层材料采用铜镍金、铜镍银、钯金、金或铜等,所述电镀方法可以是化学电镀或是电解电镀; Referring to FIG. 50 , the surface of the inert metal circuit layer exposed after the chemical etching is completed in step 21 is electroplated on the metal circuit layer. After the metal circuit layer is electroplated, the base island and the lower part of the pin are relatively formed on the back of the metal substrate. The metal circuit layer can be single-layer or multi-layer, and the material of the metal circuit layer is copper-nickel-gold, copper-nickel-silver, palladium-gold, gold or copper, etc. The electroplating method can be chemical electroplating or electrolytic electroplating;
步骤二十三、绿漆披覆 Step 23, green paint coating
参见图51,在步骤二十二完成电镀金属线路层的金属基板背面进行绿漆的被覆; Referring to FIG. 51 , in step 22, the backside of the metal substrate on which the metal circuit layer is electroplated is covered with green paint;
步骤二十四、绿漆表面开孔 Step 24. Open holes on the surface of the green paint
参见图52,在步骤二十三金属基板背面披覆的绿漆表面进行后续要植金属球区域的开孔作业,所述开孔方式可以采用干式激光烧结或是湿式化学腐蚀的方法; Referring to Fig. 52, on the surface of the green paint coated on the back of the metal substrate in step 23, the hole opening operation of the area to be planted with metal balls is carried out. The hole opening method can be dry laser sintering or wet chemical etching;
步骤二十五、清洗 Step twenty-five, cleaning
参见图53,对步骤二十四金属基板背面绿漆开孔处进行清洗以去除氧化物质或有机物质等,同时可进行金属保护层的被覆,金属保护层采用抗氧化剂; Referring to Figure 53, clean the openings of the green paint on the back of the metal substrate in step 24 to remove oxidized substances or organic substances, and at the same time coat the metal protective layer, which uses an antioxidant;
步骤二十六、植球 Step twenty-six, planting the ball
参见图54,在步骤二十五经过清洗的小孔内植入金属球,金属球与引脚的背面相接触,所述植球方式可以采用常规的植球机或是采用金属膏印刷再经高温溶解之后即可形成球状体,金属球的材料可以是纯锡或锡合金; Referring to Figure 54, metal balls are implanted in the cleaned holes in step 25, and the metal balls are in contact with the back of the pins. The ball planting method can be a conventional ball planting machine or a metal paste printing process. Spheroids can be formed after high-temperature dissolution, and the material of the metal balls can be pure tin or tin alloy;
步骤二十七、切割成品 Step 27. Cut the finished product
参见图55,将步骤二十六完成植球的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得芯片正装单面三维线路先封后蚀封装结构成品。 Referring to Figure 55, the semi-finished products that have completed the ball planting in step 26 are cut, so that the plastic package modules that are originally integrated in an array form and contain chips are cut and separated one by one, and the single-sided chips are obtained. The three-dimensional circuit is first sealed and then etched into the finished package structure.
实施例二的封装结构如下: The packaging structure of the second embodiment is as follows:
参见图56,本发明芯片正装单面三维线路先封后蚀封装结构,它包括基岛16和引脚15,所述基岛16正面通过导电或不导电粘结物质8设置有芯片9,所述芯片9正面与引脚15正面之间用金属线10相连接,所述基岛16外围的区域、基岛16和引脚15之间的区域、引脚15与引脚15之间的区域以及基岛16和引脚16下部的区域包封有绿漆3,所述基岛16和引脚15上部的区域以及芯片9和金属线10外包封有塑封料11,所述引脚15下部的绿漆3表面上开设有小孔12,所述小孔12与引脚15背面相连通,所述小孔12内设置有金属球14,所述金属球14与引脚15背面相接触,所述金属球14与引脚15背面之间设置有金属保护层13,所述金属保护层13为抗氧化剂。
Referring to Fig. 56 , the package structure of the present invention for front-mounted single-sided three-dimensional circuit sealing before etching includes a
实施例三、有基岛静电释放圈
步骤一、取金属基板 Step 1. Take the metal substrate
参见图57,取一片厚度合适的金属基板,所述金属基板的材质可以依据芯片的功能与特性进行变换,例如:铜材、铁材、镍铁材或锌铁材等; Referring to Figure 57, take a metal substrate with a suitable thickness. The material of the metal substrate can be changed according to the functions and characteristics of the chip, for example: copper, iron, nickel-iron or zinc-iron;
步骤二、金属基板表面预镀铜材
参见图58,在金属基板表面电镀一层铜材薄膜,目的是为后续电镀作基础,所述电镀的方式可以采用化学镀或是电解电镀; Referring to Figure 58, a layer of copper film is electroplated on the surface of the metal substrate, the purpose is to serve as the basis for subsequent electroplating, and the electroplating method can be electroless plating or electrolytic plating;
步骤三、绿漆披覆
参见图59,在步骤二完成预镀铜材薄膜的金属基板正面及背面进行绿漆的被覆,以保护后续的电镀金属层工艺作业;
Referring to Figure 59, in
步骤四、金属基板正面去除部分绿漆
参见图60,利用曝光显影设备在步骤三完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域;
Referring to Figure 60, use the exposure and developing equipment to complete the pattern exposure, development and window opening on the front of the metal substrate covered with green paint in
步骤五、电镀惰性金属线路层
参见图61,将步骤四金属基板正面已完成开窗的图形区域电镀上惰性金属线路层,作为后续蚀刻作业的阻挡层,所述惰性金属线路层材料采用镍、钛或铜等,所述电镀方式采用化学镀或电解电镀方式;
Referring to Fig. 61, electroplating an inert metal circuit layer on the graphic area of the front side of the metal substrate that has been windowed in
步骤六、电镀金属线路层
参见图62,在步骤五中的惰性金属线路层表面镀上金属线路层,所述金属线路层可以是单层或多层,所述金属线路层材料采用银、铝、铜、镍金或镍钯金等,所述电镀方式可以是化学电镀也可以是电解电镀的方式; Referring to Fig. 62, a metal circuit layer is plated on the surface of the inert metal circuit layer in step five, and the metal circuit layer can be a single layer or multiple layers, and the material of the metal circuit layer is silver, aluminum, copper, nickel gold or nickel Palladium, gold, etc., the electroplating method can be chemical plating or electrolytic plating;
步骤七、绿漆披覆
参见图63,在步骤六完成电镀金属线路层的金属基板正面再次进行绿漆的被覆,以保护后续的电镀金属层工艺作业; Referring to FIG. 63 , in step six, the front side of the metal substrate on which the electroplating metal circuit layer is completed is coated with green paint again to protect the subsequent electroplating metal layer process operations;
步骤八、金属基板正面去除部分绿漆
参见图64,利用曝光显影设备在步骤七完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域;
Referring to Figure 64, use the exposure and development equipment to complete the pattern exposure, development and window opening on the front of the metal substrate coated with green paint in
步骤九、电镀金属线路层
参见图65,将步骤八金属基板正面已完成开窗的图形区域电镀上金属线路层,所述金属线路层可以是单层或多层,所述金属线路层材料采用银、铝、铜、镍金或镍钯金等,所述电镀方式可以是化学电镀也可以是电解电镀的方式; Referring to Fig. 65, electroplate the metal circuit layer on the graphic area where the window has been opened on the front side of the metal substrate in step eight. The metal circuit layer can be single layer or multi-layer, and the material of the metal circuit layer is silver, aluminum, copper, nickel Gold or nickel-palladium-gold, etc., the electroplating method can be chemical electroplating or electrolytic electroplating;
步骤十、绿漆披覆
参见图66,在步骤九完成电镀金属线路层的金属基板正面再次进行绿漆的被覆,以保护后续的电镀金属层工艺作业; Referring to FIG. 66 , in step nine, the front of the metal substrate on which the electroplating metal circuit layer is completed is coated with green paint again to protect the subsequent electroplating metal layer process operations;
步骤十一、金属基板正面去除部分绿漆
参见图67,利用曝光显影设备在步骤十完成绿漆披覆的金属基板正面进行图形曝光、显影以及开窗,以露出金属基板正面后续需要进行电镀的图形区域; Referring to Figure 67, use the exposure and development equipment to perform pattern exposure, development and window opening on the front of the metal substrate covered with green paint in step ten, so as to expose the pattern area that needs to be electroplated on the front of the metal substrate;
步骤十二、覆上线路网板
参见图68,在金属基板正面覆上线路网板,线路网板覆盖后续不需要进行金属化的区域; Referring to Fig. 68, the circuit board is covered on the front of the metal substrate, and the circuit board covers the area that does not need to be metallized in the future;
步骤十三、金属化前处理
参见图69,对步骤十一金属基板正面已完成开窗的图形区域进行电镀金属线路层的金属化前处理,所述金属化前处理方式可采用涂布、喷洒、印刷、淋涂或浸泡等方式; Referring to Figure 69, perform metallization pre-treatment on the metallized circuit layer on the graphic area where the window has been opened on the front of the metal substrate in step eleven. Way;
步骤十四、移除线路网板
参见图70,将步骤十二中金属基板正面覆上的线路网板移除;
Referring to Figure 70, remove the circuit board covered on the front side of the metal substrate in
步骤十五、电镀金属线路层
参见图71,将步骤十三金属基板正面完成电镀金属线路层前处理的区域电镀上金属线路层,所述金属线路层电镀完成后即在金属基板正面相对形成基岛、引脚和静电释放圈的上部,所述金属线路层可以是单层或多层,所述金属线路层材料采用银、铝、铜、镍金或镍钯金等,所述电镀方式可以是化学电镀也可以是电解电镀的方式;
Referring to Figure 71, the metal circuit layer is electroplated on the area where the pretreatment of the electroplating metal circuit layer is completed on the front of the metal substrate in
步骤十六、涂覆粘结物质
参见图72,在步骤十五相对形成的基岛上部正面涂覆导电或是不导电的粘结物质,目的是为后续芯片植入后与引脚的接合; Referring to Fig. 72, a conductive or non-conductive adhesive substance is coated on the upper surface of the base island formed oppositely in step fifteen, for the purpose of bonding with the pins after subsequent chip implantation;
步骤十七、装片 Step seventeen, loading film
参见图73,在步骤十六基岛上部正面涂覆的导电或不导电粘结物质上进行芯片的植入; Referring to FIG. 73 , chip implantation is performed on the conductive or non-conductive adhesive substance coated on the upper surface of the sixteen base island in the step;
芯片植入可以有单个或多个,若植入的芯片为多个时,后续还要进行芯片正面与芯片正面之间的金属线键合作业; There can be one or more chips implanted. If there are multiple chips implanted, the metal wire bonding operation between the front of the chip and the front of the chip will be carried out later;
步骤十八、金属线键合 Step 18. Wire Bonding
参见图74,在芯片正面与引脚正面之间以及芯片正面与静电释放圈之间进行键合金属线作业,所述金属线的材料采用金、银、铜、铝或合金材料,金属线的形状可以是丝状也可以是带状; Referring to Figure 74, the metal wire bonding operation is performed between the front of the chip and the front of the pins and between the front of the chip and the electrostatic discharge ring. The material of the metal wire is gold, silver, copper, aluminum or an alloy material, and the metal wire The shape can be filament or ribbon;
步骤十九、包封 Step nineteen, encapsulation
参见图75,将步骤十八完成装片打线后的金属基板正面进行包封塑封料作业,塑封料的包封方式可以采用模具灌胶方式、喷涂方式或刷胶方式,所述塑封料可以采用有填料物质或是无填料物质的环氧树脂; Referring to Figure 75, encapsulate the front of the metal substrate after step 18 has been loaded and wired. The encapsulation method of the plastic compound can be mold filling, spraying or brushing. The plastic compound can be Epoxy resins with or without fillers;
步骤二十、金属基板背面去除部分绿漆 Step 20. Remove part of the green paint on the back of the metal substrate
参见图76,利用曝光显影设备对金属基板背面披覆的绿漆进行图形曝光、显影以及开窗,以露出金属基板背面后续需要进行化学蚀刻的图形区域; Referring to Fig. 76, the green paint coated on the back of the metal substrate is subjected to graphic exposure, development and window opening by using the exposure and development equipment, so as to expose the pattern area on the back of the metal substrate that needs to be subsequently chemically etched;
步骤二十一、化学蚀刻 Step 21. Chemical etching
参见图77,将步骤二十中金属基板背面完成开窗的图形区域进行化学蚀刻,化学蚀刻直至惰性金属线路层的位置为止,蚀刻药水可以采用氯化铜或是氯化铁; Referring to Fig. 77, chemically etch the graphic area where the window is opened on the back of the metal substrate in step 20, until the position of the inert metal circuit layer is chemically etched, and the etching solution can be copper chloride or ferric chloride;
步骤二十二、电镀金属线路层 Step 22: Electroplating the metal circuit layer
参见图78,在步骤二十一完成化学蚀刻后露出的惰性金属线路层表面进行金属线路层的电镀,金属线路层电镀完成后即在金属基板背面相对形成基岛、引脚和静电释放圈的下部,所述金属线路层可以是单层或多层,所述金属线路层材料采用铜镍金、铜镍银、钯金、金或铜等,所述电镀方法可以是化学电镀或是电解电镀; Referring to FIG. 78, the surface of the inert metal circuit layer exposed after the chemical etching in step 21 is electroplated on the metal circuit layer. After the metal circuit layer is electroplated, base islands, pins and electrostatic discharge rings are relatively formed on the back of the metal substrate. In the lower part, the metal circuit layer can be single-layer or multi-layer, and the material of the metal circuit layer is copper-nickel-gold, copper-nickel-silver, palladium-gold, gold or copper, etc., and the electroplating method can be electroless plating or electrolytic plating ;
步骤二十三、绿漆披覆 Step 23, green paint coating
参见图79,在步骤二十二完成电镀金属线路层的金属基板背面进行绿漆的被覆; Referring to FIG. 79 , in step 22, the backside of the metal substrate on which the metal circuit layer is electroplated is covered with green paint;
步骤二十四、绿漆表面开孔 Step 24. Open holes on the surface of the green paint
参见图80,在步骤二十三金属基板背面披覆的绿漆表面进行后续要植金属球区域的开孔作业,所述开孔方式可以采用干式激光烧结或是湿式化学腐蚀的方法; Referring to FIG. 80 , on the surface of the green paint coated on the back of the metal substrate in step 23, the hole opening operation of the area to be planted with metal balls is carried out. The hole opening method can be dry laser sintering or wet chemical etching;
步骤二十五、清洗 Step twenty-five, cleaning
参见图81,对步骤二十四金属基板背面绿漆开孔处进行清洗以去除氧化物质或有机物质等,同时可进行金属保护层的被覆,金属保护层采用抗氧化剂; Referring to Figure 81, clean the green paint opening on the back of the metal substrate in step 24 to remove oxidized substances or organic substances, and at the same time coat the metal protective layer, which uses an antioxidant;
步骤二十六、植球 Step twenty-six, planting the ball
参见图82,在步骤二十五经过清洗的小孔内植入金属球,金属球与引脚的背面相接触,所述植球方式可以采用常规的植球机或是采用金属膏印刷再经高温溶解之后即可形成球状体,金属球的材料可以是纯锡或锡合金; Referring to Figure 82, metal balls are implanted in the cleaned holes in step 25, and the metal balls are in contact with the back of the pins. The ball planting method can be a conventional ball planting machine or metal paste printing and then printed. Spheroids can be formed after high-temperature dissolution, and the material of the metal balls can be pure tin or tin alloy;
步骤二十七、切割成品 Step 27. Cut the finished product
参见图93,将步骤二十六完成植球的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得芯片正装单面三维线路先封后蚀封装结构成品。 Referring to Figure 93, the semi-finished product that has completed the ball planting in step 26 is cut, so that the plastic package modules that are originally integrated in the form of an array assembly and contain chips are cut and separated one by one, and the single-sided chip is obtained. The three-dimensional circuit is first sealed and then etched into the finished package structure.
实施例三的封装结构如下: The packaging structure of the third embodiment is as follows:
参见图84,本发明芯片正装单面三维线路先封后蚀封装结构,它包括基岛16和引脚15,所述基岛16与引脚15之间设置有静电释放圈17,所述基岛16正面通过导电或不导电粘结物质8设置有芯片9,所述芯片9正面与引脚15正面之间以及芯片9正面与静电释放圈17之间用金属线10相连接,所述基岛16外围的区域、基岛16和引脚15之间的区域、引脚15与引脚15之间的区域以及基岛16和引脚15下部的区域包封有绿漆3,所述基岛16和引脚15上部的区域以及芯片9和金属线10外包封有塑封料11,所述引脚15下部的绿漆3表面上开设有小孔12,所述小孔12与引脚15背面相连通,所述小孔12内设置有金属球14,所述金属球14与引脚15背面相接触,所述金属球14与引脚15背面之间设置有金属保护层13,所述金属保护层13为抗氧化剂。
Referring to Fig. 84 , the package structure of the present invention, which is a single-sided three-dimensional circuit, is sealed first and then etched. It includes a
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103400772A (en) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | Packaging-prior-to-etching chip-normally-bonded type three-dimensional system-level metal circuit board structure and process method thereof |
CN103400773A (en) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | Packaging-prior-to-etching passive device type three-dimensional system-level metal circuit board structure and process method thereof |
CN103515249A (en) * | 2013-08-06 | 2014-01-15 | 江苏长电科技股份有限公司 | Firstly-packaged secondly-etched three-dimensional system level chip front-installed bump packaged structure and technology method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004327903A (en) * | 2003-04-28 | 2004-11-18 | Dainippon Printing Co Ltd | Resin sealed semiconductor device and its manufacturing method |
CN1691314A (en) * | 2004-04-21 | 2005-11-02 | 美龙翔微电子科技(深圳)有限公司 | Flip ball grid array packaging base plate and making technique thereof |
CN101840901A (en) * | 2010-04-30 | 2010-09-22 | 江苏长电科技股份有限公司 | Lead frame structure of static release ring without paddle and production method thereof |
CN102005432A (en) * | 2010-09-30 | 2011-04-06 | 江苏长电科技股份有限公司 | Packaging structure with four pin-less sides and packaging method thereof |
-
2012
- 2012-06-09 CN CN2012101900126A patent/CN102723289B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004327903A (en) * | 2003-04-28 | 2004-11-18 | Dainippon Printing Co Ltd | Resin sealed semiconductor device and its manufacturing method |
CN1691314A (en) * | 2004-04-21 | 2005-11-02 | 美龙翔微电子科技(深圳)有限公司 | Flip ball grid array packaging base plate and making technique thereof |
CN101840901A (en) * | 2010-04-30 | 2010-09-22 | 江苏长电科技股份有限公司 | Lead frame structure of static release ring without paddle and production method thereof |
CN102005432A (en) * | 2010-09-30 | 2011-04-06 | 江苏长电科技股份有限公司 | Packaging structure with four pin-less sides and packaging method thereof |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103400772A (en) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | Packaging-prior-to-etching chip-normally-bonded type three-dimensional system-level metal circuit board structure and process method thereof |
CN103400773A (en) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | Packaging-prior-to-etching passive device type three-dimensional system-level metal circuit board structure and process method thereof |
CN103515249A (en) * | 2013-08-06 | 2014-01-15 | 江苏长电科技股份有限公司 | Firstly-packaged secondly-etched three-dimensional system level chip front-installed bump packaged structure and technology method thereof |
CN103515249B (en) * | 2013-08-06 | 2016-02-24 | 江苏长电科技股份有限公司 | First be honored as a queen and lose three-dimensional systematic chip formal dress bump packaging structure and process |
CN103400773B (en) * | 2013-08-06 | 2016-06-08 | 江阴芯智联电子科技有限公司 | First it is honored as a queen and loses passive device three-dimensional systematic metal circuit board structure and process |
CN103400772B (en) * | 2013-08-06 | 2016-08-17 | 江阴芯智联电子科技有限公司 | First it is honored as a queen and loses chip formal dress three-dimensional systematic metallic circuit plate structure and process |
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