CN102709326B - Thin film transistor (TFT) and its manufacture method, array base palte and display device - Google Patents

Abstract

The invention discloses a kind of thin film transistor (TFT) and its manufacture method, array base palte and display device, it is related to display technology field, to reduce the leakage current of thin film transistor (TFT), improves TFT stability.A kind of thin film transistor (TFT), including grid, gate insulation layer, active layer and the source-drain electrode layer being formed on substrate, the source-drain electrode layer include source electrode and the drain electrode of the thin film transistor (TFT)；Wherein, the active layer uses metal-oxide semiconductor (MOS), and metal layer is equipped between the active layer and the gate insulation layer, to reduce the carrier capture effect between the active layer and gate insulation layer.The scheme that the embodiment of the present invention is provided is suitable for arbitrarily needing the display device being driven using thin film transistor (TFT).

Description

Thin film transistor and its manufacturing method, array substrate and display device

technical field

The invention relates to the field of display technology, in particular to a thin film transistor, a manufacturing method thereof, an array substrate and a display device.

Background technique

Thin Film Transistor-Liquid Crystal Display (TFT-LCD), which is relatively common at present, is mainly divided into active matrix liquid crystal display (AM-LCD) and passive matrix liquid crystal display (PM-LCD). Wherein, the active layer of the active matrix liquid crystal display is mainly composed of amorphous silicon (a-Si) or polycrystalline silicon (p-Si).

For a-Si TFT, the disadvantage is that the lower mobility and stability are greatly affected by temperature; for p-SiTFT, the disadvantage is that the uniformity of the deposited film is poor and the distribution of polycrystalline grain boundaries is different. Performance varies widely. Due to the above-mentioned defects of the thin film transistor with the silicon base as the active layer, the development of the liquid crystal display has been restricted, and it cannot meet the current needs gradually.

Among them, a-IGZO (amorphous-indium gallium zinc oxide) and other metal oxide semiconductors are used to replace the silicon base as the active layer of the thin film transistor, because it has little change to the original structure design of the TFT, and the other structures correspond to The process flow is basically unchanged, so the equipment modification is relatively simple; most importantly, the performance of thin film transistors based on metal oxide semiconductors such as a-IGZO has been significantly improved, which has attracted the attention of the display field, replacing silicon-based thin film transistors and becoming the next generation mainstream technology.

However, when thin-film transistors based on metal oxide semiconductors such as a-IGZO are exposed to water and oxygen in the external environment, or during the process of depositing and forming an etch barrier layer SiO2, oxygen atoms will pass through the active layer of a-IGZO TFT and Penetrate into the gate insulating layer; at the same time, in the working state, when the light from the backlight irradiates the array substrate, it will activate the external environment to generate a shallow energy level defect state, and carrier capture occurs at the interface between the active layer and the gate insulating layer effect, which in turn causes a relatively large leakage current, which affects the stability of the TFT.

Contents of the invention

Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate and a display device, which are used to reduce the leakage current of the thin film transistor and improve the stability of the TFT.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

A thin film transistor, comprising a gate formed on a substrate, a gate insulating layer, an active layer, and a source-drain electrode layer, the source-drain electrode layer including the source and drain electrodes of the thin film transistor; wherein, the The source layer adopts metal oxide semiconductor, and a metal layer is arranged between the active layer and the gate insulating layer to reduce the carrier trapping effect between the active layer and the gate insulating layer.

A method for manufacturing a thin film transistor, including the process of forming a gate, a gate insulating layer, an active layer, and a source-drain electrode layer on a substrate; wherein, the source-drain electrode layer includes the source and drain of the thin-film transistor; The active layer adopts a metal oxide semiconductor; and,

Between the step of forming the gate insulating layer and the step of forming the active layer, further comprising: forming a metal layer between the gate insulating layer and the active layer.

An array substrate, including the above-mentioned thin film transistor.

A display device includes the above-mentioned array substrate.

In the thin film transistor and its manufacturing method, array substrate, and display device provided by the embodiments of the present invention, a metal layer is provided between the active layer and the gate insulating layer of the oxide thin film transistor, thereby forming a gap between the active layer and the metal layer. The contact surface between the metal layer and the gate insulating layer; and at the contact surface between the metal layer and the gate insulating layer, a large number of carriers can be provided by the metal layer, effectively compensating the gate insulation The carrier trapping effect at the layer interface, so the carrier trapping effect at the interface can be ignored; compared with the existing oxide thin film transistor, the thin film transistor provided in this scheme can effectively reduce the leakage current of the thin film transistor and improve TFT stability.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only of the present invention. For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a thin film transistor provided in an embodiment of the present invention;

FIG. 2 is a first schematic diagram of the position of the metal layer 7 in FIG. 1;

FIG. 3 is a second schematic diagram of the position of the metal layer 7 in FIG. 1;

4 to 7 are schematic flow charts of a method for manufacturing a thin film transistor provided by an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention;

Reference signs: 1-substrate; 2-gate; 3-gate insulating layer; 4-active layer; 5-source; 6-drain; 7-metal layer; 8-etching barrier layer; 9-passivation layer; 10-pixel electrode.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

The thin film transistor, the manufacturing method thereof, the array substrate and the display device provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 1 , the thin film transistor provided by the embodiment of the present invention includes a gate 2 formed on a substrate 1, a gate insulating layer 3, an active layer 4 and a source-drain electrode layer, and the source-drain electrode layer includes the thin-film transistor. The source electrode 5 and the drain electrode 6; wherein, the active layer 4 adopts a metal oxide semiconductor, and a metal layer 7 is provided between the active layer 4 and the gate insulating layer 3, so as to reduce the Carrier trapping effect between gate insulating layers 3.

In the thin film transistor shown in Figure 1, the metal oxide semiconductor used in the active layer 4 can be but not limited to indium gallium zinc oxide a-IGZO; as long as it is a transparent oxide film with good semiconductor properties, it can be For the production of the active layer.

In FIG. 1 and the subsequent embodiments, the bottom-gate TFT is used as an example to introduce the structure of the thin film transistor provided by the present invention; for the top-gate TFT, those skilled in the art can modify it according to the idea of the present invention. I won't repeat them here. However, it should be noted that the top-gate TFT based on the improved idea of the present invention should also fall within the protection scope of the present invention.

Preferably, the material of the above-mentioned metal layer 7 can be metal titanium Ti; like this, at the contact surface between the metal Ti and the gate insulating layer 3, a large number of carriers can be provided by the Ti in the metal layer 7, effectively compensating the gate. The carrier trapping effect at the interface of the insulating layer, so the carrier trapping effect at the interface can be ignored, thereby reducing the threshold voltage of the TFT, increasing the on-state current, and reducing power consumption.

Further, a contact surface is also formed between the metal layer 7 and the active layer 4; since the active layer 4 uses a metal oxide semiconductor, taking a-IGZO as an example, the oxygen atoms in the a-IGZO material are easily absorbed Metal Ti is adsorbed, so a layer of titanium oxide TiOx film will be formed between the metal Ti and the active layer 4 (as shown in FIG. 2 ). The TiOx film can prevent the oxygen atoms in the a-IGZO active layer from further penetrating into the gate insulating layer, and avoid the oxygen defect state V[O] that causes the gate insulating layer to produce a shallow energy level, so it can also effectively reduce the thickness of the thin film transistor. Generation of operating leakage current.

Of course, the above metal layer 7 can also be selected from other metals, such as metal aluminum Al; similarly, on the contact surface between the metal Al and the gate metal layer, Al can provide sufficient carriers to compensate for the carrier trapping effect, and at the same time On the contact surface between the metal Al and the active layer, Al2O3 formed by oxidation of Al can prevent oxygen atoms in a-IGZO from diffusing to the gate insulating layer, thereby reducing the working leakage current of the TFT and improving the stability of the TFT.

In this embodiment, the active layer 4 completely covers the metal layer 7 . Specifically, reference may be made to the two structures shown in FIG. 2 and FIG. 3 . It can be seen from FIG. 2 that the active layer 4 is covered on the metal layer 7 to avoid TFT failure caused by the direct contact between the metal layer 7 and the source 5 and the drain 6; Layer 7 is embedded in gate insulating layer 3 to form the structure shown in FIG. 3 . As long as a metal layer is provided between the active layer 4 and the gate insulating layer 3, the structure used to reduce the TFT leakage current should fall within the protection scope of the present invention.

In addition, in the thin film transistor provided in this embodiment, an etch stop layer (Etch Stop Layer, ESL) 8 is further provided above the active layer.

In the thin film transistor provided in the embodiment of the present invention, a metal layer is provided between the active layer and the gate insulating layer of the oxide thin film transistor, thereby forming the contact surface between the active layer and the metal layer and the metal layer and the gate insulating layer. interface between layers. At the contact surface between the metal layer and the gate insulating layer, a large number of carriers can be provided by the metal layer, effectively compensating the carrier trapping effect at the interface of the gate insulating layer, so the carrier at the interface The trapping effect can be ignored, which can effectively increase the on-state current and reduce the power consumption of the thin film transistor; at the same time, at the contact surface between the active layer and the metal layer, the metal layer absorbs the oxygen in the active layer Atoms form a layer of metal oxide film, which prevents the oxygen atoms in the active layer from further penetrating into the gate insulating layer, avoids the deep energy level transition of the oxygen atoms in the gate insulating layer due to light, and also reduces the working leakage of the TFT. current.

Compared with the existing oxide thin film transistors, the thin film transistors provided in this solution effectively reduce the generation of leakage current, lower the threshold voltage, increase the on-state current, and reduce power consumption; Compared with the thin film transistor of the a-IGZO active layer, the thin film transistor in this embodiment greatly improves the stability of the TFT.

Corresponding to the above-mentioned thin film transistor, an embodiment of the present invention also provides a method for manufacturing a thin film transistor, including the process of sequentially forming a gate, a gate insulating layer, an active layer, and a source-drain electrode layer on a substrate; the source-drain electrodes The layer includes the source and the drain of the thin film transistor; wherein, the active layer adopts a metal oxide semiconductor; and,

After forming the gate insulating layer and before forming the active layer, the method further includes: forming a metal layer between the gate insulating layer and the active layer on the gate insulating layer.

The above thin film transistor manufacturing method will be further described in detail below. In the subsequent description, the bottom-gate TFT is still taken as an example, and reference may be made to FIG. 4 to FIG. 7 for details.

The thin film transistor manufacturing method in this embodiment specifically includes the following steps:

S1, deposit a gate metal thin film on the substrate 1, and form a gate line (not shown in the figure) and a gate 2 through a patterning process, as shown in Figure 4;

Wherein, the substrate 1 may be, but not limited to, a glass substrate, a quartz substrate or a substrate formed of organic materials.

S2. Depositing a gate insulating layer 3 on the substrate formed with the gate line and the gate 2, as shown in FIG. 5 ;

S3. Deposit a layer of metal thin film on the gate insulating layer 3, such as metal Ti, and form the pattern of the metal layer 7 through a patterning process, as shown in Figure 6, so that the metal layer 7 can be sandwiched between the gate insulating layer 3 and the active layer. between layers 4;

S4, in an Ar/O2 atmosphere, deposit an oxide semiconductor film, such as a-IGZO, on the metal layer 7, and form a pattern of the active layer 4 through a patterning process;

Wherein, the active layer 4 completely covers the metal layer 7 . As shown in FIG. 7 , the active layer 4 may be covered on the metal layer 7 so that the two sides of the metal layer 7 will not cause TFT failure due to contact with the source and drain of the thin film transistor.

Wherein, the pattern of the active layer 4 is formed through a patterning process, specifically: coating a photoresist on the oxide semiconductor film, performing exposure and development processes, and then forming an active layer 4 on the oxide semiconductor layer by wet etching. Layer 4 pattern.

In addition, after step S4 is completed, an etch stop layer 8 may also be formed above the active layer 4 to protect the active layer 4 in subsequent processes.

S5, annealing the active layer 4 in an oxygen atmosphere;

Under the Ar/O2 atmosphere, the oxygen atoms in the metal oxide such as a-IGZO in the active layer 4 diffuse toward the region with a lower oxygen content, that is, diffuse into the metal layer 7 .

In this embodiment, the metal layer 7 can be metal Ti, because Ti is easy to absorb oxygen atoms in the active layer, so after the annealing treatment, the titanium metal at the contact surface of the active layer 4 and the metal layer 7 It is easy to form a layer of TiOx oxide film when it is partially oxidized.

Specifically, during the annealing process, the metal oxide films such as a-IGZO in the active layer will be affected by the temperature, and the valence bonds will be activated to generate a certain amount of oxygen escape; since the annealing process is carried out under an oxygen atmosphere, the external The oxygen concentration is higher than the oxygen concentration of the active layer, and part of the oxygen diffuses to the active layer. The aforementioned two processes exist simultaneously during the annealing treatment, and by controlling the amount of oxygen passing through, the equilibrium state of oxygen escape and diffusion can be adjusted. Therefore, the above annealing process has little effect on the oxygen content of metal oxides such as a-IGZO in the active layer 4 .

In addition, the temperature-rising annealing can reduce the defect states in the a-IGZO active layer, make the interface from rough to smooth, and make the interface contact good.

S6. Deposit a layer of source-drain metal thin film on the active layer 4, and form the source 5 and drain 6 of the thin film transistor through a patterning process; the structure of the finally formed thin film transistor is shown in FIG. 1 .

Through the above steps, the fabrication of the thin film transistor can be completed.

If it is an array substrate manufacturing process, it is only necessary to continue to form structures such as a passivation layer and a pixel electrode layer on the substrate on which the above-mentioned thin film transistors have been formed. Since the subsequent process is similar to the existing array substrate manufacturing process, it will not be repeated here.

Although the above method descriptions all take the bottom-gate TFT as an example, those skilled in the art can easily combine the above-mentioned improvement ideas with the top-gate TFT, and realize the top-gate TFT through specific steps. Production process. The process of manufacturing a top-gate TFT using the improved concept of the present invention will not be repeated here; however, the method for manufacturing a top-gate TFT based on the improved concept of the present invention should fall within the protection scope of the present invention.

The scheme in the embodiment of the present invention designs the semiconductor a-IGZO thin film as an a-IGZO thin film active layer covering the metal layer Ti, thereby forming a dual-channel active layer, which not only achieves the purpose of blocking the oxide semiconductor active layer Oxygen atoms cross into the gate insulating layer to reduce the operating leakage current, and at the same time effectively provide a large number of carriers to compensate for the carrier capture effect at the interface of the insulating layer, thereby solving the technical problems of large leakage current and poor stability of the oxide bulk transistor.

In addition, an array substrate is provided in an embodiment of the present invention, and the array substrate includes the thin film transistor described in the above embodiments.

FIG. 8 shows an array substrate structure provided in an embodiment of the present invention, which includes a substrate 1, and a gate 2, a gate insulating layer 3, an active layer 4, and a source-drain electrode layer sequentially formed on the substrate 1. The source-drain electrode layer includes a source 5 and a drain 6 of a thin film transistor; a passivation layer 9 is formed above the gate insulating layer 3 and the source-drain electrode layer, and a pixel is also formed above the passivation layer 9 An electrode 10, the pixel electrode 10 is electrically connected to the drain 6 through a passivation layer via hole;

Wherein, the active layer 4 adopts a metal oxide semiconductor, and a metal layer 7 is provided between the active layer 4 and the gate insulating layer 3 to reduce the load between the active layer 4 and the gate insulating layer 3. Flow trapping effect.

The structure of the array substrate shown in FIG. 8 is only one form of the array substrate provided by the present invention; the protection scope of the present invention is not limited thereto. For example, the array substrate provided by the present invention may also be an array substrate based on an IPS (In-Plane Switching) or ADS (Advanced Super Dimensional Switching) pixel structure.

Furthermore, an embodiment of the present invention also provides a display device, which includes the above-mentioned array substrate.

The above display device may be a liquid crystal display device or other types of display devices. Wherein, the liquid crystal display device may be a liquid crystal panel, a liquid crystal TV, a mobile phone, a liquid crystal display, etc., which include a color filter substrate and the array substrate in the above-mentioned embodiments. The above other types of display devices, such as electronic paper, do not include the color filter substrate, but include the array substrate in the above embodiment.

Since both the array substrate and the display device provided in the embodiments of the present invention include the thin film transistors provided in the above embodiments, the array substrate and the display device in this embodiment also have the benefits brought by the above thin film transistors. Effect; that is, it can effectively reduce the generation of leakage current, reduce the threshold voltage, increase the on-state current, and reduce power consumption.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. A thin film transistor, comprising a grid formed on a substrate, a gate insulating layer, an active layer and a source-drain electrode layer, the source-drain electrode layer comprising a source electrode and a drain electrode of the thin film transistor; it is characterized in that , the active layer adopts a metal oxide semiconductor, and a metal layer is arranged between the active layer and the gate insulating layer to reduce the carrier trapping effect between the active layer and the gate insulating layer ; Wherein, a layer of metal oxide thin film is formed at the contact surface between the active layer and the metal layer. 2. The thin film transistor according to claim 1, wherein the active layer completely covers the metal layer. 3. The thin film transistor according to claim 1 or 2, wherein the metal layer is made of titanium metal. 4. The thin film transistor according to claim 3, wherein a titanium oxide thin film is formed between the metal layer and the active layer. 5. A method for manufacturing a thin film transistor, comprising the process of forming a gate, a gate insulating layer, an active layer, and a source-drain electrode layer on a substrate; wherein, the source-drain electrode layer includes the source electrode and the drain electrode of the thin film transistor pole; characterized in that, the active layer uses a metal oxide semiconductor; and, Between the step of forming the gate insulating layer and the step of forming the active layer, the method further includes: forming a metal layer between the gate insulating layer and the active layer; Wherein, a layer of metal oxide thin film is formed at the contact surface between the active layer and the metal layer. 6. The thin film transistor manufacturing method according to claim 5, characterized in that, The process of forming the metal layer between the gate insulating layer and the active layer includes: depositing a metal film on the gate insulating layer, and forming a metal layer between the gate insulating layer and the active layer through a patterning process. a metal layer between the active layers; The process of forming the active layer includes: depositing an oxide semiconductor thin film above the metal layer in an Ar/ _O2 atmosphere, and forming a pattern of the active layer through a patterning process; the active layer completely covers the metal layer. 7. The thin film transistor manufacturing method according to claim 5 or 6, characterized in that, after forming the active layer, the method further comprises: Under the Ar/O ₂ atmosphere, the active layer is annealed. 8. The thin film transistor manufacturing method according to claim 7, wherein the material of the metal layer is titanium metal; and, After the annealing treatment, the titanium metal layer at the contact surface of the active layer and the metal layer is partially oxidized to form a titanium oxide film. 9. An array substrate, comprising the thin film transistor according to any one of claims 1 to 4. 10. A display device comprising the array substrate according to claim 9.