CN102064109B - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

A method of manufacturing a thin film transistor, comprising: forming a grid electrode on a substrate; forming a gate insulating layer on the substrate to cover the gate electrode; forming an oxide semiconductor layer on the gate insulating layer; forming a semi-transparent layer on a partial region of the oxide semiconductor layer; using the semi-transparent layer as a mask, carrying out an optical annealing process to convert the oxide semiconductor layer into an oxide channel layer and two ohmic contact layers, wherein the oxide channel layer is positioned below the semi-transparent layer, and the ohmic contact layers are positioned at two sides of the oxide channel layer and are connected with the oxide channel layer; and forming a source electrode and a drain electrode which are electrically insulated with each other on the gate insulating layer and the ohmic contact layer. The thin film transistor has stable electrical characteristics, and the process of the invention is simpler, thereby being beneficial to the mass production of the thin film transistor.

Description

Thin film transistor and manufacturing method thereof

technical field

The invention relates to a thin film transistor and its manufacturing method, and in particular to a thin film transistor with an oxide channel layer and its manufacturing method.

Background technique

Recently, the awareness of environmental protection has risen, and flat display panels (flat display panels) with superior characteristics such as low power consumption, good space utilization efficiency, no radiation, and high image quality have become the mainstream of the market. Common flat panel displays include liquid crystal displays, plasma displays, and electroluminescent displays. Taking the currently most popular liquid crystal display as an example, it is mainly composed of a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer sandwiched between them. On known thin film transistor array substrates, amorphous silicon (a-Si) thin film transistors or low-temperature polysilicon thin film transistors are often used as switching elements for each sub-pixel. In recent years, studies have pointed out that oxide semiconductor thin film transistors have higher carrier mobility than amorphous silicon thin film transistors, and oxide semiconductor thin film transistors have higher mobility than low-temperature polysilicon thin film transistors. , it has better threshold voltage (threat hold voltage, Vth) uniformity. Therefore, oxide semiconductor thin film transistors have the potential to become key components of next-generation flat-panel displays.

1A to 1D are schematic cross-sectional views of the manufacturing process of a conventional oxide semiconductor thin film transistor. Please refer to FIG. 1A to FIG. 1D in sequence. First, a buffer layer 101 is formed on the substrate 100, and then a gate 102 is formed on a part of the buffer layer 101, and then a gate insulating layer 104 is formed on the substrate 100 to cover the gate. Pole 102, as shown in FIG. 1A. Next, an oxide semiconductor layer 106 is formed on the gate insulating layer 104 , as shown in FIG. 1B . Then, using the photomask M as a mask, an excimer laser annealing (exaimer laser annealing) process is performed, so that the part of the oxide semiconductor layer 106 not covered by the photomask M is converted into two ohmic contact layers 106b, and The portion of the oxide semiconductor layer 106 that is shielded by the photomask M maintains the characteristics of the semiconductor to form the oxide channel layer 106a. The ohmic contact layer 106b is located on both sides of the oxide channel layer 106a and connected to the oxide channel layer 106a, as shown in FIG. 1B and FIG. 1C. Finally, a source S and a drain D electrically insulated from each other are respectively formed on the gate insulating layer 104 and the ohmic contact layer 106b. In this way, the fabrication of known oxide semiconductor thin film transistors is completed.

However, the electrical characteristics (the relationship between the drain current and the gate voltage) of the oxide semiconductor thin film transistor fabricated by the above process are relatively unstable. Therefore, in the known technology, in order to maintain the electrical characteristics of the above-mentioned oxide semiconductor thin film transistor, the oxide channel layer 106a is usually annealed after the above-mentioned process is completed, such as a high-temperature annealing process (thermal annealing) or quasi- Molecular laser annealing (excimer laser annealing) process to stabilize the electrical characteristics of the oxide semiconductor thin film transistor. However, this process will make the process of the known oxide semiconductor thin film transistor more complicated. Based on the above, how to improve the electrical characteristics of the oxide semiconductor thin film transistor without increasing the complexity of the process is actually one of the issues that developers are concerned about.

Contents of the invention

The purpose of the present invention is to overcome the disadvantages of the prior art.

The present invention provides a thin film transistor having stable electrical characteristics.

The invention provides a method for manufacturing a thin film transistor, which is helpful for the mass production of the thin film transistor.

The invention provides a manufacturing method of a thin film transistor, which includes: forming a gate on a substrate. Next, a gate insulating layer is formed on the substrate to cover the gate. Then, an oxide semiconductor layer is formed on the gate insulating layer. Afterwards, a semi-transparent layer is formed on a partial region of the oxide semiconductor layer. Then, using the semi-transparent layer as a mask, an optical annealing process is performed to convert the oxide semiconductor layer into an oxide channel layer and two ohmic contact layers, wherein the oxide channel layer is located under the semi-transparent layer, and The ohmic contact layer is located on both sides of the oxide channel layer and connected with the oxide channel layer. Finally, a source electrode and a drain electrode electrically insulated from each other are formed on the gate insulating layer and the ohmic contact layer.

The invention provides a manufacturing method of a thin film transistor, which includes: forming a gate on a substrate. Next, a gate insulating layer is formed on the substrate to cover the gate. Then, a source and a drain electrically insulated from each other are formed on the gate insulating layer. Afterwards, an oxide semiconductor layer is formed on the gate insulating layer, the source and the drain. Next, a semi-transparent layer is formed on a partial region of the oxide semiconductor layer. Finally, using the semi-transparent layer as a mask, an optical annealing process is performed to convert the oxide semiconductor layer into an oxide channel layer and two ohmic contact layers, wherein the oxide channel layer is located under the semi-transparent layer, And the ohmic contact layer is located on both sides of the oxide channel layer and connected with the oxide channel layer.

The invention provides a thin film transistor, which includes a gate, a gate insulating layer, an oxide semiconductor layer, a semitransparent layer, a source and a drain. A gate insulating layer covers the gate. The oxide semiconductor layer is disposed on the gate insulating layer and located above the gate. The oxide semiconductor layer includes an oxide channel layer and two ohmic contact layers, wherein the ohmic contact layers are located on both sides of the oxide channel layer and connected to the oxide channel layer. The semi-transmissive layer is located above the oxide channel layer. The source and the drain are located on the gate insulating layer and the ohmic contact layer, and the source and the drain are electrically insulated from each other.

The invention provides a thin film transistor, which includes a gate, a gate insulating layer, a source, a drain, an oxide semiconductor layer and a semitransparent layer. A gate insulating layer covers the gate. The source and the drain are disposed on the gate insulating layer and electrically insulated from each other. The oxide semiconductor layer is disposed on the gate insulating layer, the source and the drain. The oxide semiconductor layer includes an oxide channel layer and two ohmic contact layers, wherein the ohmic contact layers are located on both sides of the oxide channel layer and connected to the oxide channel layer. The semi-transmissive layer is located above the oxide channel layer.

In an embodiment of the present invention, the material of the aforementioned oxide semiconductor layer includes indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide (IGO), tin oxide (ZnO), cadmium oxide. Germanium (2CdO·GeO ₂ ) or nickel cobalt oxide (NiCo ₂ O ₄ ).

In an embodiment of the present invention, the material of the aforementioned semi-transparent layer includes silicon oxide (SiOx), silicon nitride (SiNx), titanium oxide (TiOx), indium trioxide (In2O3), InGaO3, InGaZnO, SnO2 , ZnO, Zn2In2O5, silver (Ag), ZnSnO3, Zn2SnO4 or amorphous silicon (a-Si).

In an embodiment of the present invention, the aforementioned optical annealing process utilizes laser light to irradiate the semi-transparent layer and the oxide semiconductor layer.

In an embodiment of the present invention, in the aforementioned optical annealing process, after the laser passes through the semi-transparent layer, the energy of the laser is attenuated between 10% and 90%.

In an embodiment of the present invention, the aforementioned semi-transparent layer includes a semi-transparent shielding layer or a semi-transparent absorbing layer.

In an embodiment of the present invention, the sheet resistance of the aforementioned ohmic contact layer is Rs1 (Ω/□), and the sheet resistance of the oxide channel layer is Rs2 (Ω/□), and Rs2/Rs1 is about 10 ⁸ .

In an embodiment of the present invention, the sheet resistance Rs1 of the aforementioned ohmic contact layer is about 10 ⁴ Ω/□, and the sheet resistance Rs2 of the oxide channel layer is about 10 ¹² Ω/□.

In an embodiment of the present invention, in the aforementioned manufacturing method of the thin film transistor, before forming the semi-transparent layer, it further includes forming a dielectric layer between the semi-transparent layer and the oxide semiconductor layer.

The thin film transistor of the invention has stable electrical characteristics, and the process of the invention is relatively simple, which is beneficial to mass production of the thin film transistor.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A to FIG. 1D are cross-sectional schematic diagrams of a known manufacturing process of an oxide semiconductor thin film transistor.

2A to 2E are schematic cross-sectional views of the manufacturing process of the thin film transistor according to the first embodiment of the present invention.

2F to 2H are schematic cross-sectional views of a part of the manufacturing process of the thin film transistor according to the first embodiment of the present invention.

2E and 2H are schematic cross-sectional views of the thin film transistor according to the first embodiment of the present invention.

FIG. 2I is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.

3A to 3E are schematic cross-sectional views of the manufacturing process of the thin film transistor according to the second embodiment of the present invention.

3G to 3H are schematic cross-sectional views of a part of the manufacturing process of the thin film transistor according to the second embodiment of the present invention.

3E and 3H are schematic cross-sectional views of a thin film transistor according to a second embodiment of the present invention.

FIG. 3F is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100, 200: Substrate

101: buffer layer

102, 202: grid

104, 204: gate insulating layer

106, 206: oxide semiconductor layer

106a, 206a: oxide channel layer

106b, 206b: ohmic contact layer

207: Dielectric layer

208: semi-transparent layer

S, S': source

D, D': Drain

M: mask

L: Laser

TFT: thin film transistor

Detailed ways

【The first embodiment】

2A to 2E are schematic cross-sectional views of the manufacturing process of the thin film transistor of this embodiment. First, referring to FIG. 2A , a gate 202 is formed on a substrate 200 . Next, a gate insulating layer 204 is formed entirely on the substrate 200 to cover the gate 202 . In this embodiment, the material of the substrate 200 is, for example, glass, quartz, organic polymer, opaque/reflective material (such as conductive material, wafer, ceramic, etc.) or other suitable materials.

In this embodiment, the material of the gate 202 is generally a metal material. However, the present invention is not limited thereto. In other embodiments, the material of the gate 202 can also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or metals. Stacked layers of materials and other conductive materials. In addition, the material of the gate insulating layer 204 in this embodiment is, for example, an inorganic dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic dielectric material, or the above-mentioned organic and inorganic materials. combinations of dielectric materials, but the invention is not limited thereto.

Next, referring to FIG. 2B , an oxide semiconductor layer 206 is formed on a partial region on the gate insulating layer 204 . In this embodiment, the material of the oxide semiconductor layer 206 is, for example, amorphous silicon indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide (IGO), tin oxide (ZnO), cadmium oxide, Germanium oxide (2CdO·GeO ₂ ), nickel cobalt oxide (NiCo ₂ O ₄ ), or other suitable materials.

Next, referring to FIG. 2C , a semi-transparent layer 208 is formed on a partial region of the oxide semiconductor layer 206 . In this embodiment, the semi-transparent layer is, for example, a semi-transparent shielding layer to shield part of the incident light. However, the present invention is not limited thereto. In other embodiments, the semi-transparent layer can also be a semi-transparent absorbing layer to absorb part of the incident light. In this embodiment, the material of the semi-transparent layer 208 is, for example, silicon oxide (SiOx), silicon nitride (SiNx), titanium oxide (TiOx), indium trioxide (In2O3), InGaO3, InGaZnO, SnO2, ZnO, Zn2In2O5, silver (Ag), ZnSnO3, Zn2SnO4 or amorphous silicon (a-Si), but the present invention is not limited thereto.

Next, please refer to FIG. 2C and FIG. 2D , using the above-mentioned semi-transparent layer 208 as a mask, perform an optical annealing process to convert the oxide semiconductor layer 206 into an oxide channel layer 206a and two ohmic contact layers 206b, as shown in FIG. 2C and Figure 2D. In more detail, the optical annealing process of this embodiment is, for example, using laser light L to irradiate the semi-transparent layer 208 and the oxide semiconductor layer 206, wherein the part of the oxide semiconductor layer 206 that is not shielded by the semi-transparent layer 208 can receive The energy of the laser light L is relatively large (approximately equal to the energy of the original incident laser light L), while the oxide semiconductor layer 206 shielded by the semi-transparent layer 208 can receive relatively small energy of the laser light L. For example, the oxide semiconductor layer 206 shielded by the semi-transparent layer 208 can receive the energy of the laser L between 10% and 90% of the energy of the original incident laser L.

In this embodiment, the part of the oxide semiconductor layer 206 that receives the laser light L with higher energy can be transformed into an ohmic contact layer 206b with a lower resistance, while the part of the oxide semiconductor layer 206 that is irradiated with the laser L with lower energy It is an oxide channel layer 206a with stable electrical characteristics, as shown in FIG. 2D . Furthermore, if the sheet resistance of the ohmic contact layer 206b in this embodiment is Rs1 (Ω/□), and the sheet resistance of the oxide channel layer 206a is Rs2 (Ω/□), then the oxide channel layer 206a The ratio (Rs2/Rs1) of the sheet resistance Rs2 of the ohmic contact layer 206b to the sheet resistance Rs1 (Ω/□) of the ohmic contact layer 206b is about 10 ⁸ . More specifically, in this embodiment, the sheet resistance Rs1 of the ohmic contact layer 206 b is, for example, about 10 ⁴ Ω/□, and the sheet resistance Rs2 of the oxide channel layer 206 a is, for example, about 10 ¹² Ω/□.

It is worth noting that, in this embodiment, the semi-transparent layer 208 on the oxide semiconductor layer 206 can be partially used to make the oxide semiconductor layer 206 shielded by the semi-transparent layer 208 and the part not shielded by the semi-transparent layer 208 The oxide semiconductor layer 206 can receive laser light L with different energies at the same time. Therefore, in this embodiment, the oxide channel layer 206 a with good electrical characteristics and the ohmic contact layer 206 b with low resistance can be formed simultaneously. In addition, the thickness or composition of the semi-transparent layer 208 in this embodiment can be properly adjusted to change its ability to attenuate the energy of the laser L, so that the electrical characteristics of the oxide channel layer 206a can be optimized (optimized) .

Next, referring to FIG. 2E , a source S' and a drain D' are electrically insulated from each other on part of the gate insulating layer 204 and the ohmic contact layer 206b, respectively. In this embodiment, the source S' and the drain D' electrically insulated from each other can respectively form a good ohmic contact through the ohmic contact layer 206b and the oxide channel layer 206a located thereunder. In this embodiment, the material of the source S' and the drain D' is generally a metal material. However, the present invention is not limited thereto. In other embodiments, the materials of the source S' and the drain D' can also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, and metal materials. Oxynitride or stacked layers of metal materials and other conductive materials.

After the fabrication of the source S' and the drain D' is completed, the fabrication of the thin film transistor TFT of this embodiment is preliminarily completed.

It can be clearly seen from FIG. 2E that the thin film transistor TFT of this embodiment includes a gate 202, a gate insulating layer 204, an oxide semiconductor layer 206, a semi-transparent layer 208, a source S' and a drain D'. The gate insulating layer 204 covers the gate 202 . The oxide semiconductor layer 206 includes an oxide channel layer 206a and two ohmic contact layers 206b, wherein the ohmic contact layers 206b are located on both sides of the oxide channel layer 206a and connected to the oxide channel layer 206a. The oxide semiconductor layer 206 is disposed on the gate insulating layer 204 and the oxide channel layer 206 a is located above the gate 202 . The semi-transparent layer 208 is located above the oxide channel layer 206a. The source S' and the drain D' are located on the gate insulating layer 204 and the ohmic contact layer 206b, and the source S' and the drain D' are electrically insulated from each other.

In addition, in this embodiment, a dielectric layer 207 may be formed between the semi-transmissive layer 208 and the oxide semiconductor layer 206 before forming the semi-transmissive layer 208 , as shown in FIG. 2F . In this embodiment, the material of the dielectric layer 207 can be a transparent dielectric material, such as silicon oxide (SiOx), but the invention is not limited thereto.

Next, an optical annealing process is performed using the semi-transparent layer 208 as a mask to transform the oxide semiconductor layer 206 into an oxide channel layer 206a and two ohmic contact layers 206b, as shown in FIG. 2F and FIG. 2G .

Next, please refer to FIG. 2H , in this embodiment, a source S' and a drain D' electrically insulated from each other can also be formed on the ohmic contact layer 206b on a portion of the gate insulating layer 204, respectively. Of course, in other embodiments, the semi-transparent layer 208 may also be selectively removed after the source S' and the drain D' are fabricated, so as to form the thin film transistor TFT as shown in FIG. 2I .

It can be clearly seen from FIG. 2H that the thin film transistor TFT of this embodiment may also include a gate 202, a gate insulating layer 204, an oxide semiconductor layer 206, a dielectric layer 207, a semi-transparent layer 208, a source S' and a drain. Pole D'. The gate insulating layer 204 covers the gate 202 . The oxide semiconductor layer 206 includes an oxide channel layer 206a and two ohmic contact layers 206b, wherein the ohmic contact layers 206b are located on both sides of the oxide channel layer 206a and connected to the oxide channel layer 206a. The oxide semiconductor layer 206 is disposed on the gate insulating layer 204 and the oxide channel layer 206 a is located above the gate 202 . The dielectric layer 207 is located on the oxide channel layer 206 a, and the semi-transparent layer 208 is located on the oxide channel layer 206 a and the dielectric layer 207 . In addition, the source S' and the drain D' are located on part of the ohmic contact layer 206b on the gate insulating layer 204 and connected to the dielectric layer 207, and the source S' and the drain D' are electrically insulated from each other.

【Second Embodiment】

3A to 3E are schematic cross-sectional views of the manufacturing process of the thin film transistor of this embodiment. The materials that can be used for the various components of the thin film transistor of this embodiment are the same as those of the first embodiment, and will not be repeated below.

First, please refer to FIG. 3A , a gate 202 is formed on the substrate 200 . Next, a gate insulating layer 204 is formed entirely on the substrate 200 to cover the gate 202 .

Next, please refer to FIG. 3B , a source S' and a drain D' electrically insulated from each other are formed on a part of the gate insulating layer 204. Referring to FIG.

Next, referring to FIG. 3C , an oxide semiconductor layer 206 is formed on the gate insulating layer 204, the source S' and the drain D'. In other words, the oxide semiconductor layer 206 of this embodiment covers part of the gate insulating layer 204 above the gate 202, part of the source S' and part of the drain D'.

Next, referring to FIG. 3D , a semi-transparent layer 208 is formed on a partial region of the oxide semiconductor layer 206 .

Next, please refer to FIG. 3D and FIG. 3E , using the above-mentioned semi-transparent layer 208 as a mask, perform an optical annealing process to convert the oxide semiconductor layer 206 into an oxide channel layer 206a and two ohmic contact layers 206b, as shown in FIG. 3D and Figure 3E. More specifically, the optical annealing process of this embodiment is, for example, using laser light L to irradiate the semi-transparent layer 208 and the oxide semiconductor layer 206 . Among them, the part of the oxide semiconductor layer 206 that is not shielded by the non-translucent layer 208 has a larger energy of the laser L that can be received (approximately equal to the energy of the original incident laser L), while the part of the oxide semiconductor layer that is shielded by the semi-transparent layer 208 Layer 206, which can receive less energy of the laser light L. For example, the oxide semiconductor layer 206 shielded by the semi-transparent layer 208 can receive the energy of the laser L between 10% and 90% of the energy of the original incident laser L.

In this embodiment, the part of the oxide semiconductor layer 206 that receives the laser light L with higher energy can be transformed into an ohmic contact layer 206b with a lower resistance, while the part of the oxide semiconductor layer 206 that receives the laser L with lower energy is An oxide channel layer 206a with stable electrical properties is shown in FIG. 3E. Furthermore, if the sheet resistance of the ohmic contact layer 206b in this embodiment is Rs1 (Ω/□), and the sheet resistance of the oxide channel layer 206a is Rs2 (Ω/□), then the oxide channel layer 206a The ratio (Rs2/Rs1) of the sheet resistance Rs2 of the ohmic contact layer 206b to the sheet resistance Rs1 (Ω/□) of the ohmic contact layer 206b is about 10 ⁸ . More specifically, in this embodiment, the sheet resistance Rs1 of the ohmic contact layer 206 b is, for example, about 10 ⁴ Ω/□, and the sheet resistance Rs2 of the oxide channel layer 206 a is, for example, about 10 ¹² Ω/□.

It is worth noting that, in this embodiment, the semi-transparent layer 208 on the oxide semiconductor layer 206 can also be used to make the oxide semiconductor layer 206 shielded by the semi-transparent layer 208 and the part not covered by the semi-transparent layer 208 The shielded oxide semiconductor layer 206 can simultaneously receive laser light L with different energies. Therefore, in this embodiment, the oxide channel layer 206 a with good electrical characteristics and the ohmic contact layer 206 b with low resistance can be formed simultaneously. In addition, the thickness or composition of the semi-transparent layer 208 in this embodiment can also be properly adjusted to change its ability to attenuate the energy of the laser L, so that the electrical characteristics of the oxide channel layer 206a can be optimized. ).

After the oxide channel layer 206 a and the ohmic contact layer 206 b are fabricated, the fabrication of the thin film transistor TFT of this embodiment is preliminarily completed. Of course, in other embodiments, the photoresist layer 208 may also be selectively removed after the oxide channel layer 206 a and the ohmic contact layer 206 b are fabricated, so as to form the thin film transistor TFT as shown in FIG. 3F .

It can be clearly seen from FIG. 3E that the thin film transistor TFT of this embodiment may include a gate 202 , a gate insulating layer 204 , an oxide semiconductor layer 206 , a semi-transparent layer 208 , a source S and a drain D. As shown in FIG. The gate insulating layer 204 covers the gate 202 . The source S' and the drain D' are disposed on a portion of the gate insulating layer 204 and are electrically insulated from each other. The oxide semiconductor layer 206 is disposed on the gate insulating layer 204, the source S' and the drain D'. The oxide semiconductor layer 206 includes an oxide channel layer 206a and two ohmic contact layers 206b. Wherein, the ohmic contact layer 206b is located on both sides of the oxide channel layer 206a and connected to the oxide channel layer 206 . Moreover, the two ohmic contact layers 206b are respectively connected to the source S' and the drain D'. The semi-transparent layer 208 is located above the oxide channel layer 206 .

In addition, in this embodiment, a dielectric layer 207 may be formed between the semi-transmissive layer 208 and the oxide semiconductor layer 206 before forming the semi-transmissive layer 208 , as shown in FIG. 3G . Next, the oxide semiconductor layer 206 can also be transformed into an oxide channel layer 206a and two ohmic contact layers 206b by performing an optical annealing process through the dielectric layer 207 using the above-mentioned semi-transparent layer 208 as a mask, as shown in the figure 3G and Figure 3H.

It can be clearly seen from FIG. 3H that the thin film transistor TFT of this embodiment may also include a gate 202, a gate insulating layer 204, an oxide semiconductor layer 206, a dielectric layer 207, a semi-transparent layer 208, a source S' and a drain. Pole D'. The gate insulating layer 204 covers the gate 202 . The source S' and the drain D' are disposed on the gate insulating layer 204 and electrically insulated from each other. The oxide semiconductor layer 206 is disposed on the gate insulating layer 204, the source S' and the drain D'. The oxide semiconductor layer 206 includes an oxide channel layer 206a and two ohmic contact layers 206b. Wherein, the ohmic contact layer 206b is located on both sides of the oxide channel layer 206a and connected to the oxide channel layer 206 . Moreover, the two ohmic contact layers 206b are respectively connected to the source S' and the drain D'. The dielectric layer 207 is located on the oxide channel layer 206a, the ohmic contact layer 206b, the source S', the drain D' and part of the gate insulating layer 204. The semi-transparent layer 208 is located above the dielectric layer 207 and part of the oxide channel layer 206a.

In summary, the present invention can simultaneously form an oxide channel layer with good electrical characteristics and an ohmic contact layer with low resistance through the semi-transparent layer. Therefore, the electrical characteristics and mass productivity of the thin film transistor of the present invention can be balanced.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be determined by the scope of protection defined by the appended claims.

Claims (16)

1. A method for manufacturing a thin film transistor, comprising: forming a gate on a substrate; forming a gate insulating layer on the substrate to cover the gate; forming an oxide semiconductor layer on the gate insulating layer; forming a semi-transparent layer on a part of the oxide semiconductor layer; Using the semi-transparent layer as a mask, perform an optical annealing process to convert the oxide semiconductor layer into an oxide channel layer and two ohmic contact layers, wherein the oxide channel layer is located in the semi-transparent layer below, and the two ohmic contact layers are located on both sides of the oxide channel layer and connected to the oxide channel layer; and A source and a drain electrically insulated from each other are formed on the gate insulating layer and the two ohmic contact layers, The optical annealing process uses a laser to irradiate the semi-transparent layer and the oxide semiconductor layer, and after the laser passes through the semi-transparent layer, the energy of the laser is attenuated between 10% and 90%. the 2. The manufacturing method of a thin film transistor as claimed in claim 1, wherein the material of the oxide semiconductor layer comprises indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide (IGO), tin oxide (ZnO ), cadmium oxide germanium oxide (2CdO GeO ₂ ) or nickel cobalt oxide (NiCo ₂ O ₄ ). 3. The manufacturing method of a thin film transistor as claimed in claim 1, wherein the material of the semi-transparent layer comprises silicon oxide (SiOx), silicon nitride (SiNx), titanium oxide (TiOx), indium trioxide ( _In2 O ₃ ), InGaO ₃ , InGaZnO, SnO ₂ , ZnO, Zn ₂ In ₂ O ₅ , silver (Ag), ZnSnO ₃ , Zn ₂ SnO ₄ , or amorphous silicon (a-Si). 4. The manufacturing method of the thin film transistor according to claim 1, wherein the semi-transparent layer comprises a semi-transparent shielding layer or a semi-transparent absorbing layer. the 5 . The method for manufacturing a thin film transistor according to claim 1 , wherein the sheet resistance of the two ohmic contact layers is Rs1, and the sheet resistance of the oxide channel layer is Rs2, and Rs2/Rs1 is 10 ⁸ . 6. The method for manufacturing a thin film transistor according to claim 5, wherein Rs1 is 10 ⁴ Ω/□, and Rs2 is 10 ¹² Ω/□. 7 . The method for manufacturing a thin film transistor according to claim 1 , further comprising forming a dielectric layer between the semi-transmissive layer and the oxide semiconductor layer before forming the semi-transmissive layer. the 8. A method for manufacturing a thin film transistor, comprising: forming a gate on a substrate; forming a gate insulating layer on the substrate to cover the gate; forming a source and a drain electrically insulated from each other on the gate insulating layer; forming an oxide semiconductor layer on the gate insulating layer, the source and the drain; forming a semi-transparent layer on a partial region of the oxide semiconductor layer; and Using the semi-transparent layer as a mask, perform an optical annealing process to convert the oxide semiconductor layer into an oxide channel layer and two ohmic contact layers, wherein the oxide channel layer is located on the semi-transparent layer below, and the two ohmic contact layers are located on both sides of the oxide channel layer and connected to the oxide channel layer, Wherein the optical annealing process uses a laser to irradiate the semi-transparent layer and the oxide semiconductor layer, and after the laser passes through the semi-transparent layer, the energy of the laser is attenuated between 10% and 90%. the 9. The manufacturing method of a thin film transistor as claimed in claim 8, wherein the material of the oxide semiconductor layer comprises indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide (IGO), tin oxide (ZnO ), cadmium oxide germanium oxide (2CdO GeO ₂ ) or nickel cobalt oxide (NiCo ₂ O ₄ ). 10. The manufacturing method of a thin film transistor as claimed in claim 8, wherein the material of the semi-transparent layer comprises silicon oxide (SiOx), silicon nitride (SiNx), titanium oxide (TiOx), indium trioxide ( _In2 O ₃ ), InGaO ₃ , InGaZnO, SnO ₂ , ZnO, Zn ₂ In ₂ O ₅ , silver (Ag), ZnSnO ₃ , Zn ₂ SnO ₄ , or amorphous silicon (a-Si). 11. The manufacturing method of the thin film transistor according to claim 8, wherein the semi-transparent layer comprises a semi-transparent shielding layer or a semi-transparent absorbing layer. the 12 . The method for manufacturing a thin film transistor according to claim 8 , wherein the sheet resistance of the two ohmic contact layers is Rs1, and the sheet resistance of the oxide channel layer is Rs2, and Rs2/Rs1 is 10 ⁸ . 13. The method for manufacturing a thin film transistor according to claim 12, wherein Rs1 is 10 ⁴ Ω/□, and Rs2 is 10 ¹² Ω/□. 14. The method for manufacturing a thin film transistor according to claim 8, further comprising forming a dielectric layer between the semi-transparent layer and the oxide semiconductor layer before forming the semi-transparent layer. the 15. A thin film transistor comprising: a gate; a gate insulating layer covering the gate; An oxide semiconductor layer, configured on the gate insulating layer and located above the gate, the oxide semiconductor layer includes an oxide channel layer and two ohmic contact layers, the two ohmic contact layers are located on the oxide On both sides of the channel layer and connected to the oxide channel layer; a semi-transmissive layer overlying the oxide channel layer; and A source and a drain are located on the gate insulating layer and the two ohmic contact layers, and the source and the drain are electrically insulated from each other, Wherein, after the laser light used for annealing the oxide semiconductor layer passes through the semi-transparent layer, the energy of the laser light is attenuated between 10% and 90%. the 16. A thin film transistor comprising: a gate; a gate insulating layer covering the gate; A source and a drain are disposed on the gate insulating layer and are electrically insulated from each other; An oxide semiconductor layer is disposed on the gate insulating layer, the source and the drain, the oxide semiconductor layer includes an oxide channel layer and two ohmic contact layers, and the two ohmic contact layers are located on the on both sides of and connected to the oxide channel layer; and a semi-transparent layer located above the oxide channel layer, Wherein, after the laser light used for annealing the oxide semiconductor layer passes through the semi-transparent layer, the energy of the laser light is attenuated between 10% and 90%. the

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