CN102685003B - Data switching device and read-back method - Google Patents
Data switching device and read-back method Download PDFInfo
- Publication number
- CN102685003B CN102685003B CN201210126755.7A CN201210126755A CN102685003B CN 102685003 B CN102685003 B CN 102685003B CN 201210126755 A CN201210126755 A CN 201210126755A CN 102685003 B CN102685003 B CN 102685003B
- Authority
- CN
- China
- Prior art keywords
- read
- cpu
- exchange
- list item
- buffer memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000011159 matrix material Substances 0.000 claims description 3
- 239000003550 marker Substances 0.000 abstract 1
- 230000007246 mechanism Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
- Debugging And Monitoring (AREA)
Abstract
The embodiment of the invention discloses a data switching device and a read-back method, wherein the data switching device comprises an RAM (Random Access Memory), a gate circuit, a CPU (Central Processing Unit), a logic circuit, a cache and a cache marker register. At first, the CPU configures the cache in advance so as to define a read-back table item that needs to be read from an exchange matching table saved in the RAM; when contents that are read from the exchange matching table by the logic circuit covers the read-back table item, the corresponding table item read from the exchange matching table is saved in the cache; and/or when information that is read from the exchange matching table by the logic circuit does not cover the read-back table item, the CPU sends a read-back request to the RAM so as to obtain the table item needing to be read from the exchange matching table and save the table item in the cache; and finally, the CPU queries the read-back table item in the cache, so as to perform debugging and locating. The data switching device and the read-back method are suitable for the field of a communication system.
Description
Technical field
The present invention relates to field of wireless communications, particularly a kind of switch and read-back approach.
Background technology
Often adopt crossbar switching matrix crossbar structure in switch, the exchanges data between any passage can be realized.In crossbar structure, between any passage, there is node, represent that any passage can carry out exchanges data.Crossbar needs an exchange to join table, is used for storing the exchange message of each data in each passage.Owing to will realize the exchange between any passage, square multiple exchanging the scale and number of channels of joining table is directly proportional.
At device interior, the exchange of crossbar is joined table content and is write by CPU, and requires can rewrite at any time to join table.Logical circuit can be accessed exchange and be joined table in the equipment course of work, carries out exchanges data according to joining the information stored in table.Logic is very high to exchanging the reading requirement of real-time of joining table, and access is very frequent.Exchange in addition join that table also wants can by CPU retaking of a year or grade, debug and online orientation problem time, CPU retaking of a year or grade exchange configuration is an important means, but in equipment working state at ordinary times, CPU can not frequently read exchange and join table, and the requirement of real-time that table is joined in CPU reading is not high, but can not lose operation.The memory bank that the usual random access memory ram by four port dual-ports in return joins table at present realizes the operations such as CPU read and write, but using dual-ports RAM to realize the operations such as CPU read and write can cause the problem that switching equipment area and power consumption are all very large.
Summary of the invention
The embodiment of the present invention provides a kind of switch and read-back approach, solves use two and reads two and write RAM when realizing the operation such as CPU read and write, the problem that switching equipment area and power consumption are all very large.
The technical scheme that the embodiment of the present invention adopts is:
A kind of switch, comprising: random access memory ram, gate circuit, central processor CPU, logical circuit, buffer memory;
Described RAM is used for memory transactions and joins table, described RAM comprises read port and write port, described CPU is used for being joined in table to described exchange by the write port of described RAM writing exchange message, and described exchange message is the information of carrying out exchanges data in described switch between each passage;
Described gate circuit comprises: output, first input end and the second input, and described output is connected with the read port of described RAM;
Described logical circuit sends logic read request by described second input to described RAM, and carries out exchanges data according to the content of joining table reading from described exchange;
Described buffer memory, for when described logical circuit joins the content covering retaking of a year or grade list item of table reading from described exchange, by corresponding from described exchange join table read list item be stored into described buffer memory, and/or when described logical circuit from described exchange join table read information do not cover described retaking of a year or grade list item time, described CPU is sent it back the list item of read request also needed for acquisition by the described first input end of described gate circuit to described RAM, be stored in described buffer memory, wherein, the list item showing to read joined by the needs that described retaking of a year or grade list item is defined by pre-configured described buffer memory for described CPU from described exchange,
Described CPU also for inquiring about the described retaking of a year or grade list item stored in described buffer memory, with realize debugging and location.
A method for CPU retaking of a year or grade, comprising:
The pre-configured buffer memory of CPU needs the exchange stored from RAM to join the retaking of a year or grade list item read table to define;
When described logical circuit joins the content covering retaking of a year or grade list item of table reading from described exchange, by corresponding from described exchange join table read list item be stored into described buffer memory, and/or when described logical circuit from described exchange join table read information do not cover described retaking of a year or grade list item time, described CPU sends it back read request to described RAM, to join the list item of acquisition needs reading in table from described exchange and to be stored in described buffer memory;
Described CPU inquires about the described retaking of a year or grade list item in described buffer memory, to carry out debugging and locating.
The switch that the embodiment of the present invention provides and read-back approach comprise: random access memory ram, gate circuit, central processor CPU, logical circuit, buffer memory.First the pre-configured buffer memory of CPU needs the exchange stored from RAM to join the retaking of a year or grade list item read table to define, when described logical circuit joins the content covering retaking of a year or grade list item of table reading from described exchange, by corresponding from described exchange join table read list item be stored into described buffer memory, and/or when described logical circuit from described exchange join table read information do not cover described retaking of a year or grade list item time, described CPU sends it back read request to described RAM, to join the list item of acquisition needs reading in table from described exchange and to be stored in described buffer memory, last described CPU inquires about the described retaking of a year or grade list item in described buffer memory, to carry out debugging and locating.The memory bank that prior art in return joins table by four port dual-ports random access memory rams usually realizes the operations such as CPU read and write, but using dual-portsRAM to realize the operations such as CPU read and write can cause the problem that switching equipment area and power consumption are all very large.And the embodiment of the present invention joins table by adopting dual-port two-ports RAM memory transactions, and the result of multiplexing logical read operation is as the result of CPU read operation, thus decreases the area of switching equipment and reduce the power consumption of switching equipment.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The switch structural representation that Fig. 1 provides for the embodiment of the present invention;
The method flow diagram of the CPU retaking of a year or grade that Fig. 2 provides for the embodiment of the present invention;
Fig. 3 is the RAM structural representation that memory transactions joins table;
Fig. 4 is polling mechanism periodic table.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
For making the advantage of technical solution of the present invention clearly, below in conjunction with drawings and Examples, the present invention is elaborated.
The embodiment of the present invention provides a kind of switch, as shown in Figure 1, the entity of described device can be exchanges data chip, and described device comprises: random access memory ram 11, gate circuit 12, central processor CPU 13, logical circuit 14, buffer memory 15, cache tag register 16.
Described RAM11 is used for memory transactions and joins table, described RAM11 comprises read port 31 and write port 32, described CPU13 is used for being joined in table to described exchange by the write port 32 of described RAM11 writing exchange message, described exchange message is the information of carrying out exchanges data in described switch between each passage, and described read port 31 comprises: read enable signal subport, read address subport and read data subport.Described write port 32 comprises: write enable signal subport, write address subport and write data subport.
Wherein, when described switch is crossbar switching matrix crossbar framework, the exchange message that table stores each data in each passage in the switch of described crossbar structure is joined in described exchange.Described RAM can be dual-port two-ports type RAM.
Described gate circuit 12 comprises: output, first input end and the second input, described output and described RAM11 read enable signal subport and described address subport of reading is connected.
Wherein, described gate circuit 12 can be OR circuit.
Described logical circuit 14 is connected with the read data subport of described RAM11, and described logical circuit 14 sends logic read request by described second input to described RAM11, and carries out exchanges data according to the content of joining table reading from described exchange.
Described buffer memory 15, for when described logical circuit 14 joins the content covering retaking of a year or grade list item of table reading from described exchange, by corresponding from described exchange join table read list item be stored into described buffer memory 15, and/or when described logical circuit 14 from described exchange join table read information do not cover described retaking of a year or grade list item time, described CPU13 is sent it back the list item of read request also needed for acquisition by the described first input end of described gate circuit 12 to described RAM11, be stored in described buffer memory 15, wherein, the list item showing to read joined by the needs that described retaking of a year or grade list item is defined by pre-configured described buffer memory for described CPU13 from described exchange.
Described CPU13 also for inquiring about the described retaking of a year or grade list item stored in described buffer memory, with realize debugging and location.
Described cache tag register 16 is connected with described CPU13 and described buffer memory 15.
Whether described cache tag register 16 is for identifying described retaking of a year or grade list item stored in described buffer memory, so that when CPU13 judges to there is significant bit in described cache tag register 16, from described buffer memory 15, obtain the retaking of a year or grade list item corresponding with described significant bit.
Wherein, each bit in cache tag register 16 represents that whether the retaking of a year or grade list item of correspondence is stored in buffer memory respectively.CPU13 can obtain the value of this cache tag register 16 by inquiry mode, if cache tag register 16 corresponding bit is effective, show that the retaking of a year or grade list item needed for CPU13 retaking of a year or grade is ready.The heap(ed) capacity of buffer memory 15 can adjust according to the actual flow of CPU13 retaking of a year or grade, but does not join the expansion of table scale with exchange and expand.
The switch that the embodiment of the present invention provides, when being obtained exchange by read operation and joining table, can adopt polling mechanism.Such as, exchange and join table one and have 64 exchange table entries, then set polling cycle as 64, as shown in Figure 3, because logic is read very frequent, if cover the retaking of a year or grade list item that CPU needs to read, now can directly the result read of multiplexing logical as CPU reading back result.If the content read by logical circuit does not read the retaking of a year or grade list item covering the reading of CPU needs, the retaking of a year or grade list item required for CPU read operation acquisition can be inserted.Assuming that the exchange table entries 0 ~ 18 that logic needs reading to exchange joins in table and exchange table entries 22 ~ 63, CPU need retaking of a year or grade exchange table entries 0 ~ 4 and exchange table entries 19 ~ 21.Then the poll moment 0 ~ 18,22 ~ 63 is distributed to logic to read, the poll moment 19 ~ 21 is distributed to CPU and reads.Because exchange table entries 0 ~ 4 is also needed for CPU retaking of a year or grade, the result that poll moment 0 ~ 4 logic is read just can by directly multiplexing.According to polling mechanism, the retaking of a year or grade list item of CPU does not obtain at synchronization, therefore devises an exchange in invention and joins table cache, can by the result temporary cache of CPU retaking of a year or grade.The heap(ed) capacity of this buffer memory can adjust according to the actual flow of CPU retaking of a year or grade, does not join the expansion of table scale and expand with exchange.If retaking of a year or grade list item is stored in buffer memory needed for CPU, then need not carry out retaking of a year or grade again at next polling cycle, the power consumption of chip can be reduced so further.
The embodiment of the present invention can also be applied in other scenes, such as, if the frequency of utilization of CPU read port is very high, and the requirement of real-time that the very low and logic of the probability of use that logic is read is read is not high, then the retaking of a year or grade list item that can be read by multiplexing CPU read operation needs the content read realize logic read operation as being read by logic.Meanwhile, the problems such as the service efficiency of certain port of RAM is not high can also be solved by the application embodiment of the present invention.
The embodiment of the present invention provides a kind of method of CPU retaking of a year or grade, and as shown in Figure 2, described method comprises:
201, the pre-configured buffer memory of CPU needs the exchange stored from RAM to join table the retaking of a year or grade list item needing reading to define.
Wherein, the information storing and carry out exchanges data in switch between each passage is joined in table in described exchange.
202, when described logical circuit joins the content covering retaking of a year or grade list item of table reading from described exchange, by corresponding from described exchange join table read list item be stored into described buffer memory, and/or when described logical circuit from described exchange join table read information do not cover described retaking of a year or grade list item time, described CPU sends it back read request to described RAM, to join the list item of acquisition needs reading in table from described exchange and to be stored in described buffer memory.
203, described CPU inquires about the described retaking of a year or grade list item in described buffer memory, to carry out debugging and locating.
Particularly, described CPU judges whether there is significant bit in the described cache tag register corresponding with described buffer memory, when there is significant bit, described CPU reads described retaking of a year or grade list item corresponding to described significant bit from described buffer memory, then carries out debugging and locating.
The CPU read-back approach that the embodiment of the present invention provides can also be applied in other scenes, such as, if the frequency of utilization of CPU read port is very high, and the requirement of real-time that the very low and logic of the probability of use that logic is read is read is not high, then the retaking of a year or grade list item that can be read by multiplexing CPU read operation needs the content read realize logic read operation as being read by logic.Meanwhile, the problems such as the service efficiency of certain port of RAM is not high can also be solved by the application embodiment of the present invention.
The switch that the embodiment of the present invention provides and read-back approach, comprise: random access memory ram, gate circuit, central processor CPU, logical circuit, buffer memory, cache tag register, first the pre-configured buffer memory of CPU needs the exchange stored from RAM to join the retaking of a year or grade list item read table to define, when described logical circuit joins the content covering retaking of a year or grade list item of table reading from described exchange, by corresponding from described exchange join table read list item be stored into described buffer memory, and/or when described logical circuit from described exchange join table read information do not cover described retaking of a year or grade list item time, described CPU sends it back read request to described RAM, to join the list item of acquisition needs reading in table from described exchange and to be stored in described buffer memory, last described CPU inquires about the described retaking of a year or grade list item in described buffer memory, to carry out debugging and locating.The memory bank that prior art in return joins table by four port dual-ports random access memory rams usually realizes the operations such as CPU read and write, but using dual-portsRAM to realize the operations such as CPU read and write can cause the problem that switching equipment area and power consumption are all very large.And the embodiment of the present invention joins table by adopting dual-port two-ports RAM memory transactions, and the result of multiplexing logical read operation is as the result of CPU read operation, thus decreases the area of switching equipment and reduce the power consumption of switching equipment.
The switch that the embodiment of the present invention provides can realize the above-mentioned embodiment of the method provided, and concrete function realizes the explanation referred in embodiment of the method, does not repeat them here.The switch that the embodiment of the present invention provides and read-back approach go for field of wireless communications, but are not limited only to this.
One of ordinary skill in the art will appreciate that all or part of flow process realized in above-described embodiment method, that the hardware that can carry out instruction relevant by computer program has come, described program can be stored in a computer read/write memory medium, this program, when performing, can comprise the flow process of the embodiment as above-mentioned each side method.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or random store-memory body (Random Access Memory, RAM) etc.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (8)
1. a switch, is characterized in that, comprising: random access memory ram, gate circuit, central processor CPU, logical circuit, buffer memory;
Described RAM is dual-port two-ports type RAM, table is joined for memory transactions, described RAM comprises read port and write port, described CPU is used for being joined in table to described exchange by the write port of described RAM writing exchange message, and described exchange message is the information of carrying out exchanges data in described switch between each passage;
Described gate circuit comprises: output, first input end and the second input, and described output is connected with the read port of described RAM;
Described logical circuit sends logic read request by described second input to described RAM, and carries out exchanges data according to the content of joining table reading from described exchange;
Described buffer memory, for when described logical circuit joins the content covering retaking of a year or grade list item of table reading from described exchange, by corresponding from described exchange join table read list item be stored into described buffer memory, and/or when described logical circuit from described exchange join table read information do not cover described retaking of a year or grade list item time, described CPU is sent it back the list item of read request also needed for acquisition by the described first input end of described gate circuit to described RAM, be stored in described buffer memory, wherein, the list item showing to read joined by the needs that described retaking of a year or grade list item is defined by pre-configured described buffer memory for described CPU from described exchange,
Described CPU also for inquiring about the described retaking of a year or grade list item stored in described buffer memory, with realize debugging and location.
2. switch as claimed in claim 1, it is characterized in that, described switch also comprises: cache tag register, described cache tag register is connected with described CPU and described buffer memory, whether described cache tag register is for identifying described retaking of a year or grade list item stored in described buffer memory
So that when described CPU judges to there is significant bit in described cache tag register, from described buffer memory, obtain the retaking of a year or grade list item corresponding with described significant bit.
3. switch according to claim 1, is characterized in that, the read port of described RAM comprises: read enable signal subport, read address subport and read data subport;
The output of described gate circuit reads enable signal subport with described and described address subport of reading is connected, and described read data subport connects described buffer memory and described logical circuit.
4. switch according to claim 1, is characterized in that, the write port of described RAM comprises: write enable signal subport, write address subport and write data subport;
Described CPU is by described write enable signal subport, write address subport and write data subport and to join in table to described exchange and write exchange message.
5., according to the arbitrary described switch of Claims 1-4, it is characterized in that, described gate circuit is OR circuit.
6. switch according to claim 1, it is characterized in that, when described switch is crossbar switching matrix crossbar framework, described exchange is joined table and is stored the exchange message of carrying out exchanges data in the switch of described crossbar structure between each passage.
7. a method for CPU retaking of a year or grade, is characterized in that, comprises
The pre-configured buffer memory of CPU needs the exchange stored from RAM to join the retaking of a year or grade list item read table to define; Described RAM is dual-port two-ports type RAM;
When logical circuit joins the content covering retaking of a year or grade list item of table reading from described exchange, by corresponding from described exchange join table read list item be stored into described buffer memory, and/or when described logical circuit from described exchange join table read information do not cover described retaking of a year or grade list item time, described CPU sends it back read request to described RAM, to join the list item of acquisition needs reading in table from described exchange and to be stored in described buffer memory;
Described CPU inquires about the described retaking of a year or grade list item in described buffer memory, to carry out debugging and locating.
8. the method for CPU retaking of a year or grade according to claim 7, is characterized in that, the described retaking of a year or grade list item that described CPU inquires about in described buffer memory comprises: described CPU judges whether there is significant bit in the cache tag register corresponding with described buffer memory; When there is significant bit, described CPU reads described retaking of a year or grade list item corresponding to described significant bit from described buffer memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210126755.7A CN102685003B (en) | 2012-04-26 | 2012-04-26 | Data switching device and read-back method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210126755.7A CN102685003B (en) | 2012-04-26 | 2012-04-26 | Data switching device and read-back method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102685003A CN102685003A (en) | 2012-09-19 |
| CN102685003B true CN102685003B (en) | 2015-01-21 |
Family
ID=46816388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210126755.7A Expired - Fee Related CN102685003B (en) | 2012-04-26 | 2012-04-26 | Data switching device and read-back method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102685003B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3040806B1 (en) * | 2015-09-07 | 2019-10-11 | Continental Automotive France | ELECTRONIC VEHICLE CALCULATOR COMPATIBLE WITH THE CAN-FD COMMUNICATION PROTOCOL |
| CN113900974B (en) * | 2021-12-07 | 2022-04-19 | 睿思芯科(深圳)技术有限公司 | Storage device, data storage method and related equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01240938A (en) * | 1988-03-23 | 1989-09-26 | Toshiba Corp | Data read back method |
| US6550023B1 (en) * | 1998-10-19 | 2003-04-15 | Hewlett Packard Development Company, L.P. | On-the-fly memory testing and automatic generation of bitmaps |
| CN1504884A (en) * | 2002-11-29 | 2004-06-16 | 华为技术有限公司 | Self-testing method and apparatus for synchronous dynamic random memory |
| CN1798088A (en) * | 2004-12-30 | 2006-07-05 | 中兴通讯股份有限公司 | Dispatching method and equipment for searching and updating routes based on FPGA |
-
2012
- 2012-04-26 CN CN201210126755.7A patent/CN102685003B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01240938A (en) * | 1988-03-23 | 1989-09-26 | Toshiba Corp | Data read back method |
| US6550023B1 (en) * | 1998-10-19 | 2003-04-15 | Hewlett Packard Development Company, L.P. | On-the-fly memory testing and automatic generation of bitmaps |
| CN1504884A (en) * | 2002-11-29 | 2004-06-16 | 华为技术有限公司 | Self-testing method and apparatus for synchronous dynamic random memory |
| CN1798088A (en) * | 2004-12-30 | 2006-07-05 | 中兴通讯股份有限公司 | Dispatching method and equipment for searching and updating routes based on FPGA |
Non-Patent Citations (1)
| Title |
|---|
| SOPC中FPGA IP核配置方案研究与实现;梁颖;《万方数据企业知识服务平台学位论文》;20100730;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102685003A (en) | 2012-09-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2021004231A1 (en) | Data storage method for flash memory device and flash memory device | |
| CN103049390B (en) | The data processing method of apply metadata and storage system | |
| CN102722455B (en) | Method and device for storing data in flash memory equipment | |
| WO2023098032A1 (en) | Memory space extension method and apparatus, electronic device, and storage medium | |
| CN101719099A (en) | Method and device for reducing write amplification of solid state disk | |
| CN112632069B (en) | Hash table data storage management method, device, medium and electronic equipment | |
| CN101627372A (en) | Selectively utilizing a plurality of disparate solid state storage locations | |
| CN101986305A (en) | File system operating method and communication device | |
| CN112882649B (en) | Data storage device and non-volatile memory control method | |
| CN112506823B (en) | FPGA data reading and writing method, device, equipment and readable storage medium | |
| CN117632043B (en) | CXL memory module, control chip, data processing method, medium and system | |
| CN104781794A (en) | In-place change between transient and persistent state for data structures in non-volatile memory | |
| CN102981801B (en) | A kind of conversion method of local bus data bit width and device | |
| CN118363914B (en) | Data processing method, solid state disk device and host | |
| CN104575595A (en) | Nonvolatile random access memory device | |
| KR20180092715A (en) | Storage device managing duplicated data based on the number of operations | |
| CN103222286B (en) | Route switching device, network switching system and route switching method | |
| CN105404591A (en) | Processor system and storer control method for same | |
| CN102685003B (en) | Data switching device and read-back method | |
| CN102609364A (en) | Cache exchange method | |
| CN102789422B (en) | The method for writing data of solid state hard disc | |
| CN107544937A (en) | A kind of coprocessor, method for writing data and processor | |
| CN103246622B (en) | A kind of method of exented memory, memory node, host node and system | |
| CN105788636A (en) | EMMC controller based on parallel multichannel structure | |
| CN102789424A (en) | External extended DDR2 (Double Data Rate 2) read-write method on basis of FPGA (Field Programmable Gate Array) and external extended DDR2 particle storage on basis of FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150121 |