CN102646580B - Planarization method and gate structure applied in semiconductor element process - Google Patents

Abstract

The invention discloses a planarization method and a grid structure applied to a semiconductor element process. The method comprises the following steps: providing a substrate with a grid structure comprising a polysilicon dummy grid and a dielectric layer above; removing the polysilicon dummy gate to form a trench; forming a gate barrier layer in the trench; forming a grid metal layer on the surface of the grid barrier layer and filling the groove; performing a first planarization process on the gate metal layer by using a first reactant to remove part of the gate metal layer, wherein the etching rate of the first reactant to the gate metal layer is greater than that to the gate barrier layer; and performing a second planarization process on the gate barrier layer and the gate metal layer by using a second reactant to remove part of the gate barrier layer and the gate metal layer, wherein the etching rate of the second reactant to the gate barrier layer is greater than that to the gate metal layer.

Description

Planarization method and gate structure applied in semiconductor element process

technical field

The invention relates to a planarization method, in particular to a planarization method applicable to semiconductor element technology.

Background technique

With the rapid development of semiconductor components in recent years, the size of the components has entered the nanometer level, so the thickness of the gate insulating layer (Gate Dielectric Layer) in the metal oxide semiconductor transistor component is bound to be relatively thinner with the reduction of the channel size. However, an excessively thin insulating layer thickness will inevitably induce serious gate leakage current, and this leakage current will affect the characteristics of the device, resulting in increased energy consumption of the product. Therefore, it is a necessary means to introduce a high dielectric constant (hereinafter referred to as High-k) material to complete the gate insulating layer to reduce the generation of gate leakage current. In addition, the High-k process is often combined with a metal gate process to reduce the resistance of the gate electrode. In order to improve thermal stability and prevent the metal gate from reacting with the high dielectric constant gate insulating layer, a barrier layer is usually added between the metal gate and the high dielectric constant gate insulating layer. This is usually done with titanium nitride (TiN). However, in the manufacturing process of the above-mentioned gate structure, problems often arise due to poor planarization of the device surface. How to improve these problems is the main purpose of the development of the present invention.

Contents of the invention

The purpose of the present invention is to provide a planarization method, which can be applied to the integrated circuit process, so as to improve the disadvantages of poor planarization by known means.

The present invention proposes a planarization method, which is applied in the process of semiconductor elements. The method includes the following steps: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a groove; forming a barrier layer and a metal layer; using a first reactant to perform a first planarization process on the metal layer to remove part of the metal layer to expose the barrier layer, wherein the etching rate of the first reactant to the metal layer is greater than that of the metal layer The etch rate of the barrier layer; and using a second reactant to perform a second planarization process on the barrier layer and the metal layer to remove part of the barrier layer and the metal layer to expose the dielectric layer, wherein the second reactant The etch rate for the barrier layer is greater than the etch rate for the metal layer.

In a preferred embodiment of the present invention, the above planarization method further includes forming a gate dielectric layer under the dielectric layer.

In a preferred embodiment of the present invention, the above planarization method further includes forming a gate dielectric layer in the trench before forming the barrier layer.

In a preferred embodiment of the present invention, the above-mentioned gate dielectric layer is a high dielectric constant dielectric layer, the barrier layer is a gate barrier layer, and the metal layer is a gate metal layer.

In a preferred embodiment of the present invention, the above-mentioned high dielectric constant dielectric layer can be made of hafnium oxide (HfO ₂ ), hafnium silicon oxynitride (HfSiON) or hafnium silicon oxide (HfSiO) as a single layer or multilayer structure.

In a preferred embodiment of the present invention, the above barrier layer can be made of titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC), titanium carbide (TiC), tantalum nitride (TaN), titanium nitride Single-layer or multi-layer structures completed by materials such as aluminum (TiAlN).

In a preferred embodiment of the present invention, the above metal layer can be made of titanium nitride (TiN), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), cobalt ( Co), copper (Cu) or nickel (Ni) and other materials to complete the single-layer or multi-layer structure.

In a preferred embodiment of the present invention, the above-mentioned first planarization process and the second planarization process may be a first chemical mechanical polishing process and a second chemical mechanical polishing process, and the first reactant and the second The reactants can be the first chemical mechanical polishing agent and the second chemical mechanical polishing agent respectively. The first planarization process and the second planarization process can be completed on a single machine, or separately on a plurality of machines that provide different chemical mechanical polishing agents, and the first chemical mechanical polishing agent and the second chemical mechanical polishing The agent may also include an adhesive material comprising silica, ceria or alumina powder.

In a preferred embodiment of the present invention, both the above-mentioned first chemical mechanical polishing agent and the second chemical mechanical polishing agent may include an oxidizer (oxidizer), and the oxidizer concentration of the first chemical mechanical polishing agent may be lower than that of the second chemical mechanical polishing agent. Oxidizing agent concentration in mechanical polish.

In a preferred embodiment of the present invention, the above-mentioned oxidizing agent may be hydrogen peroxide.

In a preferred embodiment of the present invention, the hydrogen peroxide concentration range in the first chemical mechanical polishing agent may be 0% to 1%, and the hydrogen peroxide concentration range in the second chemical mechanical polishing agent may be greater than 1%. .

The present invention also proposes another planarization method, which is applied in the process of semiconductor elements. The method includes the following steps: providing a substrate with a gate structure including a polysilicon dummy gate and a dielectric layer above the substrate; removing the polysilicon dummy gate and Forming at least a trench in the dielectric layer; forming a gate barrier layer on the sidewall and bottom of the trench and on the surface of the dielectric layer; forming a gate metal layer on the surface of the gate barrier layer and filling Filling the trench; using a first reactant to perform a first planarization process on the gate metal layer to remove part of the gate metal layer to expose the gate barrier layer, wherein the first reactant is The etch rate of the gate metal layer is greater than the etch rate of the gate barrier layer; and a second reactant is used to perform a second planarization process on the gate barrier layer and the gate metal layer to remove A portion of the gate barrier layer and the gate metal layer exposes the dielectric layer, wherein the etching rate of the gate barrier layer by the second reactant is greater than the etching rate of the gate metal layer.

In a preferred embodiment of the present invention, the above planarization method further includes forming a gate dielectric layer under the dielectric layer.

In a preferred embodiment of the present invention, the above planarization method further includes forming a gate dielectric layer in the trench before forming the barrier layer.

In a preferred embodiment of the present invention, the step of removing part of the gate metal layer to expose the gate barrier layer may further include the following steps: using a third reactant to perform a third planarization on the gate metal layer The etching process is used to reduce the thickness of the gate metal layer to a predetermined thickness, and the etching rate of the gate metal layer by the third reactant is greater than the etching rate of the gate metal layer by the first reactant.

In a preferred embodiment of the present invention, the aforementioned preset thickness may be greater than 100 angstroms.

In a preferred embodiment of the present invention, the above-mentioned gate dielectric layer is a high dielectric constant dielectric layer, which is made of hafnium oxide (HfO ₂ ), hafnium silicon oxynitride (HfSiON) or Single-layer or multi-layer structures completed by materials such as hafnium silicon oxide (HfSiO).

In a preferred embodiment of the present invention, the above barrier layer can be made of titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC), titanium carbide (TiC), tantalum nitride (TaN), titanium nitride Single-layer or multi-layer structures completed by materials such as aluminum (TiAlN).

In a preferred embodiment of the present invention, the above metal layer can be made of titanium nitride (TiN), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), cobalt ( Co), copper (Cu) or nickel (Ni) and other materials to complete the single-layer or multi-layer structure.

In a preferred embodiment of the present invention, the above-mentioned first planarization process and the second planarization process can be a first chemical mechanical polishing process and a second chemical mechanical polishing process, and the first reactant and the second The reactants can be respectively a first chemical mechanical polishing agent and a second chemical mechanical polishing agent. The first planarization process and the second planarization process can be completed on a single machine, or separately on a plurality of machines that provide different chemical mechanical polishing agents, and the first chemical mechanical polishing agent and the second chemical mechanical polishing The agent may also include an adhesive material comprising silica, ceria or alumina powder.

In a preferred embodiment of the present invention, the etching selectivity ratio of the first chemical mechanical polishing agent for the gate metal layer to the gate barrier layer is greater than 20, and the second chemical mechanical polishing agent for the gate metal layer The etch selectivity ratio to the gate barrier layer is greater than 20.

In a preferred embodiment of the present invention, both the first chemical mechanical polishing agent and the second chemical mechanical polishing agent may include an oxidizer, and the oxidizer concentration of the first chemical mechanical polishing agent is lower than that of the second chemical mechanical polishing agent. 2. Oxidant concentration in chemical mechanical polishing agent.

In a preferred embodiment of the present invention, the above-mentioned oxidizing agent may be hydrogen peroxide.

In a preferred embodiment of the present invention, the hydrogen peroxide concentration range in the first chemical mechanical polishing agent may be 0% to 1%, and the hydrogen peroxide concentration range in the second chemical mechanical polishing agent may be greater than 1%. .

The invention also proposes another gate structure, which includes a substrate, a dielectric layer, a gate barrier layer, and a gate metal layer. The dielectric layer is located above the substrate and has at least one groove. The gate barrier layer is located in the trench. The gate metal layer is located on the surface of the gate barrier layer and fills up the trench. The top surface of the gate metal layer is lower than the sidewall of the trench, and the height difference between them is less than 50 angstroms.

Description of drawings

1(a), 1(b), and 1(c), which are schematic diagrams of the process steps of the planarization method developed by the present invention to improve the deficiencies of known means.

2(a) and 2(b), which are schematic diagrams of two gate structures completed by the technology of the present invention.

Explanation of reference signs

Substrate 10 Dielectric layer 101

Gate dielectric layer 1010

Barrier layer 102 Metal layer 103

groove 104 dish 1030

detailed description

Please refer to Figures 1(a), 1(b), and 1(c), which are schematic diagrams of the process steps of the planarization method developed by the present invention to improve the deficiencies of known means, and can be widely used in the semiconductor element process. First, a substrate 10 is provided, such as a common silicon substrate, and then a high dielectric constant/metal gate (HKMG) process is performed on the substrate 10 to complete a metal oxide semiconductor transistor device, as shown in FIG. 1(a), A dielectric layer 101 is formed above the substrate 10, a trench 104 is formed in the dielectric layer 101, and a gate dielectric layer (gate dielectric layer) 1010, a barrier layer (barrier layer) 102 are formed in the trench 104. and metal layer 103 to complete the gate structure. The trench 104 may be formed by removing a polysilicon dummy gate (dummy poly (not shown in the figure)). As for the gate dielectric layer 1010 in the gate structure, it can be formed after the trench 104 is formed to complete the structure shown in FIG. 1(a), but the gate dielectric layer can also be formed before the trench 104 is formed. The electrical layer 1010 is as shown in FIG. 2( a ). The gate dielectric layer 1010 can be made of a high-k dielectric material. The barrier layer may be a gate barrier layer in the gate structure, and the metal layer may be a gate metal layer in the gate structure.

Next, a first planarization process is performed on the metal layer 103 by using a first reactant to remove part of the metal layer 103 to expose the barrier layer 102, wherein by controlling the composition of the first reactant, the metal layer 103 will be planarized. The etch rate of the metal layer 103 is adjusted to be greater than the etch rate of the barrier layer 102 . In this way, the etching action can be stopped on the barrier layer 102, but also because the metal layer 103 is etched faster, a structure as shown in Figure 1(b) is produced, the barrier layer 102 is exposed and the metal layer 103 produces a slight dishing 1030 .

In order to eliminate the above-mentioned dish-shaped depressions 1030, the present invention uses a second reactant to perform a second planarization process on the exposed barrier layer 102 and the metal layer 103 to remove part of the barrier layer 102 and part of the metal layer 103. The metal layer 103 exposes the dielectric layer 101 outside the opening of the trench 104 , wherein the etching rate of the barrier layer 102 by the second reactant is greater than the etching rate of the metal layer 103 . In this way, the etching action can stop on the dielectric layer 101, but because the etching of the barrier layer 102 is faster and the etching of the metal layer 103 is slower, a structure as shown in FIG. 1(c) is produced, the metal layer The original dishing 1030 of 103 is eliminated, resulting in a flat surface. The top surface of the metal layer 103 is lower than the sidewall of the trench 104 , that is, the height difference between the top surfaces of the dielectric layers 101 on both sides is less than 50 angstroms. Finally, after cleaning, it can be sent to the next process, such as the production of the inner dielectric layer.

According to the description of the above steps, it can be seen that the present invention can effectively improve the flatness of the product after the process is completed through two planarization processes with different etching selectivity ratios, thereby improving the shortcomings of known methods and achieving the main purpose of developing the present invention. . The first planarization process and the second planarization process may be the first chemical mechanical polishing process and the second chemical mechanical polishing process, and the first reactant and the second reactant may be the first chemical mechanical polishing agent and the second chemical mechanical polishing process respectively. A second chemical mechanical polish. These planarization processes can be completed on a single machine (Single pad CMP), or separately on multiple machines that provide different chemical mechanical polishing agents (multi-pad CMP), and these chemical mechanical polishing agents also have Abrasive materials may be included, such as silicon dioxide (SiO ₂ ), cerium oxide (CeO ₂ ) or aluminum oxide (Al ₂ O ₃ ) powder. In addition, both the first chemical mechanical polishing agent and the second chemical mechanical polishing agent include an oxidizer. In order to adjust an appropriate etching selectivity ratio, the oxidizer concentration of the first chemical mechanical polishing agent will be lower than that of the second chemical mechanical polishing agent. The oxidizing agent concentration in the second chemical mechanical polishing agent, and this oxidizing agent can be hydrogen peroxide etc., for example, the hydrogen peroxide concentration range in the first chemical mechanical polishing agent can be 0%～1%, this second chemical mechanical polishing agent The concentration range of hydrogen peroxide in the polishing agent can be greater than 1%, such as 3% or 5%, so that the etching selectivity of the first chemical mechanical polishing agent for the gate metal layer and the gate barrier layer can be Controlled to be greater than 20, the etching selectivity ratio of the second chemical mechanical polishing agent for the gate metal layer and the gate barrier layer can be controlled to be greater than 20.

As for the gate dielectric layer (gate dielectric layer) 1010, it can be mainly completed by a high dielectric constant dielectric layer, such as hafnium oxide (HfO ₂ ), hafnium silicon oxynitride (HfSiON) or hafnium silicon oxide (HfSiO) The single-layer or multi-layer structure completed by other materials is mainly formed under the barrier layer 102. If the gate dielectric layer 1010 is formed before the trench 104 is completed (so-called "HK First"), the gate dielectric layer 1010 The layer 1010 will only be formed at the bottom of the trench 104 to form a schematic diagram of the gate structure completed by the technology of the present invention as shown in FIG. 1010 (so-called “HK Last”), the gate dielectric layer 1010 is formed on the bottom and sidewalls of the trench 104 to form a U-shaped cross-section, forming a gate structure as shown in FIG. 2( b ). As for the barrier layer 102, it can be made of titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC), titanium carbide (TiC), tantalum nitride (TaN), titanium aluminum nitride (TiAlN) and other materials. Single-layer or multi-layer structure, the barrier layer 102 can be used to act as a work function metal layer (Work Function metal layer), a stress layer (strained layer), a work function fine-tuning metal layer (Work Function tuning metal layer) in the gate structure , lining layer (liner layer) or sealing layer (sealantlayer) and other roles. As for the metal layer 103, it can be made of titanium nitride (TiN), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), copper (Cu) Or a single-layer or multi-layer structure completed by metal or metallic materials such as nickel (Ni).

In addition, in order to increase production capacity, before using the first reactant to remove part of the gate metal layer to expose the gate barrier layer, the metal layer 103 may be firstly subjected to a third reactant. The three-planarization process is used to reduce the thickness of the gate metal layer to a predetermined thickness, then stop and switch to the first planarization process. The preset thickness can be set close to 100 angstroms but greater than 100 angstroms, and since the third reactant can be adjusted to have a faster etching rate to the metal layer 103, that is, the etching rate of the third reactant to the metal layer 103 The etching rate of the metal layer 103 is greater than that of the first reactant, so the thickness of the metal layer 103 can be reduced quickly to reduce the process time.

To sum up, after the improvement of the technology in the present invention, the problem of poor planarization in the known methods can be effectively eliminated. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection of the invention should be defined by the claims.

Claims (23)

1. a flattening method, is applied in semiconductor element technique, and the method comprises the following steps:

Substrate is provided；

Form dielectric layer on this substrate, wherein this dielectric layer has groove；

Gate dielectric, barrier layer and metal level, wherein this gate dielectric is sequentially formed in this groove It is only formed in this groove；

The first reactant is utilized to carry out the first flatening process to this metal level, in order to remove being somebody's turn to do of part Metal level and expose this barrier layer, wherein this first reactant to the etch-rate of this metal level more than to this The etch-rate of barrier layer；And

The second reactant is utilized to carry out the second flatening process to this barrier layer and this metal level, in order to remove Going this barrier layer of part and this metal level to expose this dielectric layer, wherein this second reactant is to this barrier The etch-rate of layer is more than the etch-rate to this metal level, wherein this first reactant and this second reaction All including oxidant in agent, the oxidant concentration of this first reactant is less than the oxygen in this second reactant Agent concentration.

2. flattening method as claimed in claim 1, wherein this gate dielectric is that high-k is situated between Electric layer, this barrier layer is gate barrier layer, and this metal level is gate metal layer.

3. flattening method as claimed in claim 2, wherein this dielectric layer with high dielectric constant is by aoxidizing The single or multiple lift structure that hafnium, hafnium silicon oxynitride or hafnium silicon oxide complete.

4. flattening method as claimed in claim 1, wherein this barrier layer be by titanium nitride, ramet, The single or multiple lift structure that tungsten carbide, titanium carbide, tantalum nitride, TiAlN complete.

5. flattening method as claimed in claim 1, wherein this metal level be by titanium nitride, tungsten, aluminium, The single or multiple lift structure that titanium, tantalum, tantalum nitride, cobalt, copper or nickel complete.

6. flattening method as claimed in claim 1, wherein this first flatening process is second flat with this Smooth metallization processes is respectively the first CMP process and the second CMP process, and this first Reactant and this second reactant are respectively the first chemical mechnical polishing agent and the second chemical mechnical polishing agent, These flatening process complete on single board, or are divided among providing different chemical mechnical polishing agent Complete on multiple boards, and these chemical mechnical polishing agents also include silica, ceria or It is the sticky material of alumina powder.

7. flattening method as claimed in claim 1, wherein this oxidant is hydrogen peroxide.

8. flattening method as claimed in claim 6, the wherein mistake in this first chemical mechnical polishing agent Hydrogen peroxide concentration scope is 0～1, the concentration of hydrogen peroxide scope in this second chemical mechnical polishing agent For more than 1.

9. a flattening method, is applied in semiconductor element technique, and the method comprises the following steps:

There is provided substrate, this surface has the gate configuration including polycrystalline silicon dummy gate pole and dielectric layer；

Remove this polycrystalline silicon dummy gate pole and in this dielectric layer, form at least one groove；

Form gate dielectric only in the groove；

Form gate barrier layer on the surface of this trenched side-wall and bottom and this dielectric layer；

Form gate metal layer and and fill up this groove on the surface of this gate barrier layer；

The first reactant is utilized to carry out the first flatening process to this gate metal layer, in order to remove part This gate metal layer and expose this gate barrier layer, wherein this first reactant is to this gate metal layer Etch-rate is more than the etch-rate to this gate barrier layer；And

The second reactant is utilized to carry out the second smooth chemical industry to this gate barrier layer and this gate metal layer Skill, exposes this dielectric layer in order to remove this gate barrier layer of part and this gate metal layer, wherein should The etch-rate to this gate barrier layer for second reactant is more than the etch-rate to this gate metal layer, should First reactant and this second reactant all include oxidant, the oxidant concentration of this first reactant Less than the oxidant concentration in this second reactant.

10. flattening method as claimed in claim 9, wherein in this gate metal layer removing part Also comprise the following steps: before the step exposing this gate barrier layer

The 3rd reactant is utilized to carry out the 3rd flatening process to this gate metal layer, in order to reduce this grid The thickness of pole metal level is more than to preset thickness, the etch-rate to this gate metal layer for the 3rd reactant This first reactant etch-rate to this gate metal layer.

11. flattening methods as claimed in claim 10, wherein this preset thickness is more than 100 angstroms.

12. flattening methods as claimed in claim 9, wherein this gate dielectric is that high-k is situated between Electric layer, this dielectric layer with high dielectric constant is the list being completed by hafnium oxide, hafnium silicon oxynitride or hafnium silicon oxide Layer or sandwich construction.

13. flattening methods as claimed in claim 9, wherein this barrier layer be by titanium nitride, ramet, The single or multiple lift structure that tungsten carbide, titanium carbide, tantalum nitride, TiAlN complete.

14. flattening methods as claimed in claim 9, wherein this metal level be by titanium nitride, tungsten, aluminium, The single or multiple lift structure that titanium, tantalum, tantalum nitride, cobalt, copper or nickel complete.

15. flattening methods as claimed in claim 9, wherein this first flatening process is second flat with this Smooth metallization processes is respectively the first CMP process and the second CMP process, and this first Reactant and this second reactant are respectively the first chemical mechnical polishing agent and the second chemical mechnical polishing agent, These flatening process complete on single board, or are divided among providing different chemical mechnical polishing agent Complete on multiple boards, and these chemical mechnical polishing agents also include silica, ceria or It is the sticky material of alumina powder.

16. flattening methods as claimed in claim 15, wherein this first chemical mechnical polishing agent for This gate metal layer is more than 20 with the etching selectivity of this gate barrier layer, this second chemical mechnical polishing agent Etching selectivity for this gate metal layer and this gate barrier layer is more than 20.

17. flattening methods as claimed in claim 15, wherein this oxidant is hydrogen peroxide.

18. flattening methods as claimed in claim 17, wherein in this first chemical mechnical polishing agent Concentration of hydrogen peroxide scope is 0～1, the concentration of hydrogen peroxide model in this second chemical mechnical polishing agent Enclose for more than 1.

19. 1 kinds of gate configuration, comprising:

Substrate；

Dielectric layer, is positioned at this surface and has at least one groove；

Gate dielectric, is positioned at below this dielectric layer or is only located in this groove；

Gate barrier layer, is positioned in this groove, on the surface of this gate dielectric；And

Gate metal layer, is positioned on the surface of this gate barrier layer and fills up this groove, this gate metal layer End face is less than this trenched side-wall, and both differences in height are less than 50 angstroms.

20. gate configuration as claimed in claim 19, wherein this gate dielectric is that high-k is situated between Electric layer.

21. gate configuration as claimed in claim 20, wherein this dielectric layer with high dielectric constant is by aoxidizing The single or multiple lift structure that hafnium, hafnium silicon oxynitride or hafnium silicon oxide complete.

22. gate configuration as claimed in claim 19, wherein this gate barrier layer is for by titanium nitride, carbon The single or multiple lift structure that change tantalum, tungsten carbide, titanium carbide, tantalum nitride, TiAlN complete, this grid Barrier layer is as workfunction layers, stressor layers, work function fine setting metal level, inner liner or sealing layer.

23. gate configuration as claimed in claim 19, wherein this gate metal layer be by titanium nitride, tungsten, The single or multiple lift structure that aluminium, titanium, tantalum, tantalum nitride, cobalt, copper or nickel complete.