CN102638248A - Voltage type four-value Schmidt trigger circuit based on neuron MOS (Metal Oxide Semiconductor) tube - Google Patents

Abstract

The invention discloses a voltage-type four-value Schmitt trigger circuit based on a neuron MOS tube, which includes a threshold 0.5 inversion operation and a threshold 0.5 operation circuit part 11 with a hysteresis characteristic, and a threshold 1.5 inversion circuit part 11 with a hysteresis characteristic. Phase operation and threshold 1.5 operation circuit part 12, threshold 2.5 inverse operation and threshold 2.5 operation circuit part 13 with hysteresis characteristic, four-valued signal transmission control circuit part 14. The present invention is completely based on the standard double-layer polysilicon CMOS process, and the three hysteresis voltage values in the four-valued Schmidt circuit can be adjusted by changing the capacitive coupling coefficient ratio. The scheme of complementary neuron MOS tube with independent floating gate structure is adopted to ensure that the circuit has the characteristics of low power consumption and high noise tolerance. In addition, because the threshold operation and its inverting circuit designed by the neuron MOS transistor are easy to realize the control of the threshold, this makes the proposed four-valued Schmidt circuit have a simple structure.

Description

A voltage-type four-value Schmitt trigger circuit based on neuron MOS tube

technical field

The invention relates to a Schmitt trigger circuit, in particular to a voltage-type four-value Schmitt trigger circuit based on a neuron MOS tube.

Background technique

The Schmitt trigger can effectively suppress the interference superimposed on the signal and eliminate the signal chatter, so it is widely used. It is a common circuit for shaping the signal and improving the on/off control in analog and digital systems. Two important features of the Schmidt circuit are: it can effectively receive slowly changing input signals and convert them into rapidly changing output signals; it has different detection thresholds for the DC transfer characteristics of positive and negative input signals, and the two The difference between them is called hysteresis. In multi-valued logic circuits, multi-valued Schmidt circuits should also have their corresponding status. The detection of the signal value by the circuit is made by comparing the input signal with a threshold, and the detection threshold is between two adjacent signal values. Therefore, in order to detect an m-valued logic signal, whose values are 0, 1, ..., m-1, 0.5, 1.5, ..., m-1.5 need to be set in the circuit, a total of m-1 detection thresholds. In the design of the multi-valued Schmidt circuit, it is necessary to control the m-1 detection thresholds to realize the hysteresis characteristics of the corresponding thresholds, so the design of the multi-valued Schmidt circuit is much more complicated than that of the binary circuit.

At present, the multi-valued Schmidt circuits designed based on CMOS technology mainly include current type and voltage type. The multi-valued current CMOS Schmidt circuit usually consumes a large power consumption due to the existence of a DC path. Although the multi-valued voltage CMOS Schmidt circuit has the characteristics of low power consumption, the multi-valued voltage CMOS circuit has multiple A threshold MOS tube needs to add an additional ion implantation process or use both enhancement type and depletion type MOS tubes, which increases the complexity of the process and limits the practicability. Because the four-value logic circuit is easy to realize the interface with the two-value logic circuit, the design of the four-value CMOS Schmidt circuit is particularly meaningful.

Contents of the invention

The purpose of the present invention is to propose a voltage-type four-valued Schmitt trigger circuit based on neuron MOS transistors. In addition to the characteristics of low power consumption and simple structure, they can also be adjusted by changing the capacitive coupling coefficient of the input terminal. hysteresis voltage.

The design solution of the present invention is in order to realize above-mentioned object. The present invention provides a voltage-type four-value Schmitt trigger circuit based on a neuron MOS tube, comprising a threshold 0.5 circuit, a threshold 1.5 circuit, a threshold 2.5 circuit and a four-value signal transmission control circuit; the threshold 0.5 circuit is connected with Power supply V _DD , power supply V ₂ and input signal terminal V _in ; the threshold 1.5 circuits are respectively connected to power supply V _DD , power supply V ₂ , power supply V ₁ and input signal terminal V _in ; the threshold 2.5 circuits are respectively connected to power supply V _DD , power supply V ₁ and input signal terminal V _in ; the four-valued signal transmission control circuit is respectively connected with power supply V _DD , power supply V ₁ , power supply V ₂ and output signal terminal V _out ; the threshold 0.5 circuit, threshold 1.5 circuit And the threshold 2.5 circuit is respectively connected with the four-valued signal transmission control circuit.

As a further description of a voltage-type four-value Schmitt trigger circuit based on a neuron MOS tube: the threshold 0.5 circuit includes a threshold 0.5 inverting operation circuit and a threshold 0.5 operation circuit with hysteresis characteristics; the threshold The 0.5 inversion operation circuit and the threshold 0.5 operation circuit are composed of a complementary threshold 0.5 inverter, a common binary CMOS inverter and a feedback circuit; the complementary threshold 0.5 inverter includes a neuron pMOS transistor m _p1 and a neuron nMOS transistor m _n1 ; the common binary CMOS inverter includes pMOS transistor m _p2 and nMOS transistor m _n2 ; the source of the neuron pMOS transistor m _p1 is connected to the power supply V _DD , and the drain of the neuron pMOS transistor m _p1 connected to the drain of the neuron nMOS transistor m _n1 , and the neuron pMOS transistor m _p1 has three gate input terminals, and the coupling capacitances between the three input gates and the floating gate are capacitance C _p1 , capacitance C _p2 and Capacitor C _p3 ; the source of the neuron nMOS transistor m _n1 is grounded, and the neuron nMOS transistor m _n1 has three gate input terminals, and the coupling capacitances between the three input gates and the floating gate are capacitance C _n1 , capacitance C _n2 and capacitor C _n3 ; the source of the pMOS transistor m _p2 in the CMOS inverter is connected to the power supply V _DD , the drain of the pMOS transistor m _p2 is connected to the drain of the nMOS transistor m _n2 in the CMOS inverter, and the nMOS transistor m The source of _n2 is grounded; the gate of the pMOS transistor m _p2 in the CMOS inverter is connected to the gate of the nMOS transistor m _n2 as the input end of the CMOS inverter; the input end of the CMOS inverter is connected to the The drain of the neuron pMOS transistor m _p1 is connected to the drain of the neuron nMOS transistor m _n1 ; a gate input terminal of the neuron nMOS transistor m _n1 is connected to a gate of the neuron pMOS transistor m _p1 The input terminal is connected to the input signal terminal V _in ; the other gate input terminal of the neuron pMOS transistor m _p1 is connected to the power supply V _DD , and the remaining input gate of the neuron pMOS transistor m _p1 is connected to the CMOS inverter The drain of the middle pMOS transistor m _p2 is connected to the drain of the nMOS transistor m _n2 to form a positive feedback circuit; the other gate input terminal of the neuron nMOS transistor m _n1 is connected to the power supply V ₂ , and the rest of the neuron nMOS transistor m _n1 An input grid is connected with the drain of the pMOS transistor m _p2 and the drain of the nMOS transistor m _n2 in the CMOS inverter to form a positive feedback circuit; the threshold 1.5 circuit includes a threshold 1.5 inverting operation circuit with hysteresis characteristics and threshold 1.5 operation circuit; the threshold 1.5 inverting operation circuit and the threshold 1.5 operation circuit are made up of complementary threshold 1.5 inverter, common binary CMOS inverter and feedback circuit; the complementary threshold 1.5 inverter Including neuron pMOS tube m _p3 and neuron nMOS tube m _n3 ; the common binary CMOS inverter includes pMOS tube m _p4 and nMOS tube m _n4 ; the source of the neuron pMOS tube m _p3 is connected to the power supply V _DD , the drain of the neuron pMOS tube m _p3 is connected to the drain of the neuron nMOS tube m _n3 , and the neuron pMOS tube m _p3 has three gate input terminals, the coupling capacitances between the three input gates and the floating gate are capacitance C _p4 , capacitance C _p5 and capacitance C _p6 respectively; the source of the neuron nMOS transistor m _n3 is grounded, and the neuron nMOS transistor m _n3 has three gate input terminals, and the coupling capacitances between these three input gates and the floating gate are capacitor C _n4 , capacitor C _n5 and capacitor C _n6 respectively; the source of pMOS transistor m _p4 in the CMOS inverter connected to the power supply V _DD , the drain of the pMOS transistor m _p4 is connected to the drain of the nMOS transistor m _n4 in the CMOS inverter, and the source of the nMOS transistor m _n4 is grounded; the gate of the pMOS transistor m _p4 in the CMOS inverter is connected to the The gate of the nMOS transistor m _n4 is connected as the input end of the CMOS inverter; the input end of the CMOS inverter is connected to the drain of the neuron pMOS transistor m _p3 and the drain of the neuron nMOS transistor m _n3 The gate input terminal of the neuron nMOS transistor m _n3 and a gate input terminal of the neuron pMOS transistor m _p3 are connected with the input signal terminal V _in ; the other gate input terminal of the neuron pMOS transistor m _p3 One gate input terminal is connected to the power supply _V2 , and the remaining input gate of the neuron pMOS transistor _mp3 is connected to the drain of the pMOS transistor _mp4 in the CMOS inverter and the drain of the nMOS transistor _mn4 to form a positive feedback circuit; The other gate input terminal of the neuron nMOS transistor m _n3 is connected to the power supply V ₁ , and the remaining input gate of the neuron nMOS transistor m _n3 is connected to the drain of the pMOS transistor m _p4 and the nMOS transistor m _n4 in the CMOS inverter The drains of the drains are connected to form a positive feedback circuit; the threshold 2.5 circuit includes a threshold 2.5 inversion operation circuit and a threshold 2.5 operation circuit with hysteresis characteristics; the threshold 2.5 inversion operation circuit and the threshold 2.5 operation circuit are composed of complementary Threshold 2.5 inverter, common binary CMOS inverter and feedback circuit; said threshold 2.5 inverter includes neuron pMOS transistor m _p5 and neuron nMOS transistor m _n5 ; said common binary CMOS inverter includes pMOS tube m _p6 and nMOS tube m _n6 ; the source of the neuron pMOS tube m _p5 is connected to the power supply V _DD , the drain of the neuron pMOS tube m _p5 is connected to the drain of the neuron nMOS tube m _n5 , and the neuron The pMOS transistor m _p5 has three gate input terminals, and the coupling capacitances between the three input gates and the floating gate are capacitor C _p7 , capacitor C _p8 and capacitor C _p9 respectively; the source of the neuron nMOS transistor m _n5 is grounded , the neuron nMOS transistor m _n5 has three gate input terminals, and the coupling capacitances between the three input gates and the floating gate are electric capacitor C _n7 , capacitor C _n8 and capacitor C _n9 ; the source of the pMOS transistor m _p6 in the CMOS inverter is connected to the power supply V _DD , and the drain of the pMOS transistor m _p6 is connected to the drain of the nMOS transistor m _n6 in the CMOS inverter pole, the source of the nMOS transistor m _n6 is grounded; the gate of the pMOS transistor m _p6 in the CMOS inverter is connected to the gate of the nMOS transistor m _n6 as the input end of the CMOS inverter; the CMOS inverter The input end of the neuron pMOS transistor m _p5 is connected to the drain electrode of the neuron nMOS transistor m _n5 ; a gate input end of the neuron nMOS transistor m _n5 is connected to the neuron pMOS transistor m n5 One gate input terminal of m _p5 is connected to the input signal terminal V _in , the other gate input terminal of the neuron pMOS transistor m _p5 is connected to the power supply V ₁ , and the remaining input gate of the neuron pMOS transistor m _p5 is connected to the CMOS The drain of the pMOS transistor m _p6 in the inverter is connected to the drain of the nMOS transistor m _n6 to form a positive feedback circuit; the other gate input terminal of the neuron nMOS transistor m _n5 is grounded, and the remaining gate of the neuron nMOS transistor m _n5 An input gate is connected with the drain of pMOS transistor m _p6 and the drain of nMOS transistor m _n6 in the CMOS inverter to form a positive feedback circuit; the four-valued signal transmission control circuit is composed of pMOS transistor m _p7 and pMOS transistor m _p8 , pMOS transistor m _p9 and nMOS transistor m _n7 , nMOS transistor m _n8 , and nMOS transistor m _n9 ; the source of the pMOS transistor m _p7 is connected to the power supply V _DD , and the drain of the pMOS transistor m _p7 is connected to the nMOS transistor m The drain of _n7 , the gate of pMOS transistor m _p7 are connected to the drains of pMOS transistor m _p2 and nMOS transistor m _n2 in the ordinary binary CMOS inverter in the threshold 0.5 circuit; the source of the nMOS transistor m _n7 Grounded, the gate of the nMOS transistor m _n7 is connected to the drains of the pMOS transistor m _p6 and the nMOS transistor m _n6 in the common binary CMOS inverter in the threshold 2.5 circuit; the drain of the pMOS transistor m _p8 and the The source of the pMOS transistor m _p9 is connected in series between the power supply _V2 and the output signal terminal V _out , and the gate of the pMOS transistor m _p8 is connected to the neuron pMOS transistor m _p1 and the neuron nMOS transistor m _n1 in the threshold 0.5 circuit The drain of the nMOS transistor m _n8 and the drain of the nMOS transistor m _n9 are connected in series between the output signal terminal V _out and the power supply V ₁ ; the gate of the nMOS transistor m _n9 is connected to the threshold 2.5 The drains of the neuron pMOS transistor m _p5 and the neuron nMOS transistor m _n5 in the circuit; the gate of the pMOS transistor m _p9 and the gate of the nMOS transistor m _n8 are connected to the common two in the threshold 1.5 circuit The value is the drain of pMOS transistor m _p4 and nMOS transistor m _n4 in the CMOS inverter.

Compared with the existing design scheme, the present invention has the beneficial effect that: relative to the input terminal, the threshold voltage of the neuron MOS device or circuit can be controlled by an external control gate signal, which effectively overcomes the traditional voltage-type multiple Value logic circuits require additional ion implantation processes to realize MOS transistors with multiple threshold voltages or need to use both enhancement type and depletion type MOS transistors to increase process complexity and other defects. The circuit takes advantage of the natural property that the threshold of the neuron MOS transistor is easy to control, without adding a special circuit, it can be easily implemented by adding a gate input terminal to the p-type and n-type floating gate MOS transistors respectively. Regenerative feedback in the Mitte circuit, which makes the designed circuit have a very simple structure. The scheme of complementary floating gate MOS tube with independent floating gate structure is adopted to ensure that the circuit has the characteristics of low power consumption and high noise tolerance. Moreover, the hysteresis voltage can be adjusted conveniently by changing the capacitive coupling coefficient. By increasing the number of input terminals of the floating gate MOS transistor, it is very easy to access an external control signal, thereby changing the high and low threshold voltages in the Schmidt circuit. Therefore, the biggest feature of the present invention is that it is convenient to adjust the hysteresis voltage and the threshold voltage can be directly controlled by an external control signal. The invention is completely based on the standard double-layer polysilicon CMOS technology. In addition to maintaining the low power consumption of the voltage type circuit, the new design has the characteristics of simple circuit structure, easy adjustment of hysteresis voltage, and convenient and flexible control of threshold voltage.

Description of drawings

The specific implementation manners of the present invention will be described in further detail below in conjunction with the accompanying drawings.

Figure 1 is a voltage-type four-value Schmitt trigger circuit based on a neuron MOS tube;

Fig. 2 is the symbol of n-type neuron MOS tube and p-type neuron MOS tube involved in Fig. 1 and their capacitance models;

Fig. 3 is the voltage transmission characteristic curve {C _n(p)i :C _n(p)(i+1) :C _n(p)(i+2) = 15:15:1,i∈(1,4,7)};

Fig. 4 is the voltage transfer characteristic curve {C _n(p)i :C _n(p)(i+1) :C _n(p)(i+2) = 6:6:1, i ∈ (1,4,7)}.

Detailed ways

Embodiment 1, Figure 1 shows a voltage-type four-value Schmitt trigger circuit based on a neuron MOS tube, including a threshold 0.5 circuit 11, a threshold 1.5 circuit 12, a threshold 2.5 circuit 13 and a four-value signal transmission control circuit 14. Threshold 0.5 circuit 11 is respectively connected to power supply V _DD , power supply V ₂ and input signal terminal V _in ; threshold 1.5 circuit 12 is respectively connected to power supply V _DD , power supply V ₂ , power supply V ₁ and input signal terminal V _in ; threshold 2.5 Circuit 13 is respectively connected with power supply V _DD , power supply V ₁ and input signal terminal V _in ; four-value signal transmission control circuit 14 is respectively connected with power supply V _DD , power supply V ₁ , power supply V ₂ and output signal terminal V _out ; threshold 0.5 circuit 11. The threshold 1.5 circuit 12 and the threshold 2.5 circuit 13 are respectively connected to the four-valued signal transmission control circuit 14 . The specific connection method is as follows:

The threshold 0.5 circuit 11 includes a threshold 0.5 inversion operation circuit and a threshold 0.5 operation circuit with hysteresis characteristics; the threshold 0.5 inversion operation circuit and the threshold 0.5 operation circuit are composed of complementary threshold 0.5 inverters and common binary CMOS inverters and a feedback circuit; the complementary threshold 0.5 inverter includes neuron pMOS transistor m _p1 and neuron nMOS transistor m _n1 ; the ordinary binary CMOS inverter includes pMOS transistor m _p2 and nMOS transistor m _n2 .

The source of the neuron pMOS transistor m _p1 is connected to the power supply V _DD , the drain of the neuron pMOS transistor m _p1 is connected to the drain of the neuron nMOS transistor m _n1 , and the neuron pMOS transistor m _p1 has three gate input terminals. These three inputs The coupling capacitances between the gate and the floating gate are capacitance C _p1 , capacitance C _p2 and capacitance C _p3 respectively; the source of the neuron nMOS transistor m _n1 is grounded, and the neuron nMOS transistor m _n1 has three gate input terminals. The coupling capacitances between the input gate and the floating gate are capacitance C _n1 , capacitance C _n2 and capacitance C _n3 respectively; in the CMOS inverter, the source of pMOS transistor m _p2 is connected to power supply V _DD , and the drain of pMOS transistor m _p2 is connected to The drain of the nMOS transistor m _n2 in the CMOS inverter, and the source of the nMOS transistor m _n2 are grounded; the gate of the pMOS transistor m _p2 in the CMOS inverter is connected to the gate of the nMOS transistor m _n2 as the gate of the CMOS inverter Input terminal; the input terminal of the CMOS inverter is connected to the drain of the neuron pMOS transistor m _p1 and the drain of the neuron nMOS transistor m _n1 ; a gate input terminal of the neuron nMOS transistor m _n1 is connected to the neuron pMOS transistor m One gate input terminal of _p1 is connected to the input signal terminal V _in ; the other gate input terminal of the neuron pMOS transistor m _p1 is connected to the power supply V _DD , and the remaining input gate of the neuron pMOS transistor m _p1 is connected to the CMOS inverter The drain of the middle pMOS transistor m _p2 is connected to the drain of the nMOS transistor m _n2 to form a positive feedback circuit; the other gate input terminal of the neuron nMOS transistor m _n1 is connected to the power supply V ₂ , and the remaining input of the neuron nMOS transistor m _n1 The gate is connected with the drain of the pMOS transistor m _p2 and the drain of the nMOS transistor m _n2 in the CMOS inverter to form a positive feedback circuit.

The threshold 1.5 circuit 12 includes a threshold 1.5 inversion operation circuit and a threshold 1.5 operation circuit with hysteresis characteristics; the threshold 1.5 inversion operation circuit and the threshold 1.5 operation circuit are composed of complementary threshold 1.5 inverters and common binary CMOS inverters and a feedback circuit; the complementary threshold 1.5 inverter includes neuron pMOS transistor m _p3 and neuron nMOS transistor m _n3 ; the common binary CMOS inverter includes pMOS transistor m _p4 and nMOS transistor m _n4 .

The source of the neuron pMOS transistor m _p3 is connected to the power supply V _DD , the drain of the neuron pMOS transistor m _p3 is connected to the drain of the neuron nMOS transistor m _n3 , and the neuron pMOS transistor m _p3 has three gate input terminals. The coupling capacitances between the gate and the floating gate are capacitance C _p4 , capacitance C _p5 and capacitance C _p6 respectively; the source of the neuron nMOS transistor m _n3 is grounded, and the neuron nMOS transistor m _n3 has three gate input terminals. The coupling capacitors between the input gate and the floating gate are capacitor C _n4 , capacitor C _n5 and capacitor C _n6 respectively; in the CMOS inverter, the source of pMOS transistor m _p4 is connected to the power supply V _DD , and the drain of pMOS transistor m _p4 is connected to The drain of the nMOS transistor m _n4 in the CMOS inverter, and the source of the nMOS transistor m _n4 are grounded; the gate of the pMOS transistor m _p4 in the CMOS inverter is connected to the gate of the nMOS transistor m _n4 as the gate of the CMOS inverter Input terminal; the input terminal of the CMOS inverter is connected to the drain of the neuron pMOS transistor m _p3 and the drain of the neuron nMOS transistor m _n3 ; a gate input terminal of the neuron nMOS transistor m _n3 is connected to the neuron pMOS transistor m One gate input terminal of _p3 is connected to the input signal terminal V _in ; the other gate input terminal of the neuron pMOS transistor m _p3 is connected to the power supply V ₂ , and the remaining input gate of the neuron pMOS transistor m _p3 is connected to the pMOS in the CMOS inverter The drain of the tube m _p4 is connected to the drain of the nMOS tube m _n4 to form a positive feedback circuit; the other gate input terminal of the neuron nMOS tube m _n3 is connected to the power supply V ₁ , and the remaining input gate of the neuron nMOS tube m _n3 is connected to In the CMOS inverter, the drain of the pMOS transistor m _p4 is connected to the drain of the nMOS transistor m _n4 to form a positive feedback circuit.

The threshold 2.5 circuit 13 includes a threshold 2.5 inverting operation circuit and a threshold 2.5 operation circuit with hysteresis characteristics; the threshold 2.5 inversion operation circuit and the threshold 2.5 operation circuit are composed of complementary threshold 2.5 inverters and common binary CMOS inverters and a feedback circuit; the threshold 2.5 inverter includes neuron pMOS transistor m _p5 and neuron nMOS transistor m _n5 ; the ordinary binary CMOS inverter includes pMOS transistor m _p6 and nMOS transistor m _n6 .

The source of the neuron pMOS transistor m _p5 is connected to the power supply V _DD , the drain of the neuron pMOS transistor m _p5 is connected to the drain of the neuron nMOS transistor m _n5 , and the neuron pMOS transistor m _p5 has three gate input terminals. The coupling capacitances between the gate and the floating gate are capacitance C _p7 , capacitance C _p8 and capacitance C _p9 respectively; the source of the neuron nMOS transistor m _n5 is grounded, and the neuron nMOS transistor m _n5 has three gate input terminals, the three The coupling capacitors between the input gate and the floating gate are capacitor C _n7 , capacitor C _n8 and capacitor C _n9 respectively; the source of pMOS transistor m _p6 in the CMOS inverter is connected to the power supply V _DD , and the drain of pMOS transistor m _p6 is connected to The drain of the nMOS transistor m _n6 in the CMOS inverter, the source of the nMOS transistor m _n6 is grounded; the gate of the pMOS transistor m _p6 in the CMOS inverter is connected to the gate of the nMOS transistor m _n6 as the gate of the CMOS inverter Input terminal; the input terminal of the CMOS inverter is connected to the drain of the neuron pMOS transistor m _p5 and the drain of the neuron nMOS transistor m _n5 ; a gate input terminal of the neuron nMOS transistor m _n5 is connected to the neuron pMOS transistor m One gate input terminal of _p5 is connected to the input signal terminal V _in , the other gate input terminal of the neuron pMOS transistor m _p5 is connected to the power supply V ₁ , and the remaining input gate of the neuron pMOS transistor m _p5 is connected to the pMOS in the CMOS inverter The drain of the tube m _p6 is connected to the drain of the nMOS tube m _n6 to form a positive feedback circuit; the other gate input terminal of the neuron nMOS tube m _n5 is grounded, and the remaining input gate of the neuron nMOS tube m _n5 is reversed to the CMOS The drain of the pMOS transistor m _p6 in the device is connected to the drain of the nMOS transistor m _n6 to form a positive feedback circuit.

The four-value signal transmission control circuit (14) is composed of pMOS transistor _mp7 , pMOS transistor _mp8 , pMOS transistor _mp9 , nMOS transistor _mn7 , nMOS transistor _mn8 , and nMOS transistor _mn9 ; the source of pMOS transistor _mp7 is connected to the power supply V _DD , the drain of the pMOS transistor m _p7 is connected to the drain of the nMOS transistor m _n7 , and the gate of the pMOS transistor m _p7 is connected to the pMOS transistor m _p2 and the nMOS transistor m _n2 of the ordinary binary CMOS inverter in the circuit 11 with a threshold of 0.5 The drain of the nMOS transistor m _n7 is grounded, and the gate of the nMOS transistor m _n7 is connected to the drains of the pMOS transistor m _p6 and the nMOS transistor m _n6 in the ordinary binary CMOS inverter in the threshold 2.5 circuit 13; the pMOS transistor The drain of m _p8 and the source of pMOS transistor m _p9 are connected in series between the power supply V ₂ and the output signal terminal V _out , and the gate of pMOS transistor m _p8 is connected to the neuron pMOS transistor m _p1 and neuron in the threshold 0.5 circuit 11 The drain of the nMOS transistor m _n1 ; the source of the nMOS transistor m _n8 and the drain of the nMOS transistor m _n9 are connected in series between the output signal terminal V _out and the power supply V ₁ ; the gate of the nMOS transistor m _n9 is connected to the threshold 2.5 The drains of the neuron pMOS transistor m _p5 and the neuron nMOS transistor m _n5 in the circuit 13; the gate of the pMOS transistor m _p9 and the gate of the nMOS transistor m _n8 are connected to the common binary CMOS inverter in the threshold 1.5 circuit 13 The drains of the middle pMOS transistor m _p4 and the nMOS transistor m _n4 .

In the above-mentioned four-valued signal transmission control circuit part 14, the pMOS transistor m _p7 is used to transmit the voltage V _DD of the power supply V _DD , the pMOS transistor m _p8 and pMOS transistor m _p9 are used to transmit the voltage V ₂ of the power supply V 2 , and the nMOS transistor m p7 is used to transmit the voltage V ₂ of the power supply V 2 . m _n8 and nMOS transistor m _n9 are used to transmit the voltage V ₁ of the power supply V ₁ , and nMOS transistor m _n7 is used to transmit the ground voltage 0. 0, V ₁ , V ₂ and V _DD correspond to four-valued logic signals (0, 1 , 2, 3).

Neuron MOS tube is a new type of device proposed in recent years with the characteristics of high functionality, low power consumption and flexible threshold control. People have carried out in-depth research on its application in many fields such as analog, digital and neural networks. . The processing technology of this device is fully compatible with the standard double-layer polysilicon CMOS process. The symbols of the n-type neuron MOS transistor and the p-type neuron MOS transistor and their capacitance models are shown in Figure 2. It has a plurality of input gates and a floating gate, wherein the floating gate is formed from a first layer of polysilicon, and the plurality of input control gates are formed from a second layer of polysilicon. The coupling between the input terminal and the floating gate is realized through capacitance. In the figure, V _F represents the voltage on the floating gate, V ₀ is the substrate voltage, and V ₁ , V ₂ , ..., V _n are the input signal voltages. C ₀ is the coupling capacitance between the floating gate and the substrate, which is mainly composed of the gate oxide layer capacitance C _ox , and C ₁ , C ₂ , ..., C _n are the coupling capacitances between each input gate and the floating gate. D and S in the figure represent the drain and source, respectively. The net charge _QF on the floating gate is given by:

${\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; ;</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

For n-channel floating gate MOS transistors, the substrate is grounded, so V ₀ =0. Assuming that the initial charge on the floating gate is zero, according to the law of conservation of charge, it can be obtained from the above formula:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; ;</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>\underset{\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

In the formula, w _i is the capacitance weight of the input terminal V _i . Let V _T V _T be the threshold voltage of the tube seen from the floating gate terminal, then the tube is turned on when V _F > V _T. It can be seen from formulas (2) and (3) that the neuron MOS transistor can weight and sum the input signals of each gate, and use the calculated summation result to control the "on" and "off" of the MOS transistor. Note that the weighted summation of all input signals it performs on the floating gate is done in voltage mode using capacitive coupling effects, which shows that it has better low power characteristics than current mode summing techniques. If V ₁ is used as the input terminal and the other input terminals are used as the control terminal, there are:

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V"\; filenames="HDA00001620202000011.png"\; state="\{\{state\}\}">V</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; ></span>\frac{\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; ;</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

In this way, the threshold voltage V ^* _t1 of the tube seen from the V ₁ terminal can be expressed as:

${{\mathrm{<span\; class="notranslate">\; V</span>}}^{<span\; class="notranslate">\; *</span>}}_{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="t"\; filenames="HDA00001620202000011.png"\; state="\{\{state\}\}">t</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

The above formula shows that there is no need to adjust V _T , as long as the proportional relationship between the coupling capacitors or the control terminal voltage V _i is changed, the threshold voltage of the floating gate MOS transistor relative to the input signal V ₁ can be changed, thereby controlling the conduction of the MOS transistor and deadline. This feature effectively overcomes the traditional voltage-type multi-valued logic circuit that requires additional ion implantation processes to realize MOS tubes with multiple threshold voltages or the need to use both enhancement-type and depletion-type MOS tubes to increase process complexity and Defects such as design cost. For p-channel floating gate MOS transistors, the substrate is usually connected to the highest voltage source in the circuit (such as V _DD ), so V ₀ =V _DD in formula (1), and formulas (2)-(5) need to be corrected accordingly.

The present invention utilizes the natural property that the threshold value of the neuron MOS transistor is easy to control, and proposes a new voltage-type four-value Schmidt circuit design scheme. There is no need to add a special circuit, and the regenerative feedback in the Schmidt circuit can be easily realized only by adding a gate input terminal to the p-type and n-type floating gate MOS transistors, which makes the designed circuit very simple. structure. The scheme of complementary floating gate MOS tube with independent floating gate structure is adopted to ensure that the circuit has the characteristics of low power consumption and high noise tolerance. Moreover, the hysteresis voltage can be adjusted conveniently by changing the capacitive coupling coefficient. By increasing the number of input terminals of the floating gate MOS transistor, it is very easy to access an external control signal, thereby changing the threshold voltage in the Schmidt circuit. The invention is completely based on the standard double-layer polysilicon CMOS technology. In addition to maintaining the characteristics of low power consumption of the voltage type circuit, the new design has the characteristics of simple circuit structure, easy adjustment of hysteresis voltage, and convenient and flexible control of threshold voltage. The present invention will be further described below in conjunction with the accompanying drawings and embodiments, and the purpose and effect of the present invention will become more obvious.

For the circuit shown in Figure 1, the threshold 0.5 circuit 11, the threshold 1.5 circuit 12 and the threshold 2.5 circuit 13 (that is, the threshold 0.5 inversion operation circuit and the threshold 0.5 operation circuit, the threshold 1.5 inversion operation circuit and the threshold The threshold voltage of the 1.5 operation circuit and the threshold 2.5 inverting operation circuit and the threshold 2.5 operation circuit) is given by the following formula:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>{{\mathrm{<span\; class="notranslate">\; V</span>}}^{<span\; class="notranslate">\; *</span>}}_{\mathrm{<span\; class="notranslate">\; tp</span>}}<span\; class="notranslate">\; +</span>{{\mathrm{<span\; class="notranslate">\; V</span>}}^{<span\; class="notranslate">\; *</span>}}_{\mathrm{<span\; class="notranslate">\; tn</span>}}\sqrt{{{\mathrm{<span\; class="notranslate">\; K</span>}}^{<span\; class="notranslate">\; *</span>}}_{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="HDA00001620202000011.png"\; state="\{\{state\}\}">R</figure-callout></span>}}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\sqrt{{{\mathrm{<span\; class="notranslate">\; K</span>}}^{<span\; class="notranslate">\; *</span>}}_{\mathrm{<span\; class="notranslate">\; R</span>}}}}<span\; class="notranslate">\; ;</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

in, ${K^{*}}_R=\frac{K_{\mathrm{no}}}{K_p}\frac{{w^2}_{\mathrm{ni}}}{{w^2}_p}$ . K _n and K _p are n-type and p-type floating gate MOS tubes respectively (n-type floating gate MOS tubes are neuron nMOS tube m _n1 , neuron nMOS tube m _n3 and neuron nMOS tube m _n5 ; p-type floating gate MOS tube The tube is the gain factor of the neuron pMOS tube m _p1 , the neuron pMOS tube m _p3 and the neuron pMOS tube m _p5 ), w _n(p)i is the capacitance weight of the input terminal of the n-type or p-type floating gate MOS tube, which is determined by Formula (3) is given. V ^* _tn and V ^* _tp are equivalent threshold voltages of the n-type and p-type floating gate MOS transistors relative to the input signal V _in , respectively. Taking K ^* _R = 1, formula (6) can be simplified as:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>{{\mathrm{<span\; class="notranslate">\; V</span>}}^{<span\; class="notranslate">\; *</span>}}_{\mathrm{<span\; class="notranslate">\; tp</span>}}<span\; class="notranslate">\; +</span>{{\mathrm{<span\; class="notranslate">\; V</span>}}^{<span\; class="notranslate">\; *</span>}}_{\mathrm{<span\; class="notranslate">\; tn</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

，V_0.5=0，其中

和V_0.5分别为阈0.5反相运算电路和阈0.5运算电路的输出电压。随着输入信号端信号V_in的上升，m_n1（即神经元nMOS管m_n1）渐渐导通，m_p1（即神经元pMOS管m_p1）渐渐截止，最终导致输出发生状态翻转。由式（7）可求得在输入信号上升时，电路发生状态翻转时的阈值电压为：For the threshold 0.5 inverting operation circuit and threshold 0.5 operation circuit shown in Figure 1, assuming V _in = 0 at the beginning (V _in is the input signal at the input signal terminal), then the n-type floating gate MOS transistor m _n1 (that is, the neuron The nMOS transistor m _n1 ) is cut off, the p-type floating gate MOS transistor m _p1 (that is, the neuron pMOS transistor m _p1 ) is turned on, and the output

, V _0.5 =0, where

and V _0.5 are the output voltages of the threshold 0.5 inverting operation circuit and the threshold 0.5 operation circuit respectively. As the signal V _in of the input signal terminal rises, m _n1 (that is, the neuron nMOS transistor m _n1 ) is gradually turned on, and m _p1 (that is, the neuron pMOS transistor m _p1 ) is gradually turned off, and finally the output state is reversed. From formula (7), it can be obtained that when the input signal rises, the threshold voltage when the circuit flips state is:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 0.5</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tn</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tp</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; ;</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

Among them, V _tn and V _tp are n-type and p-type floating gate MOS tubes respectively (n-type floating gate MOS tubes are neuron nMOS tube m _n1 , neuron nMOS tube m _n3 and neuron nMOS tube m _n5 ; p-type floating gate MOS tube The gate MOS transistor is the threshold voltage of the neuron pMOS transistor m _p1 , the neuron pMOS transistor m _p3 and the neuron pMOS transistor m _p5 ), w _n(p)i is the capacitance weight of the input terminal of the n-type or p-type floating gate MOS transistor , given by formula (3). V _TH(0.5+) is the high threshold voltage for threshold 0.5 in the four-valued Schmitt circuit. Once the output of the complementary threshold 0.5 inverter circuit composed of neuron pMOS transistor m _p1 and neuron nMOS transistor m _n1 is flipped to low level, the binary CMOS inverter composed of m _p2 and m _n2 will be made The output of the circuit goes high. The high-level output signal of the binary CMOS inverter is fed back to the gate input terminal of the previous stage circuit, which further accelerates the turn-on of the neuron nMOS transistor m _n1 and the cut-off of the neuron pMOS transistor m _p1 , thereby establishing regenerative feedback, As a result of this positive feedback, the output voltage of the threshold 0.5 inverting operation circuit quickly becomes , The output voltage of the threshold 0.5 operation circuit quickly changes to V _0.5 =V _DD . When the input signal terminal signal V _in falls from the high level, the circuit will undergo the opposite state transition. In the same way, the threshold voltage when the circuit flips during the falling process of the input signal terminal signal V _in can be obtained as:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 0.5</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tn</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tp</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

V _TH(0.5-) is the low threshold voltage relative to the threshold 0.5 in the four-valued Schmitt circuit. Take w _p1 =w _1n , w _p2 =w _n2 , w _p3 =w _n3 , and the hysteresis voltage can be obtained from equations (8) and (9) as $V_{h\left(0.5\right)}=2\frac{w_{\mathrm{no}3}}{w_{\mathrm{no}1}}{V}_{\mathrm{DD}}=2\frac{C_{\mathrm{no}3}}{C_{\mathrm{no}1}}{V}_{\mathrm{DD}}$ .

Similarly, for the threshold 1.5 circuit 12 shown in Figure 1, during the rising and falling process of the input signal, the threshold voltages when the circuit undergoes a state transition are respectively:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1.5</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tn</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V"\; filenames="HDA00001620202000011.png"\; state="\{\{state\}\}">V</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tp</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; ;</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 10</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1.5</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tn</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 6</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tp</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 6</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>$

Among them, V _TH(1.5+) is the high threshold voltage for threshold 1.5 in the four-value Schmitt circuit, and V _TH(1.5-) is the low threshold voltage for the threshold 1.5 in the four-value Schmitt circuit. For the threshold 2.5 circuit 13 shown in Figure 1, during the rising and falling process of the input signal, the threshold voltages when the circuit undergoes a state transition are respectively:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2.5</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tn</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tp</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 8</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; ;</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2.5</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tn</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 9</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; tp</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 8</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 9</span>}}}{{\mathrm{<span\; class="notranslate">\; w</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 13</span>}<span\; class="notranslate">\; )</span>$

Among them, V _TH(2.5+) is the high threshold voltage for the threshold 2.5 in the four-value Schmitt circuit, and V _TH(2.5-) is the low threshold voltage for the threshold 2.5 in the four-value Schmitt circuit. The above formulas (8)-(13) show that the three hysteresis voltages of the four-valued Schmidt circuit can be changed by changing the proportional relationship between the coupling capacitors or changing the control terminal voltage. Adopt TSMC 0.35μm double-layer polysilicon CMOS process parameters, and take the voltage V _DD =3.3V of the power supply V _DD , C _n(p)i :C _n(p)(i+1) :C _{n(p)(i+ 2)} =15:15:1, i∈(1,4,7), Figure 3 shows the voltage transmission characteristic curve obtained by HSPICE simulation. The error between the hysteresis voltage value obtained by simulation and the theoretical value is less than 5%. If take C _n(p)i :C _n(p)(i+1) :C _n(p)(i+2) =6:6:1,i∈(1,4,7), use the same process Parameters, the voltage transfer characteristic curve obtained by HSPICE simulation is shown in Figure 4. The simulation results show that the hysteresis voltage of the Schmitt trigger can be easily adjusted by changing the proportional coefficient of the coupling capacitance at the gate input terminal.

The invention discloses a voltage-type four-value Schmitt trigger circuit based on neuron MOS tubes. The circuit only needs six 3-input neuron MOS tubes (that is, neuron nMOS tube m _n1 , neuron nMOS tube m _n3 , neuron nMOS tube m _n5 , neuron pMOS tube m _p1 , neuron pMOS tube m _p3 , neuron pMOS tube m _p5 ) and 12 common MOS tubes (namely nMOS tube m _n2 , nMOS tube m _n4 , nMOS tube m _n6 , nMOS tube m _n7 , nMOS tube m _n8 , nMOS tube m _n9 , pMOS tube m _p2 , pMOS tube m _p4 , pMOS tube m _p6 , pMOS tube m _p7 , pMOS tube m _p8 , pMOS tube m _p9 ). Therefore, the circuit structure is very simple. Different from the complex process of using multi-level ion implantation technology to achieve multiple threshold voltages in the previous voltage-type multi-value Schmitt circuit design, the new design scheme is completely based on the standard double-layer polysilicon CMOS process, and the four-value Schmitt trigger The three hysteresis voltage values in the converter circuit can be adjusted by changing the capacitive coupling coefficient ratio. The scheme of complementary neuron MOS tube with independent floating gate structure is adopted to ensure that the circuit has the characteristics of low power consumption and high noise tolerance.

Finally, it should also be noted that what is listed above is only a specific embodiment of the present invention. Obviously, the present invention is not limited to the above embodiments, and many variations are possible. All deformations that can be directly derived or associated by those skilled in the art from the content disclosed in the present invention should be considered as the protection scope of the present invention.

Claims (2)

1. A voltage-type four-value Schmitt trigger circuit based on a neuron MOS tube; it is characterized in that: the voltage-type four-value Schmitt trigger circuit based on a neuron MOS tube includes a threshold 0.5 circuit (11) , a threshold 1.5 circuit (12), a threshold 2.5 circuit (13) and a four-valued signal transmission control circuit (14); The threshold 0.5 circuit (11) is respectively connected to a power supply V _DD , a power supply V ₂ and an input signal terminal V _in ; The threshold 1.5 circuit (12) is respectively connected with power supply V _DD , power supply V ₂ , power supply V ₁ and input signal terminal V _in ; The threshold 2.5 circuit (13) is respectively connected to a power supply V _DD , a power supply V ₁ and an input signal terminal V _in ; The four-valued signal transmission control circuit (14) is respectively connected to a power supply V _DD , a power supply V ₁ , a power supply V ₂ and an output signal terminal V _out ; The threshold 0.5 circuit (11), threshold 1.5 circuit (12) and threshold 2.5 circuit (13) are respectively connected to the four-value signal transmission control circuit (14). 2. A voltage-type four-value Schmitt trigger circuit based on a neuron MOS transistor according to claim 1, characterized in that: the threshold 0.5 circuit (11) includes a threshold 0.5 inversion with hysteresis characteristics Operation circuit and threshold 0.5 operation circuit; The threshold 0.5 inversion operation circuit and the threshold 0.5 operation circuit are composed of a complementary threshold 0.5 inverter, a common binary CMOS inverter and a feedback circuit; the complementary threshold 0.5 inverter includes a neuron pMOS tube m _p1 and neuron nMOS tube m _n1 ; the common binary CMOS inverter includes pMOS tube m _p2 and nMOS tube m _n2 ; The source of the neuron pMOS transistor m _p1 is connected to the power supply V _DD , the drain of the neuron pMOS transistor m _p1 is connected to the drain of the neuron nMOS transistor m _n1 , and the neuron pMOS transistor m _p1 has three gate input terminals, The coupling capacitances between the three input gates and the floating gate are capacitance C _p1 , capacitance C _p2 and capacitance C _p3 respectively; the source of the neuron nMOS transistor m _n1 is grounded, and the neuron nMOS transistor m _n1 has three gates At the input end, the coupling capacitances between the three input gates and the floating gate are capacitance C _n1 , capacitance C _n2 and capacitance C _n3 respectively; the source of the pMOS transistor m _p2 in the CMOS inverter is connected to the power supply V _DD , The drain of the pMOS transistor m _p2 is connected to the drain of the nMOS transistor m _n2 in the CMOS inverter, and the source of the nMOS transistor m _n2 is grounded; the gate of the pMOS transistor m _p2 in the CMOS inverter is connected to the gate of the nMOS transistor m _n2 The grid is connected as the input end of the CMOS inverter; the input end of the CMOS inverter is connected to the drain of the neuron pMOS transistor m _p1 and the drain of the neuron nMOS transistor m _n1 ; A grid input terminal of the neuron nMOS transistor m _n1 and a grid input terminal of the neuron pMOS transistor m _p1 are connected to the input signal terminal V _in ; the other grid input terminal of the neuron pMOS transistor m _p1 is connected to The power supply V _DD is connected, and the remaining input gate of the neuron pMOS transistor m _p1 is connected with the drain of the pMOS transistor m _p2 in the CMOS inverter and the drain of the nMOS transistor m _n2 to form a positive feedback circuit; the neuron The other gate input terminal of the nMOS transistor m _n1 is connected to the power supply V ₂ , and the remaining input gate of the neuron nMOS transistor m _n1 is connected to the drain of the pMOS transistor m _p2 and the drain of the nMOS transistor m _n2 in the CMOS inverter connected to form a positive feedback circuit; The threshold 1.5 circuit (12) includes a threshold 1.5 inversion operation circuit and a threshold 1.5 operation circuit with hysteresis characteristics; the threshold 1.5 inversion operation circuit and the threshold 1.5 operation circuit are composed of complementary threshold 1.5 inverters, common Composed of a binary CMOS inverter and a feedback circuit; the complementary threshold 1.5 inverter includes a neuron pMOS transistor m _p3 and a neuron nMOS transistor m _n3 ; the ordinary binary CMOS inverter includes pMOS transistors m _p4 and nMOS tube m _n4 ; The source of the neuron pMOS transistor m _p3 is connected to the power supply V _DD , the drain of the neuron pMOS transistor m _p3 is connected to the drain of the neuron nMOS transistor m _n3 , and the neuron pMOS transistor m _p3 has three gate input terminals. The coupling capacitances between each input gate and the floating gate are capacitance C _p4 , capacitance C _p5 and capacitance C _p6 respectively; the source of the neuron nMOS transistor m _n3 is grounded, and the neuron nMOS transistor m _n3 has three gate input terminals , the coupling capacitances between the three input gates and the floating gate are capacitance C _n4 , capacitance C _n5 and capacitance C _n6 respectively; the source of pMOS transistor m _p4 in the CMOS inverter is connected to the power supply V _DD , and the pMOS transistor The drain of m _p4 is connected to the drain of nMOS transistor m _n4 in the CMOS inverter, and the source of nMOS transistor m _n4 is grounded; the gate of pMOS transistor m _p4 in the CMOS inverter is connected to the gate of nMOS transistor m _n4 connected as the input end of the CMOS inverter; the input end of the CMOS inverter is connected with the drain of the neuron pMOS transistor m _p3 and the drain of the neuron nMOS transistor m _n3 ; the neuron A grid input terminal of the nMOS transistor m _n3 and a grid input terminal of the neuron pMOS transistor m _p3 are connected to the input signal terminal V _in ; the other grid input terminal of the neuron pMOS transistor m _p3 is connected to the power supply V _2. The remaining input gate of the neuron pMOS transistor m _p3 is connected to the drain of the pMOS transistor m _p4 in the CMOS inverter and the drain of the nMOS transistor m _n4 to form a positive feedback circuit; the neuron nMOS transistor m The other gate input terminal of _n3 is connected to the power supply V ₁ , and the remaining input gate of the neuron nMOS transistor m _n3 is connected to the drain of the pMOS transistor m _p4 in the CMOS inverter and the drain of the nMOS transistor m _n4 to form a positive feedback circuit; The threshold 2.5 circuit (13) includes a threshold 2.5 inversion operation circuit and a threshold 2.5 operation circuit with hysteresis characteristics; the threshold 2.5 inversion operation circuit and the threshold 2.5 operation circuit are composed of complementary threshold 2.5 inverters, common Composed of a binary CMOS inverter and a feedback circuit; the threshold 2.5 inverter includes a neuron pMOS transistor m _p5 and a neuron nMOS transistor m _n5 ; the common binary CMOS inverter includes a pMOS transistor m _p6 and an nMOS transistor m _n6 ; The source of the neuron pMOS transistor m _p5 is connected to the power supply V _DD , the drain of the neuron pMOS transistor m _p5 is connected to the drain of the neuron nMOS transistor m _n5 , and the neuron pMOS transistor m _p5 has three gate input terminals, The coupling capacitances between the three input gates and the floating gate are capacitance C _p7 , capacitance C _p8 and capacitance C _p9 respectively; the source of the neuron nMOS transistor m _n5 is grounded, and the neuron nMOS transistor m _n5 has three gates At the input end, the coupling capacitors between the three input gates and the floating gate are capacitor C _n7 , capacitor C _n8 and capacitor C _n9 respectively; the source of pMOS transistor m _p6 in the CMOS inverter is connected to the power supply V _DD , The drain of the pMOS transistor m _p6 is connected to the drain of the nMOS transistor m _n6 in the CMOS inverter, and the source of the nMOS transistor m _n6 is grounded; the gate of the pMOS transistor m _p6 in the CMOS inverter is connected to the gate of the nMOS transistor m _n6 The grid is connected as the input end of the CMOS inverter; the input end of the CMOS inverter is connected with the drain of the neuron pMOS transistor m _p5 and the drain of the neuron nMOS transistor m _n5 ; One gate input terminal of the neuron nMOS transistor m _n5 and one gate input terminal of the neuron pMOS transistor m _p5 are connected to the input signal terminal V _in , and the other gate input terminal of the neuron pMOS transistor m _p5 is connected to Power supply V ₁ , the remaining input gate of the neuron pMOS transistor m _p5 is connected with the drain of the pMOS transistor m _p6 in the CMOS inverter and the drain of the nMOS transistor m _n6 to form a positive feedback circuit; the neuron nMOS The other gate input terminal of the transistor m _n5 is grounded, and the remaining input gate of the neuron nMOS transistor m _n5 is connected to the drain of the pMOS transistor m _p6 and the drain of the nMOS transistor m _n6 in the CMOS inverter to form a positive feedback circuit; The four-value signal transmission control circuit (14) is composed of pMOS transistor m _p7 , pMOS transistor m _p8 , pMOS transistor m _p9 , nMOS transistor m _n7 , nMOS transistor m _n8 , and nMOS transistor m _n9 ; The source of the pMOS transistor m _p7 is connected to the power supply V _DD , the drain of the pMOS transistor m _p7 is connected to the drain of the nMOS transistor m _n7 , and the gate of the pMOS transistor m _p7 is connected to the threshold 0.5 circuit (11) The drains of the pMOS transistor m _p2 and the nMOS transistor m _n2 in the ordinary binary CMOS inverter; the source of the nMOS transistor m _n7 is grounded, and the gate of the nMOS transistor m _n7 is connected to the threshold 2.5 circuit (13) The drains of the pMOS transistor m _p6 and the nMOS transistor m _n6 in the ordinary binary CMOS inverter; the drain of the pMOS transistor m _p8 and the source of the pMOS transistor m _p9 are connected in series to the power supply V ₂ and the output signal terminal Between V _out , the gate of the pMOS transistor m _p8 is connected to the drain of the neuron pMOS transistor m _p1 and the neuron nMOS transistor m _n1 in the threshold 0.5 circuit (11); the source of the nMOS transistor m _n8 and The drain of the nMOS transistor m _n9 is connected in series between the output signal terminal V _out and the power supply V ₁ ; the gate of the nMOS transistor m _n9 is connected to the neuron pMOS transistor m _p5 and neuron in the threshold 2.5 circuit (13) The drain of the nMOS transistor m _n5 ; the gate of the pMOS transistor m _p9 and the gate of the nMOS transistor m _n8 are connected to the pMOS transistor in the common binary CMOS inverter in the threshold 1.5 circuit (13) m _p4 and the drain of nMOS tube m _n4 .

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