CN102623306B - Metal-multilayer insulator-metal capacitor, manufacture method for same and integrated circuit thereof - Google Patents
Metal-multilayer insulator-metal capacitor, manufacture method for same and integrated circuit thereof Download PDFInfo
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- CN102623306B CN102623306B CN201210081402.XA CN201210081402A CN102623306B CN 102623306 B CN102623306 B CN 102623306B CN 201210081402 A CN201210081402 A CN 201210081402A CN 102623306 B CN102623306 B CN 102623306B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 91
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 91
- 239000002184 metal Substances 0.000 title claims abstract description 91
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 74
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 72
- 238000000151 deposition Methods 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000000059 patterning Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 73
- 239000000377 silicon dioxide Substances 0.000 claims description 32
- 239000007789 gas Substances 0.000 claims description 30
- 230000008021 deposition Effects 0.000 claims description 27
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 26
- 239000012212 insulator Substances 0.000 claims description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 21
- 229910052760 oxygen Inorganic materials 0.000 claims description 21
- 239000001301 oxygen Substances 0.000 claims description 21
- 239000001272 nitrous oxide Substances 0.000 claims description 13
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 8
- 229910000077 silane Inorganic materials 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 6
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 6
- 230000004087 circulation Effects 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 3
- 239000001569 carbon dioxide Substances 0.000 claims description 3
- 229910002091 carbon monoxide Inorganic materials 0.000 claims description 3
- 239000000376 reactant Substances 0.000 claims description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 3
- -1 silicon nitrides Chemical class 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 39
- 239000011229 interlayer Substances 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
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Abstract
The invention provides a metal-multilayer insulator-metal capacitor, a manufacture method for the same and an integrated circuit thereof. The manufacture method for the metal-multilayer insulator-metal capacitor includes the steps: providing a silicon nitride layer; etching a non-capacitance region in the silicon nitride layer; filling a dielectric layer in the etched non-capacitance region; patterning the capacitor, namely patterning residual silicon nitride after etching, so that a plurality of silicon nitride columns are formed; depositing the silicon nitride, namely depositing the silicon nitride on the side walls of the silicon nitride columns; and filling metal, namely filling recesses of the patterned silicon nitride by metal. According to the metal-multilayer insulator-metal capacitor, capacitance of inter-layer capacitors and in-layer capacitors can be effectively enhanced, and electrical characteristics such as puncture voltage, leakage current and the like of the metal-multilayer insulator-metal capacitor and electrical uniformity among devices are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of capacitor manufacture method of metal-multilevel insulator-metal structure and metal-multilevel insulator-metal capacitor of making thus, in addition, the present invention relates to a kind of integrated circuit that has adopted metal-multilevel insulator-metal capacitor of making thus.
Background technology
Capacitor is the important composition unit in integrated circuit, is widely used in memory, microwave, and radio frequency, smart card, in the chips such as high pressure and filtering.The capacitor constructions widely adopting in chip is the metal-insulator-metal type (MIM) that is parallel to silicon chip substrate.Wherein metal be manufacture craft easily with metal interconnected the technique copper, aluminium etc. of compatibility mutually, insulator is the dielectric substance of the high-ks (k) such as silicon nitride, silica.The performance of improving high-k dielectric material is one of main method improving capacitor performance.
Plasma enhanced chemical vapor deposition method (PECVD, Plasma Enhanced Chemical Vapor Deposition) is because of the low thin film deposition being widely used in metal interconnected technique of its depositing temperature.High k value insulator silicon nitride can be shown below and utilize PECVD method under plasma ambient, to react generation by silane and ammonia.
High k value insulator oxide silicon can utilize PECVD method to be shown below under plasma ambient, to react generation by silane and nitrous oxide.
The stability of the silazine link in silicon nitride film (Si-N) is weaker than the silicon oxygen bond (Si-O) in silicon oxide film.Cause under high voltage, the leakage current of silicon nitride film capacitor is larger.Publication number a kind of method of improving aluminium-insulator-tantalum compound MIM capacitor performance that has been CN101783286A, the denomination of invention Introduction To Cn Patent that is " capacitor manufacture method that structure is metal-insulator-metal type ".By PECVD capping oxidation silicon layer on silicon nitride layer, improved the stability of associative key between insulator film Atom, thereby effectively improved the performance of this MIM capacitor.
But, along with the minimizing of chip size, and the demand of performance to large electric capacity, how under limited area, obtaining highdensity electric capacity becomes a problem having a great attraction.Along with the continuous progress of semiconductor integrated circuit manufacturing technology, performance is also accompanied by device miniaturization, microminiaturized process when constantly promoting.More and more advanced processing procedure, requires in as far as possible little region, to realize device as much as possible, obtains high as far as possible performance.Metal-oxide-metal (MOM) perpendicular to silicon chip substrate is a kind of method that realizes larger electric capacity in less chip area.Oxide wherein is not only confined to silica, comprises in actual applications the dielectric substance of the high-ks such as silicon nitride (k).The compatibility of MOM capacitor fabrication technique and metal interconnected technique is relatively good, and outer company of capacitor two-stage can synchronously realize with metal interconnected technique.
The silicon nitride film and the interior meeting of the silicon oxide film residual a large amount of si-h bond (Si-H) that utilize PECVD method to make.Si-h bond makes to have more electric charge in insulator film, has reduced the performance of metal-insulator-metal type MOM capacitor.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, the integrated circuit that metal-multilevel insulator-metal capacitor manufacture method of each electrical characteristics such as a kind of puncture voltage that can improve metal-multilevel insulator-metal capacitor, leakage current and metal-multilevel insulator-metal capacitor of making is thus provided and has adopted metal-multilevel insulator-metal capacitor of making thus.
According to a first aspect of the invention, provide a kind of metal-multilevel insulator-metal capacitor manufacture method, it comprises: silicon nitride layer provides step, for silicon nitride layer is provided; Noncapacitive district etch step, in silicon nitride layer etching noncapacitive district; Dielectric layer filling step, for the noncapacitive district filled media floor etching; Capacitor pattern forms step, for making the remaining silicon nitride pattern of etching, thereby forms a plurality of silicon nitride posts; Silica deposition step, for cvd silicon oxide on the sidewall at silicon nitride post; And metal filled step, for the recess that utilizes the silicon nitride of metal filled patterning to form.
Preferably, described metal-multilevel insulator-metal capacitor manufacture method also comprises: repeating described silicon nitride layer provides step, described noncapacitive district etch step, described dielectric layer filling step, described capacitor pattern to form step, described silica deposition step, described metallic channel formation step and described metal filled step.
Preferably, at described silicon nitride layer, provide in step, the two step endless form deposited silicon nitrides of processing with deposited silicon nitride and oxygen-containing gas by PECVD form silicon nitride layer.
Preferably, at described capacitor pattern, form in step, by photoetching be etched in the remaining silicon nitride of etching and form the figure of capacitor, and utilize anisotropic etching to carry out attenuate finally to form silicon nitride post.
Preferably, in described silica deposition step, the two step endless form cvd silicon oxides of processing with cvd silicon oxide and oxygen-containing gas by PECVD, and utilize anisotropic etching to remove the silica of horizontal direction, form thus the multilevel insulator that comprises silica-silicon-nitride and silicon oxide.
Preferably, the oxygen-containing gas in silica deposition step comprises one or more in nitric oxide, nitrous oxide, carbon monoxide and carbon dioxide.
Preferably, in silica deposition step, oxygen-containing gas in silica deposition step comprises nitrous oxide, and the flow of reactant gas silane is between 25sccm to 600sccm, the flow of reacting gas nitrous oxide is between 9000sccm to 20000sccm, the flow-rate ratio of silane and nitrous oxide is between 1:15 to 1:800, and rate of film build is between 10 nm/minute to 5000 nm/minute.
Preferably, in the two step circulations that the deposited silicon nitride in silica deposition step and oxygen-containing gas are processed, the gas flow that oxygen-containing gas is processed is between 2000 to 6000sccm, and treatment temperature is between 300 to 600 degrees Celsius.
Preferably, in the two step circulations that the deposited silicon nitride in silica deposition step and oxygen-containing gas are processed, each silicon nitride deposit thickness is 1 nanometer to 10 nanometer.
Preferably, described metal-multilevel insulator-metal capacitor manufacture method also comprises: metallic channel forms step, for be formed for forming the metallic channel of wire at dielectric layer; And, wherein, in described metal filled step, also utilize metal filled metallic channel to form conductor part.
According to a second aspect of the invention, provide a kind of basis metal-multilevel insulator-metal capacitor that described according to a first aspect of the invention metal-multilevel insulator-metal capacitor manufacture method is made.
According to a third aspect of the invention we, provide a kind of integrated circuit of described metal-multilevel insulator-metal capacitor according to a second aspect of the invention that adopted.
According to the present invention, can effectively improve the electric capacity of interlayer and layer inner capacitor, each electrical characteristics such as the puncture voltage of metal-multilevel insulator-metal capacitor that improvement comprises multiple layer metal and multilevel insulator, leakage current, and the electricity uniformity between each device.More particularly, by adopting according to metal-multilevel insulator of the present invention-metal capacitor manufacture method, can effectively reduce the si-h bond (Si-H) remaining in silicon nitride film, improve the performance of metal-silicon nitride-metal capacitor device; Thereby, effectively improve each electrical characteristics such as puncture voltage, leakage current of metal-multilevel insulator-metal capacitor.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily to the present invention, there is more complete understanding and more easily understand its advantage of following and feature, wherein:
The silicon nitride layer that Fig. 1 schematically shows the metal-multilevel insulator-metal capacitor manufacture method according to the embodiment of the present invention provides the diagram of step.
Fig. 2 schematically shows the diagram of the noncapacitive district etch step of the metal-multilevel insulator-metal capacitor manufacture method according to the embodiment of the present invention.
Fig. 3 schematically shows the diagram of the dielectric layer filling step of the metal-multilevel insulator-metal capacitor manufacture method according to the embodiment of the present invention.
Fig. 4 schematically shows the diagram of the capacitor pattern formation step of the metal-multilevel insulator-metal capacitor manufacture method according to the embodiment of the present invention.
Fig. 5 schematically shows the diagram of the silica deposition step of the metal-multilevel insulator-metal capacitor manufacture method according to the embodiment of the present invention.
Fig. 6 schematically shows the diagram of the metallic channel formation step of the metal-multilevel insulator-metal capacitor manufacture method according to the embodiment of the present invention.
Fig. 7 schematically shows the diagram of the metal filled step of the metal-multilevel insulator-metal capacitor manufacture method according to the embodiment of the present invention.
Fig. 8 schematically shows the diagram of the metal-multilevel insulator-metal capacitor obtaining after step 1 before the repetition of the metal-multilevel insulator-metal capacitor manufacture method according to the embodiment of the present invention time.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 1 to Fig. 8 schematically shows each step of the metal-multilevel insulator-metal capacitor manufacture method according to the embodiment of the present invention.As shown in Figures 1 to 8, according to the metal-multilevel insulator of the embodiment of the present invention-metal capacitor manufacture method, comprise:
Silicon nitride layer provides step, for silicon nitride layer 22 is provided; For example, in specific embodiment, can utilize PECVD to deposit the film of high k value silicon nitride layer 22; More particularly, the two step endless form that the deposition of silicon nitride layer 22 can adopt deposited silicon nitride and oxygen-containing gas to process complete, and resulting structure as shown in Figure 1.
Noncapacitive district etch step, in silicon nitride layer 22 etching noncapacitive districts 222; For example, in specific embodiment, can remove the noncapacitive district 222 in non-silicon nitride layer 22 by photoetching and etching, resulting structure as shown in Figure 2.
Dielectric layer filling step, for the noncapacitive district 222 filled media floor 1 etching; In specific embodiment, can deposit low k value dielectric layer 1, and remove unnecessary low k value dielectric layer 1 with cmp; Thus, form the mixed layer of low k value dielectric layer 1 and silicon nitride 22, resulting structure as shown in Figure 3.
Capacitor pattern forms step, for making remaining silicon nitride 22 patternings of etching, thereby forms a plurality of silicon nitride posts 221; For example, in specific embodiment, can and be etched in the remaining silicon nitride 22 of etching by photoetching and form the figure of capacitor, and utilize anisotropic etching to carry out attenuate finally to form silicon nitride post 221, resulting structure as shown in Figure 4.As shown in Figure 4, for example, the quantity of a plurality of silicon nitride posts 221 is 2; Certainly in other embodiments, can be also a plurality of silicon nitride posts 221 of other quantity.
Silica deposition step, for cvd silicon oxide 21 on the sidewall at silicon nitride post 221; For example, in specific embodiment, the two step endless form cvd silicon oxides 21 that can process with cvd silicon oxide and oxygen-containing gas by PECVD, and utilize anisotropic etching to remove the silica of horizontal direction, form thus the multilevel insulator 2 that comprises silica 21-silicon nitride 22-silica 21, resulting structure as shown in Figure 5.
Preferably, also carry out metallic channel and form step, for be formed for forming the metallic channel 12 of wire at dielectric layer 1, resulting structure as shown in Figure 6.
Metal filled step, for the recess 3 that utilizes the silicon nitride 22 of metal filled patterning to form; Preferably, in the situation that having formed metallic channel, also utilize metal filled metallic channel to form conductor part 31, resulting structure as shown in Figure 7.
After this, preferably, silicon nitride layer before repeating provides step, noncapacitive district etch step, dielectric layer filling step, capacitor pattern to form step, silica deposition step, metallic channel formation step and metal filled step respectively once, and the metal-multilevel insulator-metal capacitor structure obtaining afterwards as shown in Figure 8.
Be understandable that, Fig. 8 only shows and repeats the structure of above-mentioned each step after once, in fact, can repeatedly repeat above-mentioned silicon nitride layer provides step, noncapacitive district etch step, dielectric layer filling step, capacitor pattern to form step, silica deposition step, metallic channel formation step and metal filled step, thereby forms a plurality of stacked metal-multilevel insulator-metal capacitor structures.
After this, the processing step such as diffusion impervious layer deposition, copper plating, copper metal layer cmp that can simultaneously carry out the copper of copper wiring technique on low k value dielectric layer 1 and high k value multilevel insulator 2, completes the follow-up making of copper-connection and metal-multilevel insulator-metal capacitor.
Preferably, in a concrete preferred embodiment, the oxygen-containing gas in silica deposition step comprises one or more in nitric oxide, nitrous oxide, carbon monoxide and carbon dioxide.
Preferably, in a concrete preferred embodiment, in the two step circulations that the deposited silicon nitride in silica deposition step and oxygen-containing gas are processed, each silicon nitride deposit thickness is 1 nanometer to 10 nanometer.
Preferably, in a concrete preferred embodiment, in the two step circulations that deposited silicon nitride in silica deposition step and oxygen-containing gas are processed, the gas flow that oxygen-containing gas is processed is between 2000 to 6000sccm, and treatment temperature is between 300 to 600 degrees Celsius.
Preferably, in a concrete preferred embodiment, in silica deposition step, oxygen-containing gas in silica deposition step comprises nitrous oxide, and the flow of reactant gas silane is between 25sccm to 600sccm, the flow of reacting gas nitrous oxide is between 9000sccm to 20000sccm, and the flow-rate ratio of silane and nitrous oxide is between 1:15 to 1:800, and rate of film build is between 10 nm/minute to 5000 nm/minute.
Preferably, in a concrete preferred embodiment, the live width of multilevel insulator 2 is the required insulation thickness of capacitor.
By adopting according to the metal-multilevel insulator of the embodiment of the present invention-metal capacitor manufacture method, can effectively reduce the si-h bond (Si-H) remaining in silicon nitride film, improved the performance of metal-silicon nitride-metal capacitor device.Thereby, effectively improve each electrical characteristics such as puncture voltage, leakage current of metal-multilevel insulator-metal capacitor.
According to another preferred embodiment of the invention, the present invention also provides a kind of metal-multilevel insulator-metal capacitor of making according to above-mentioned metal-multilevel insulator-metal capacitor.
According to another preferred embodiment of the invention, the present invention also provides a kind of integrated circuit that adopts above-mentioned metal-multilevel insulator-metal capacitor.
In a word, according to the metal-multilevel insulator of the embodiment of the present invention-metal capacitor manufacture method, metal-multilevel insulator-metal capacitor of making according to above-mentioned metal-multilevel insulator-metal capacitor and adopted the integrated circuit of above-mentioned metal-multilevel insulator-metal capacitor at least also to there is following technique effect:
1) by improving dielectric k value of interlayer and layer inner capacitor, effectively improve the electric capacity of interlayer and layer inner capacitor.
2) by improving the performance of high k value insulator, effectively improve each electrical characteristics such as puncture voltage, leakage current of MIM capacitor, and the electricity uniformity between each device.
Be understandable that, although the present invention with preferred embodiment disclosure as above, yet above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (12)
1. metal-multilevel insulator-metal capacitor manufacture method, is characterized in that comprising:
Silicon nitride layer provides step, for silicon nitride layer is provided;
Noncapacitive district etch step, in silicon nitride layer etching noncapacitive district;
Dielectric layer filling step, for the noncapacitive district filled media floor etching;
Capacitor pattern forms step, for making the remaining silicon nitride pattern of etching, thereby forms a plurality of silicon nitride posts;
Silica deposition step, for cvd silicon oxide on the sidewall at silicon nitride post;
Metal filled step, for the recess that utilizes the silicon nitride of metal filled patterning to form; And
Metallic channel forms step, for be formed for forming the metallic channel of wire at dielectric layer; And in described metal filled step, also utilize metal filled metallic channel to form conductor part.
2. metal-multilevel insulator according to claim 1-metal capacitor manufacture method, characterized by further comprising described in repetition silicon nitride layer provides step, described noncapacitive district etch step, described dielectric layer filling step, described capacitor pattern to form step, described silica deposition step, described metallic channel to form step and described metal filled step.
3. metal-multilevel insulator according to claim 1 and 2-metal capacitor manufacture method, it is characterized in that, at described silicon nitride layer, provide in step, the two step endless form deposited silicon nitrides of processing with deposited silicon nitride and oxygen-containing gas by PECVD form silicon nitride layer.
4. metal-multilevel insulator according to claim 1 and 2-metal capacitor manufacture method, it is characterized in that, at described capacitor pattern, form in step, by photoetching be etched in the remaining silicon nitride of etching and form the figure of capacitor, and utilize anisotropic etching to carry out attenuate finally to form silicon nitride post.
5. metal-multilevel insulator according to claim 1 and 2-metal capacitor manufacture method, it is characterized in that, in described silica deposition step, the two step endless form cvd silicon oxides of processing with cvd silicon oxide and oxygen-containing gas by PECVD, and utilize anisotropic etching to remove the silica of horizontal direction, form thus the multilevel insulator that comprises silica-silicon-nitride and silicon oxide.
6. metal-multilevel insulator according to claim 1 and 2-metal capacitor manufacture method, it is characterized in that, the oxygen-containing gas in silica deposition step comprises one or more in nitric oxide, nitrous oxide, carbon monoxide and carbon dioxide.
7. metal-multilevel insulator according to claim 6-metal capacitor manufacture method, it is characterized in that, in silica deposition step, oxygen-containing gas in silica deposition step comprises nitrous oxide, and the flow of reactant gas silane is between 25sccm to 600sccm, the flow of reacting gas nitrous oxide is between 9000sccm to 20000sccm, the flow-rate ratio of silane and nitrous oxide is between 1:15 to 1:800, and rate of film build is between 10 nm/minute to 5000 nm/minute.
8. metal-multilevel insulator according to claim 1 and 2-metal capacitor manufacture method, it is characterized in that, in the two step circulations that deposited silicon nitride in silica deposition step and oxygen-containing gas are processed, the gas flow that oxygen-containing gas is processed is between 2000 to 6000sccm, and treatment temperature is between 300 to 600 degrees Celsius.
9. metal-multilevel insulator according to claim 1 and 2-metal capacitor manufacture method, it is characterized in that, in the two step circulations that deposited silicon nitride in silica deposition step and oxygen-containing gas are processed, each silicon nitride deposit thickness is 1 nanometer to 10 nanometer.
10. metal-multilevel insulator according to claim 1 and 2-metal capacitor manufacture method, characterized by further comprising metallic channel and forms step, for be formed for forming the metallic channel of wire at dielectric layer; And, wherein, in described metal filled step, also utilize metal filled metallic channel to form conductor part.
11. 1 kinds of metal-multilevel insulator-metal capacitors of making according to the metal-multilevel insulator described in claim 1 to 10-metal capacitor manufacture method.
12. 1 kinds of integrated circuits that adopt metal-multilevel insulator-metal capacitor according to claim 11.
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| CN105336574B (en) * | 2014-08-07 | 2020-12-25 | 无锡华润上华科技有限公司 | Manufacturing method of silicon nitride film and MIM capacitor |
| KR102775528B1 (en) * | 2021-03-02 | 2025-03-07 | 삼성전자주식회사 | Storage controller redirecting a write operation and operating method thereof |
| CN116133385A (en) * | 2021-08-30 | 2023-05-16 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| US12120863B2 (en) | 2021-08-30 | 2024-10-15 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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| US7569460B2 (en) * | 2006-08-25 | 2009-08-04 | Promos Technologies Inc. | Capacitor structure and method for preparing the same |
| CN102339832A (en) * | 2010-07-20 | 2012-02-01 | 海力士半导体有限公司 | Pillar capacitor for semiconductor device and manufacturing method thereof |
| CN102386064A (en) * | 2011-11-30 | 2012-03-21 | 上海华力微电子有限公司 | Manufacturing method of metal-oxide-metal capacitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7569460B2 (en) * | 2006-08-25 | 2009-08-04 | Promos Technologies Inc. | Capacitor structure and method for preparing the same |
| CN102339832A (en) * | 2010-07-20 | 2012-02-01 | 海力士半导体有限公司 | Pillar capacitor for semiconductor device and manufacturing method thereof |
| CN102386064A (en) * | 2011-11-30 | 2012-03-21 | 上海华力微电子有限公司 | Manufacturing method of metal-oxide-metal capacitor |
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