CN102592650B - High-speed low-power-consumption self-turn-off bit line sensitive amplifier - Google Patents

Abstract

A high-speed and low-power self-shutoff bit line sensitive amplifier, including a precharge module, a balance circuit module, an enable circuit module, a cross-coupled inverter module, an input circuit module, and a self-shutoff bit line module. The invention adopts an input The output separation structure, compared with the traditional shared input and output structure sense amplifier, avoids the discharge of the output capacitance to the bit line during the signal detection period, greatly reduces the time for forming a rated voltage difference between the bit lines, and reduces the sensitivity of the sense amplifier. The time delay improves the response speed of the sense amplifier; in addition, the pre-charge operation uses the two output terminals of the sense amplifier to be discharged to "0" through the pre-charge tube, and the pre-charge operation of the traditional sense amplifier is to pre-charge the output to VDD Compared with that, the pre-charge power consumption is saved, thereby reducing the total power consumption of the sense amplifier.

Description

A kind of high-speed low-power-consumption is from turn-offing bit line sense amplifier

Technical field

The present invention relates to a kind of high-speed low-power-consumption that is applied to semiconductor static RAM from turn-offing bit line sense amplifier.

Background technology

Storer, as the memory device of data and instruction, occupies very important position in System on Chip/SoC.The speed of storer depends primarily on reading the time of storer.The time of reading of storer mainly refers to the time of experiencing from the output that is input to data-signal of address signal, and generally the delay by address input buffer device, code translator, storage unit, sense amplifier and output buffer determines jointly.Therefore, reduce reading the time of storer, generally have two kinds of methods: the one, reduce to be input to the logical time delay of word line selection from address signal, because the form of the circuit such as inner code translator is relatively fixing, the time delay therefore reducing is in this way more limited; Another kind is to reduce to lead to from word line selection the time delay that data output is experienced, and this can realize by improving the design of sense amplifier.Visible, the design of high-performance sense amplifier is vital for the improvement of memory performance.

The object of sense amplifier work is the data in reading cells by amplifying small signal intensity between bit line.In particular, the effect of sense amplifier in storer is mainly reflected in aspect following three: be first amplification, it is enlarged into signal difference small between bit line logic level " 0 " and " 1 " of standard; Next is the electric discharge amplitude that reduces bit line, thereby reduces the power consumption that bit line discharges and recharges.Be finally by amplifying signal difference small between bit line and exporting complete logic level, avoid waiting for that the complete discharge off of bit line exports again, thereby reduce reading the time of storer.The work of sense amplifier is generally divided into two stages: the one, and preliminary filling, the 2nd, amplifies.

Sense amplifier is mainly divided into two kinds: current mode sense amplifier and voltage-type sense amplifier.Detect and amplifier bit line between Weak current poor be referred to as current mode sense amplifier, although current mode sense amplifier is not subject to the impact of bit-line load electric capacity, its structure is large compared with complicated, poor reliability, power consumption; Voltage-type sense amplifier detects and amplifies voltage difference small between bit line, although it is subject to the impact of bit-line load electric capacity, but it is simple in structure, stability is high, low in energy consumption, area is generally also little than current mode sense amplifier, so the sense amplifier adopting in current most of commercial static RAM is voltage-type sense amplifier.

As shown in Figure 1, in the voltage-type sense amplifier using in the prior art, when the given preliminary filling control signal PRE in outside, outside given enable signal SAEN are low level, sense amplifier is in pre-charge state, and its output terminal is precharged to VDD; When preliminary filling control signal PRE is high level, when enable signal SAEN is low level, sense amplifier is in detection signal state, because this sense amplifier is input and output sharing structure, so when detecting input signal, the output terminal that is charged in advance high level can be managed P3, P4 by PMOS the given bit line in outside is discharged, sense amplifier output terminal load capacitance is larger, amplification quantity is larger, this can extend the time that differential voltage between bit line reaches ratings, thereby increases the time delay of sense amplifier; The precharge operation of sense amplifier shown in Fig. 1 is that output terminal is charged to high level in advance in addition, and this can increase the power consumption of sense amplifier.

Summary of the invention

In order to solve, prior art sense amplifier output terminal meeting pairs of bit line during detecting input signal is discharged and precharge operation is that output terminal is charged to the problem that high level exists preliminary filling power consumption, the present invention proposes a kind of high-speed low-power-consumption and replaces traditional sense amplifier from turn-offing bit line sense amplifier, to reduce time delay and power consumption, improve the performance of sense amplifier.

For achieving the above object, the technical scheme that the present invention takes is: a kind of high-speed low-power-consumption is from turn-offing bit line sense amplifier, it is characterized in that, comprise pre-charge module, balancing circuit modules, enable circuits module, cross coupling inverter module, input circuit module and certainly turn-off bit line module, wherein:

Pre-charge module comprises NMOS pipe N1 and NMOS pipe N2, and NMOS pipe N1 is also connected outside given preliminary filling signal PRE with the gate interconnect of NMOS pipe N2, and the source electrode of NMOS pipe N1 and NMOS pipe N2 and substrate be ground connection GND all;

Balancing circuit modules comprises NMOS pipe N3, the grid of NMOS pipe N3 and the NMOS pipe grid of N1 and the grid of NMOS N2 link together, the drain electrode of NMOS pipe N3 is connected with the drain electrode of NMOS pipe N1, the source electrode of NMOS pipe N3 is connected with the drain electrode of NMOS pipe N2, the substrate ground connection GND of NMOS pipe N3;

Enable circuits module, comprises PMOS pipe P1, and the grid of PMOS pipe P1 connects outside given enable signal SANE, and the source electrode of PMOS pipe P1 is all connected with VDD with substrate;

Cross coupling inverter module comprises PMOS pipe P2, PMOS manages P3, NMOS manages N4, NMOS manages N5, the substrate of PMOS pipe P2 and PMOS pipe P3 all connects VDD, the source electrode of PMOS pipe P2 and PMOS pipe P3 links together and is connected with the drain electrode of PMOS pipe P1, the grid of PMOS pipe P2 and PMOS pipe P3 is connected with the grid of NMOS pipe N4 and NMOS pipe N5 respectively, the drain electrode of PMOS pipe P2 and PMOS pipe P3 is connected with the drain electrode of NMOS pipe N4 and NMOS pipe N5 respectively, the drain electrode of PMOS pipe P2, the grid of the grid of the drain electrode of NMOS pipe N4 and PMOS pipe P3 and NMOS pipe N5 links together, the grid of PMOS pipe P2, the drain electrode of the drain electrode of the grid of NMOS pipe N4 and PMOS pipe P3 and NMOS pipe N5 links together, substrate and the source grounding GND of NMOS pipe N4 and NMOS pipe N5,

Input circuit module comprises NMOS pipe N6, NMOS pipe N7, substrate and the source grounding of NMOS pipe N6 and NMOS pipe N7, the drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of NMOS pipe N6 and NMOS pipe N1, NMOS pipe N3, PMOS pipe P2 and NMOS pipe N4 links together, and the drain electrode of the drain electrode of the drain electrode of NMOS pipe N7 and NMOS pipe N2, the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together;

From turn-offing bit line module, comprise PMOS pipe P4, PMOS manages P5, NMOS pipe N8 and NMOS pipe N9, the gate interconnection of the grid of PMOS pipe P4 and NMOS pipe N8 is also managed the drain electrode of N1 with NMOS, the drain electrode of NMOS pipe N3, the drain electrode of NMOS pipe N6, the drain electrode of the drain electrode of PMOS pipe P2 and the NMOS pipe N4 connection that links together, the substrate of PMOS pipe P4 connects VDD, the source electrode of PMOS pipe P4 is connected with the outside position line BL that gives, the grid of the drain electrode of the drain electrode of PMOS pipe P4 and NMOS pipe N8 and NMOS pipe N6 links together, substrate and the source grounding GND of NMOS pipe N8, the gate interconnection of the grid of PMOS pipe P5 and NMOS pipe N9 is also managed the drain electrode of N2 with NMOS, the source electrode of NMOS pipe N3, the drain electrode of NMOS pipe N7, the drain electrode of the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together, the substrate of PMOS pipe P5 connects VDD, the source electrode of PMOS pipe P5 is connected with outside given another bit line BLB, the grid of the drain electrode of the drain electrode of PMOS pipe P5 and NMOS pipe N9 and NMOS pipe N7 links together, substrate and the source grounding GND of NMOS pipe N9.

Compare with existing sense amplifier, the present invention has the following advantages and is showing effect:

1) sense amplifier of the present invention adopts input and output isolating construction, compare with traditional shared input/output structure sense amplifier, avoided during detection signal, output capacitor pairs of bit line is discharged, greatly reduce and between bit line, form the poor time of rated voltage, thereby reduced the time delay of sense amplifier, improved the speed of sense amplifier;

2) precharge operation of sense amplifier of the present invention is that two output terminals of sense amplifier are arrived to " 0 " by preliminary filling tube discharge, output terminal to be charged to VDD in advance compare with traditional sense amplifier precharge operation, its precharge operation does not consume power consumption, and the amplifieroperation power consumption of its amplifieroperation power consumption and traditional sense amplifier is suitable, thereby the power consumption of sense amplifier of the present invention is reduced greatly;

Accompanying drawing explanation

Fig. 1 is prior art sensitive amplifier circuit schematic diagram;

Fig. 2 is the circuit theory diagrams of sense amplifier of the present invention;

Fig. 3 dotted line frame is partly the pre-charge module in Fig. 2;

Fig. 4 dotted line frame is partly the balancing circuit modules in Fig. 2;

Fig. 5 dotted line frame is partly the enable circuits module in Fig. 2;

Fig. 6 dotted line frame is partly the cross coupling inverter module in Fig. 2;

Fig. 7 dotted line frame is partly the input circuit module in Fig. 2;

Fig. 8 dotted line frame is partly the bit line of the shutoff certainly module in Fig. 2;

Fig. 9 is input signal, control signal and the signal output waveform figure of sense amplifier of the present invention.

Embodiment

Referring to Fig. 2-8, sense amplifier of the present invention comprises pre-charge module, balancing circuit modules, enable circuits module, cross coupling inverter module, input circuit module and certainly turn-offs bit line module, wherein:

Pre-charge module (Fig. 3 dotted line frame part), for by the output terminal of sense amplifier externally given enable signal SAEN discharge into " 0 " current potential before effectively, comprise two NMOS pipes N1, N2 by the given preliminary filling control signal PRE in outside, being controlled, NMOS pipe N1 is also connected outside given preliminary filling signal PRE with the gate interconnect of N2, and the source electrode of NMOS pipe N1 and N2 and substrate be ground connection GND all;

Balancing circuit modules (Fig. 4 dotted line frame part), for the current potential at effective forward horizontal stand two output terminals of the enable signal SAEN of sense amplifier, two output terminal current potentials are equated, it comprises the NMOS pipe N3 that outside given preliminary filling control signal PRE controls, the grid of NMOS pipe N3 and the NMOS pipe grid of N1 and the grid of NMOS N2 link together, the drain electrode of NMOS pipe N3 is connected with the drain electrode of NMOS pipe N1, the source electrode of NMOS pipe N3 is connected with the drain electrode of NMOS pipe N2, the substrate ground connection GND of NMOS pipe N3;

Enable circuits module (Fig. 5 dotted line frame part), for controlling opening and shutting off of whole sense amplifier, it comprises the PMOS pipe P1 that enable signal SAEN controls, and the grid of PMOS pipe P1 connects outside given enable signal SANE, and the source electrode of PMOS pipe P1 is all connected with VDD with substrate;

Cross coupling inverter module (Fig. 6 dotted line frame part), after opening at sense amplifier, amplify fast small bit line differential voltage, comprise PMOS pipe P2, P3, NMOS manages N4, N5, the substrate of PMOS pipe P2 and P3 all connects VDD, the source electrode of PMOS pipe P2 and P3 links together and is connected with the drain electrode of PMOS pipe P1, the grid of PMOS pipe P2 and PMOS pipe P3 is connected with the grid of NMOS pipe N4 and NMOS pipe N5 respectively, the drain electrode of PMOS pipe P2 and PMOS pipe P3 is connected with the drain electrode of NMOS pipe N4 and NMOS pipe N5 respectively, the drain electrode of PMOS pipe P2, the grid of the grid of the drain electrode of NMOS pipe N4 and PMOS pipe P3 and NMOS pipe N5 links together, the grid of PMOS pipe P2, the drain electrode of the drain electrode of the grid of NMOS pipe N4 and PMOS pipe P3 and NMOS pipe N5 links together, substrate and the source grounding GND of NMOS pipe N4 and NMOS pipe N5, PMOS manages P2, NMOS pipe N4 forms phase inverter INV1, PMOS manages P3, NMOS pipe N5 forms phase inverter INV2.

Input circuit module (Fig. 7 dotted line frame part), for detection of bit line differential voltage with after sense amplifier is opened, the output terminal of sense amplifier is discharged, comprise from the NMOS pipe N6 that turn-offs bit line module output voltage control, NMOS manages N7, substrate and the source grounding of NMOS pipe N6 and NMOS pipe N7, the drain electrode of the drain electrode of NMOS pipe N6 and NMOS pipe N1, the drain electrode of NMOS pipe N3, the drain electrode of the drain electrode of PMOS pipe P2 and NMOS pipe N4 links together, the drain electrode of the drain electrode of NMOS pipe N7 and NMOS pipe N2, the drain electrode of the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together.

From turn-offing bit line module (Fig. 8 dotted line frame part), for transmission and shutoff bit-line voltage, comprise PMOS pipe P4, PMOS manages P5, NMOS pipe N8 and NMOS pipe N9, the gate interconnection of the grid of PMOS pipe P4 and NMOS pipe N8 is also managed the drain electrode of N1 with NMOS, the drain electrode of NMOS pipe N3, the drain electrode of NMOS pipe N6, the drain electrode of the drain electrode of PMOS pipe P2 and the NMOS pipe N4 connection that links together, the substrate of PMOS pipe P4 connects VDD, the source electrode of PMOS pipe P4 is connected with the outside position line BL that gives, the grid of the drain electrode of the drain electrode of PMOS pipe P4 and NMOS pipe N8 and NMOS pipe N6 links together, substrate and the source grounding GND of NMOS pipe N8, the gate interconnection of the grid of PMOS pipe P5 and NMOS pipe N9 is also managed the drain electrode of N2 with NMOS, the source electrode of NMOS pipe N3, the drain electrode of NMOS pipe N7, the drain electrode of the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together, the substrate of PMOS pipe P5 connects VDD, the source electrode of PMOS pipe P5 is connected with outside given another bit line BLB, the grid of the drain electrode of the drain electrode of PMOS pipe P5 and NMOS pipe N9 and NMOS pipe N7 links together, substrate and the source grounding GND of NMOS pipe N9.Because the grid of PMOS pipe P4, NMOS pipe N8 and PMOS pipe P5, NMOS pipe N9 is controlled by the output signal of sense amplifier respectively, the source electrode of PMOS pipe P4, PMOS pipe P5 is connected to position line BL, BLB with outside respectively again, so when sense amplifier is during in pre-charge state, sense amplifier is output as " 0 ", two PMOS pipe P4, P5 conducting, bit-line voltage can be delivered to the grid of input circuit NMOS pipe N6, NMOS pipe N7; After sense amplifier is opened and is correctly exported, output terminal is that the meeting of high level is turn-offed the PMOS pipe being connected with bit line, thereby cut-out bit line is connected with input circuit module, complete from the process of turn-offing bit-line voltage, this process is controlled by internal signal completely, does not need additionally to introduce external control signal.

Principle of work of the present invention is as follows:

With reference to Fig. 9, the preliminary filling control signal PRE that sense amplifier of the present invention is outside given and outside given enable signal SAEN are same signal.When the given preliminary filling control signal PRE in outside, outside given enable signal SAEN are high level, sense amplifier turn-offs.Preliminary filling pipe NMOS pipe N1, NMOS pipe N2 opens, sense amplifier is in pre-charge state, and now its two output terminal is not to be charged to VDD, but discharges into " 0 " current potential by two NMOS pipe N1, N2, pre-charge process consumed energy not just like this, the average power consumption of pre-charge process is 0; In pre-charge process, balance pipe NMOS pipe N3 opens, for make two output terminals before sense amplifier carries out amplifieroperation in identical current potential; When output1, output2 two node potentials are " 0 ", from two PMOS pipe P4, P5 of breaking circuit module, to open completely, the outside voltage of position line BL, BLB of giving manages by PMOS the grid that P4, P5 are delivered to input pipe NMOS pipe N6, N7;

When the given preliminary filling control signal PRE in outside, outside given enable signal SAEN are low level, sense amplifier is started working.Enabling to manage PMOS pipe P1 opens, supply voltage VDD charges to two output terminals by PMOS pipe P1, P2, the PMOS pipe P3 pipe of opening, input pipe NMOS pipe N6, N7 open, sense amplifier two output terminals respectively by NMOS manage N6, N7 discharges, the rising of output1, output2 two node potentials or decline depend on that supply voltage VDD is to the charging rate of output terminal and the output terminal velocity of discharge over the ground.Incipient stage, PMOS pipe is in saturation region, and NMOS pipe is in linear zone, so charging current and discharge current are respectively:

$I_P=\frac{1}{2}\·{\mathrm{\μ}}_p\·C_{\mathrm{ox}}\·{\left(\frac{W}{L}\right)}_p\·{(V_{\mathrm{GS}}-V_{\mathrm{thp}})}^2$

$I_N={\mathrm{\μ}}_n\·C_{\mathrm{ox}}\·{\left(\frac{W}{L}\right)}_n\·[(V_{\mathrm{GS}}-V_{\mathrm{thn}})\·V_{\mathrm{DS}}-\frac{1}{2}{V}_{\mathrm{DS}}^2]$

Wherein, I _p, I _nbe respectively charging current and discharge current; m _p, m _nbe respectively the mobility of hole and electronics; C _oxelectric capacity for gate oxide;

be respectively the breadth length ratio in PMOS pipe and NMOS pipe trench road; V _gS, V _dSbe respectively the voltage difference between metal-oxide-semiconductor grid and source electrode, drain electrode and source electrode; V _thp, V _thnbe respectively the threshold voltage of PMOS pipe and NMOS pipe.

In the incipient stage, charging current is greater than discharge current, so the current potential of 2 of output1, output2 can rise, because outside, give the current potential of position line BL, BLB unequal, so the discharge current size of NMOS pipe N6, N7 is unequal, thereby the current potential ascending velocity of node output1, output2 is different, as shown in Figure 9, when outside to the current potential of position line BL higher than outside during to the current potential of position line BLB, the discharge current of NMOS pipe N6 is greater than the discharge current of NMOS pipe N7, thus node output1 current potential ascending velocity is less than node output2, as node output1, when output2 current potential rises to a certain degree, phase inverter INV1, the NMOS pipe N4 of INV2, N6 opens, positive feedback between cross coupling inverter forms, the current potential of node output1 can reduce rapidly, the current potential of node output2 can raise rapidly, while input pipe and the positive feedback of certainly turn-offing between bit line module also form: output2 current potential is higher, from the PMOS pipe P5 that turn-offs bit line module, turn-off, simultaneously, larger from the NMOS pipe N9 discharge current that turn-offs bit line module, the grid-control voltage of input pipe NMOS N7 is less, thereby the discharge current of NMOS pipe N7 is less, the current potential of node output2 is higher, when output2 current potential rises to a certain degree, PMOS pipe P5 turn-offs, and the grid of input pipe NMOS pipe N7 is cut off with outside being connected of position line BLB, thereby completes from turn-offing bit line operation.Owing to there being the existence of two positive-feedback circuit structures, so after sense amplifier is opened, sense amplifier output terminal is output complete logic level " 0 " and " 1 " rapidly.

When differential voltage between bit line is 350mV, sense amplifier of the present invention and existing sense amplifier time delay and the power consumption under 5 kinds of process corner contrasts as following table 1-table 5:

Table 1

Table 2

Table 3

Table 4

Table 5

Data from above table can find out, sense amplifier of the present invention is compared with prior art sense amplifier, and speed has promoted 4.1%～11.8%, and power consumption has promoted 41.8%～46.2%, therefore have speed and lower power consumption faster.

Claims (1)

1. high-speed low-power-consumption, from turn-offing a bit line sense amplifier, is characterized in that, comprise pre-charge module, balancing circuit modules, enable circuits module, cross coupling inverter module, input circuit module and certainly turn-off bit line module, wherein:

Pre-charge module comprises NMOS pipe N1 and NMOS pipe N2, and NMOS pipe N1 is also connected outside given preliminary filling signal PRE with the gate interconnect of NMOS pipe N2, and the source electrode of NMOS pipe N1 and NMOS pipe N2 and substrate be ground connection GND all;

Balancing circuit modules comprises NMOS pipe N3, the grid of NMOS pipe N3 and the NMOS pipe grid of N1 and the grid of NMOS N2 link together, the drain electrode of NMOS pipe N3 is connected with the drain electrode of NMOS pipe N1, the source electrode of NMOS pipe N3 is connected with the drain electrode of NMOS pipe N2, the substrate ground connection GND of NMOS pipe N3;

Enable circuits module, comprises PMOS pipe P1, and the grid of PMOS pipe P1 connects outside given enable signal SAEN, and the source electrode of PMOS pipe P1 is all connected with VDD with substrate;

Cross coupling inverter module comprises PMOS pipe P2, PMOS manages P3, NMOS manages N4, NMOS manages N5, the substrate of PMOS pipe P2 and PMOS pipe P3 all connects VDD, the source electrode of PMOS pipe P2 and PMOS pipe P3 links together and is connected with the drain electrode of PMOS pipe P1, the grid of PMOS pipe P2 and PMOS pipe P3 is connected with the grid of NMOS pipe N4 and NMOS pipe N5 respectively, the drain electrode of PMOS pipe P2 and PMOS pipe P3 is connected with the drain electrode of NMOS pipe N4 and NMOS pipe N5 respectively, the drain electrode of PMOS pipe P2, the grid of the grid of the drain electrode of NMOS pipe N4 and PMOS pipe P3 and NMOS pipe N5 links together, the grid of PMOS pipe P2, the drain electrode of the drain electrode of the grid of NMOS pipe N4 and PMOS pipe P3 and NMOS pipe N5 links together, substrate and the source grounding GND of NMOS pipe N4 and NMOS pipe N5,

Input circuit module comprises NMOS pipe N6, NMOS pipe N7, substrate and the source grounding of NMOS pipe N6 and NMOS pipe N7, the drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of NMOS pipe N6 and NMOS pipe N1, NMOS pipe N3, PMOS pipe P2 and NMOS pipe N4 links together, and the drain electrode of the drain electrode of the drain electrode of NMOS pipe N7 and NMOS pipe N2, the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together;

From turn-offing bit line module, comprise PMOS pipe P4, PMOS manages P5, NMOS pipe N8 and NMOS pipe N9, the gate interconnection of the grid of PMOS pipe P4 and NMOS pipe N8 is also managed the drain electrode of N1 with NMOS, the drain electrode of NMOS pipe N3, the drain electrode of NMOS pipe N6, the drain electrode of the drain electrode of PMOS pipe P2 and the NMOS pipe N4 connection that links together, the substrate of PMOS pipe P4 connects VDD, the source electrode of PMOS pipe P4 is connected with the outside position line BL that gives, the grid of the drain electrode of the drain electrode of PMOS pipe P4 and NMOS pipe N8 and NMOS pipe N6 links together, substrate and the source grounding GND of NMOS pipe N8, the gate interconnection of the grid of PMOS pipe P5 and NMOS pipe N9 is also managed the drain electrode of N2 with NMOS, the source electrode of NMOS pipe N3, the drain electrode of NMOS pipe N7, the drain electrode of the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together, the substrate of PMOS pipe P5 connects VDD, the source electrode of PMOS pipe P5 is connected with outside given another bit line BLB, the grid of the drain electrode of the drain electrode of PMOS pipe P5 and NMOS pipe N9 and NMOS pipe N7 links together, substrate and the source grounding GND of NMOS pipe N9.

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