CN104347100B - Sense amplifier - Google Patents
Sense amplifier Download PDFInfo
- Publication number
- CN104347100B CN104347100B CN201310314797.8A CN201310314797A CN104347100B CN 104347100 B CN104347100 B CN 104347100B CN 201310314797 A CN201310314797 A CN 201310314797A CN 104347100 B CN104347100 B CN 104347100B
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- nmos tube
- pmos
- drain electrode
- connects
- grid
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Abstract
The invention discloses a kind of sense amplifier, including：The drain electrode of first NMOS tube M1 connects the source electrode of the second NMOS tube M2 and the 3rd NMOS tube M3，The drain electrode of the second NMOS tube M2 and the 3rd NMOS tube M3 connects the drain electrode of the 4th NMOS tube M4 and the 5th NMOS tube M5 respectively，Second NMOS tube M2 and the 3rd NMOS tube M3 grid are connected，4th NMOS tube M4 and the 5th NMOS tube M5 grid are connected，4th NMOS tube M4 source electrode is connect the 6th NMOS tube M6 and drains and be grounded by memory element，The drain electrode of 5th NMOS tube M5 connects the drain electrode of the 7th NMOS tube M7 and the 8th NMOS tube M8 drains and passes through the first electric capacity P1 ground connection，8th NMOS tube M8 source electrode connects the drain electrode of the 9th NMOS tube M9，9th NMOS tube M9 source ground，Its grid connects control signal c.It is of the invention can reduce compared with existing sense amplifier 20% power consumption.
Description
Technical field
The present invention relates to IC manufacturing field, more particularly to a kind of sense amplifier.
Background technology
As shown in figure 1, existing sense amplifier, first needed M2M4 before reading action, M3M5 places branch road first fills
Electricity arrive same current potential, be then powered off M6M7 pipe, stop charge, open M1 pipe, due to memory element sonos cell electric current and
The reference current that M8 pipes are produced is inconsistent, and final out1 points and out2 point voltages separate.Complete M1 after reading action, M6, M7 shut-off
By out1, out2 current potentials are put into vgnd and wait next charging read operation.Pbias1, nbias1, nbias2 are used as bias voltage one
It is straight to provide.Operating process is to start a, and the current potential of b is vpwr, and M1M6M7 pipes are turned off, when b point current potentials are changed into vgnd from vpwr,
M6, M7 pipe is opened, and starts to charge M2M4 pipes place branch road and M3M5 places branch road, until out1 voltages are equal to out2 simultaneously substantially
Till stable.Then a point current potentials are changed into vgnd from vpwr, and b point current potentials are changed into vpwr from vgnd, and M1 pipes are opened, the shut-off of M6M7 pipes.
Due to the electric current of memory element sonos cell electric currents and M8 pipes it is inconsistent, the separate no longer phase of the voltage of final out1 and out2 points
Deng.By latch cicuit reading logical zero afterwards, 1, reading action is completed.A point current potentials are changed into vpwr, M1 shut-offs from vgnd.M2M4
Pipe place branch road and M3M5 pipes place branch road start to discharge until vgnd, wait next charging read procedure.In this process by
Need current potential to be charged to certain steady potential from vgnd, the main source of power consumption is exactly the process that this charges, and is made in charging
Into the waste of device power consumption.
The content of the invention
The technical problem to be solved in the present invention is to provide and a kind of the sensitive of power consumption can be reduced compared with existing sense amplifier
Amplifier.
For solve above-mentioned technical problem, the present invention sense amplifier, including：The drain electrode of first PMOS M1 meets the 2nd PMOS
The source electrode of pipe M2 and the 3rd PMOS M3, the drain electrode of the second PMOS M2 and the 3rd PMOS M3 connect respectively the first NMOS tube M4 and
The drain electrode of the second NMOS tube M5, the second PMOS M2 and the 3rd PMOS M3 grid are connected, the first NMOS tube M4 and the 2nd NMOS
Pipe M5 grids are connected, and the first NMOS tube M4 source electrode is connect the 4th PMOS M6 and drains and be grounded by memory element, the second NMOS tube
M5 source electrodes connect the drain electrode of the 5th PMOS M7 and the 3rd NMOS tube M8 drains and passes through the first electric capacity P1 ground connection, the 3rd NMOS tube M8 source
Pole connects the drain electrode of the 4th NMOS tube M9, and the 4th NMOS tube M9 source ground, its grid connect control signal c.
The present invention is turned off by increasing a switching tube M9 and control signal c and reads reference current after release
Road, no longer carries out discharge operation, and the current potential of branch road is maintained at the state after reading release, and the charging process of subsequent operation is just not
Again from vgnd, but start to charge up from higher current potential.Power consumption penalty caused by being reduced with this in charging process.
The principle of the invention is as follows：
Increase the switch that logic control signal c controls M9, pbias1, nbias1, nbias2 are carried always as bias voltage
For.Operating process, starts a, and the current potential of b is vpwr, M1M6M7 pipes shut-off, when b point current potentials are changed into vgnd, M6, M7 from vpwr
Pipe is opened, and starts to charge M2M4 pipes place branch road and M3M5 places branch road, until out1 voltages are equal to out2 basicly stable
Till.Then a point current potentials are changed into vgnd from vpwr, and b point current potentials are changed into vpwr from vgnd, and M1 pipes are opened, the shut-off of M6M7 pipes.Due to
The electric current of memory element sonos cell electric currents and M8 pipes is inconsistent, and the voltage of final out1 and out2 points is separately no longer equal.
By sensitive amplifier circuit reading logical zero afterwards, 1, reading action is completed.A point current potentials are changed into vpwr, M1 shut-offs from vgnd.c
Point current potential is changed into vgnd from vpwr, turns off M9, makes M3M5 pipes place branch road not have discharge path, at the end of maintaining read operation
Current potential.Next charging operations, out2 points current potential are no longer just vgnd, but a higher medium voltage, so as to reduce charging
The power consumption penalty of process, the present invention can reduce the power consumption of sense amplifier 20%.
Description of the drawings
The present invention is further detailed explanation with specific embodiment below in conjunction with the accompanying drawings：
Fig. 1 is a kind of existing sense amplifier.
Fig. 2 is the control sequential figure of Fig. 1 sense amplifiers.
Fig. 3 is the structural representation of the present invention.
Fig. 4 is the control sequential figure of the present invention.
Specific embodiment
As shown in figure 3, the sense amplifier of the present invention, including：The drain electrode of first PMOS M1 connects the second PMOS M2 and the
The source electrode of three PMOSs M3, the drain electrode of the second PMOS M2 and the 3rd PMOS M3 meet the first NMOS tube M4 and the 2nd NMOS respectively
The drain electrode of pipe M5, the second PMOS M2 and the 3rd PMOS M3 grid are connected, the first NMOS tube M4 and the second NMOS tube M5 grid
It is connected, the first NMOS tube M4 source electrode is connect the 4th PMOS M6 and drains and be grounded by memory element, and the second NMOS tube M5 source electrode connects
5th PMOS M7 drains and the 3rd NMOS tube M8 drains and passes through the first electric capacity P1 ground connection, and the 3rd NMOS tube M8 source electrode connects the 4th
NMOS tube M9 drains, and the 4th NMOS tube M9 source ground, its grid connect control signal c.
During present invention work, start a, the current potential of b is vpwr, M1M6M7 pipes shut-off, when b point current potentials are changed into from vpwr
Vgnd, M6, M7 pipe is opened, and starts to charge M2M4 pipes place branch road and M3M5 places branch road, until out1 voltages are equal to out2
And it is basicly stable till.Then a point current potentials are changed into vgnd from vpwr, and b point current potentials are changed into vpwr from vgnd, and M1 pipes are opened, M6M7
Pipe is turned off.Due to the electric current of memory element sonos cell electric currents and M8 pipes it is inconsistent, the voltage minute of final out1 and out2 points
Open no longer equal.By sensitive amplifier circuit reading logical zero afterwards, 1, reading action is completed.A point current potentials are changed into from vgnd
Vpwr, M1 are turned off.C point current potentials are changed into vgnd from vpwr, turn off M9, make M3M5 pipes place branch road not have discharge path, maintain
Current potential at the end of read operation.Next charging operations, out2 points current potential are no longer just vgnd, but a higher middle electricity
Pressure, so as to reduce the power consumption penalty of charging process.
The present invention has been described in detail above by specific embodiment and embodiment, but these not constitute it is right
The restriction of the present invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Enter, these also should be regarded as protection scope of the present invention.
Claims (1)
1. a kind of sense amplifier, is characterized in that, including：First PMOS (M1) drain electrode meets the second PMOS (M2) and the 3rd
The source electrode of PMOS (M3), the drain electrode of the second PMOS (M2) and the 3rd PMOS (M3) connect the first NMOS tube (M4) and respectively
The drain electrode of two NMOS tubes (M5), the second PMOS (M2) are connected with the 3rd PMOS (M3) grid, the first NMOS tube (M4) and
Two NMOS tubes (M5) grid is connected, and the first NMOS tube (M4) source electrode is connect the 4th PMOS (M6) and drains and connect by memory element
Ground, the second NMOS tube (M5) source electrode connects the drain electrode of the 5th PMOS (M7) and the 3rd NMOS tube (M8) drains and by the first electric capacity
(P1) it is grounded, the 3rd NMOS tube (M8) source electrode connects the drain electrode of the 4th NMOS tube (M9), the 4th NMOS tube (M9) source ground, its grid
Connect control signal (c).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310314797.8A CN104347100B (en) | 2013-07-24 | 2013-07-24 | Sense amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310314797.8A CN104347100B (en) | 2013-07-24 | 2013-07-24 | Sense amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104347100A CN104347100A (en) | 2015-02-11 |
| CN104347100B true CN104347100B (en) | 2017-03-29 |
Family
ID=52502550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310314797.8A Active CN104347100B (en) | 2013-07-24 | 2013-07-24 | Sense amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104347100B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6163486A (en) * | 1997-09-24 | 2000-12-19 | Oki Electric Industry Co., Ltd. | Output circuit of semiconductor memory device |
| CN102163451A (en) * | 2010-02-15 | 2011-08-24 | 索尼公司 | Nonvolatile semiconductor memory device |
| CN102592650A (en) * | 2012-02-17 | 2012-07-18 | 安徽大学 | High-speed low-power-consumption self-turn-off bit line sensitive amplifier |
-
2013
- 2013-07-24 CN CN201310314797.8A patent/CN104347100B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6163486A (en) * | 1997-09-24 | 2000-12-19 | Oki Electric Industry Co., Ltd. | Output circuit of semiconductor memory device |
| CN102163451A (en) * | 2010-02-15 | 2011-08-24 | 索尼公司 | Nonvolatile semiconductor memory device |
| CN102592650A (en) * | 2012-02-17 | 2012-07-18 | 安徽大学 | High-speed low-power-consumption self-turn-off bit line sensitive amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104347100A (en) | 2015-02-11 |
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