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CN102543968B - 三维立体堆叠芯片封装结构 - Google Patents

三维立体堆叠芯片封装结构 Download PDF

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CN102543968B
CN102543968B CN201110034039.1A CN201110034039A CN102543968B CN 102543968 B CN102543968 B CN 102543968B CN 201110034039 A CN201110034039 A CN 201110034039A CN 102543968 B CN102543968 B CN 102543968B
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黄昱玮
杨琮富
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Abstract

本发明公开一种三维立体芯片堆叠封装结构，该芯片堆叠封装结构至少包含具有坡度的一挡墙结构，位于载体上并紧靠堆叠芯片。通过该挡墙结构来帮助底胶填充。本发明通过整合挡墙结构至封装结构中，可以帮助底胶的填充完全并避免底胶填充时气泡或空隙残存，而可以提高封装结构接点可靠度。

Description

三维立体堆叠芯片封装结构
技术领域
本发明涉及一种封装结构，且特别是涉及一种堆叠芯片的封装结构。
背景技术
半导体产业新兴技术3DIC是指将芯片垂直重叠并以直通硅晶穿孔(through-silicon vias，TSV)技术来连接，该种方式旨在缩短芯片之间的导线、缩小元件尺寸并提高运作频宽。3DIC技术能有效增加产品效能、减低功耗、降低成本、缩小体积，并能整合异质IC，而帮助建构完整立体堆叠芯片架构。
3DIC使用直通硅晶穿孔连接IC间的电性提供了非常高密度的垂直堆叠，使得两管芯间距仅数十微米，随着焊球封装技术朝更精细方向发展，维持可靠性所带来的挑战也愈来愈大。更小的焊球间距意味着每个连接的表面积更小，相比较于采用更大焊球、具有更宽松间距的情况，这反过来会将机械应力集中到更小的面积上，衰退与热周期会对焊接点产生机械应力，如果不对封装/焊料接合之处进行恰当的工程处理，焊接点可能会断裂。
传统的芯片封装使用的解决方法为在表面粘着元件下使用底胶填充技术(underfill)，适当的底胶材料选择虽然可将IC与载板间的间隙填充，但堆叠的芯片如何能适当地点胶填充成为目前一大难题。
发明内容
本发明的目的在于提供一种堆叠芯片封装结构，以解决上述问题。
本发明提供一种堆叠芯片封装结构，该封装结构包括一基板、至少一芯片堆设置于该基板上、一挡墙结构位于该基板上，以及一底胶填充于该芯片堆相互堆叠的该些芯片间。该挡墙结构紧靠该芯片堆的至少一侧边，该挡墙结构具有至少一斜坡面，自该芯片堆中间高度以上延伸至该基板。
为让本发明的上述特征能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1是本发明的一实施例的一种堆叠芯片封装结构的立体示意图；
图2是本发明的一实施例的一种堆叠芯片封装单元结构的侧面示意图；
图3是本发明的另一实施例的堆叠芯片封装结构的部分立体示意图；
图4是本发明的又一实施例的堆叠芯片封装结构的部分立体示意图；
图5是本发明的另一实施例的堆叠芯片封装结构的部分立体示意图；
图6A-图6B是本发明的又一实施例的挡墙结构的立体示意图。
主要元件符号说明
10：堆叠芯片封装结构
100：基板
110：芯片
110A：芯片堆
120：凸块
130：底胶
200：挡墙结构
200A：梯形体部分
200B、200A’、200B’：三角形体部分
200S、200AS、200BS、200AS’、200BS’：斜坡面
200L：斜坡道
D1：第一方向
D2：第二方向
D3：第三方向
具体实施方式
本发明是关于整合式堆叠芯片封装单元结构与其相关制作工艺，使堆叠芯片各层间间隙均可充分被底胶填满，可保护并提高堆叠芯片各焊球接点的可靠度，减少机械应力与热应力集中在接点而造成断裂的情形。
本案说明书中所谓“芯片”包含所有目前电子或半导体技术领域中已知的芯片，较佳但不限于，薄化芯片、存储器芯片或高射频芯片。
图1是依照本发明的一实施例的一种堆叠芯片封装结构的立体示意图。
图2是依照本发明的一实施例的一种堆叠芯片封装单元结构的侧面示意图。
图3是依照本发明的另一实施例的堆叠芯片封装结构的立体示意图。
图1所示是填充底胶之前的封装结构10包括位于一基板100上的多个堆叠芯片110(图中显示四个芯片相互堆叠为一芯片堆110A，但实际芯片堆叠数目并不限为四)、位于芯片100之间的多数个凸块120与设置在基板100上的至少一具有坡度的挡墙结构200。多个芯片110堆叠设置在基板100上并以覆晶方式通过凸块120相互电连接。将芯片堆叠方向(亦即芯片的厚度方向)设为第一方向D1也是所谓垂直方向，而垂直于第一方向并沿着芯片110的一边延伸的方向设为第二方向D2，而垂直于第一、第二方向为第三方向D3。基板100例如是印刷电路板或具有一或多层线路的半导体基底，或者是材料为硅或为玻璃的载板(interposer)。
具有坡度的该挡墙结构200是位于堆叠芯片110的侧边、位于芯片堆110A之间并紧靠堆叠芯片110，该挡墙结构200为具有直角三角形侧面的三角柱体结构并至少具有一斜坡面200S，其斜坡面200S自堆叠芯片堆110A最上层沿着芯片一边(第二方向D2)斜向延伸至基板100，该斜坡面的坡度(倾斜度)是该挡墙结构200于第一方向D1的高度除以该挡墙结构200于第二方向D2延伸的长度。
由于该挡墙结构200的斜坡面200S自堆叠芯片堆110A最上层延伸至基板100，底胶填充灌注时利用此一斜坡面200S作为底胶流动通道，使底胶填充时可沿此斜坡面200S流动(底胶流动方向如箭头所示)。图2所示是填充底胶之后的封装结构10。沿着挡墙结构200的斜坡面200S流动的底胶130通过毛细作用填满堆叠芯片110间的间隙，而完成底胶填充。
此处，该挡墙结构200是位于堆叠芯片110的侧边并紧靠堆叠芯片110，但此领域者可理解实际制作上该挡墙结构与堆叠芯片间可能有细微空隙，并非为密合或密封状态。图示中所绘示挡墙结构200等高于堆叠芯片堆110A最上层的上表面，但是其高度只需高于或等于堆叠芯片堆110A最上层的芯片与其下芯片间的最上层间隙即可，故所谓此处「最上层」是包括最上层芯片与最上层间隙的高度范围。
图3仅显示出填充底胶之前的封装结构10的部分，虽然图中仅显示出一芯片堆110A以方便该挡墙结构200的描述，但实际的封装结构10可包括多个芯片堆110A。图3中该挡墙结构200为具有三角形侧面的三角柱体结构并具有两个斜坡面200S，其斜坡面200S自堆叠芯片堆110A最上层分别延伸至基板100。以挡墙结构200侧面为等腰三角形来举例，其斜坡面200S自堆叠芯片堆110A最上层分别沿着芯片一边(顺或逆着第二方向D2)斜向延伸至基板100，该斜坡面的坡度(倾斜度)是该挡墙结构200于第一方向D1的高度除以该挡墙结构200于第二方向D2延伸长度的一半。底胶填充灌注时利用此两斜坡面200S作为底胶流动通道，使底胶填充时可沿此两斜坡面200S流动(底胶流动方向如箭头所示)。挡墙结构200的斜坡面200S与水平面(定义为基板100表面100a)具有一夹角θ，该夹角θ介于0～90度间，依照挡墙结构的形状与堆叠芯片堆的高度而变化。
图4仅显示出填充底胶之前的封装结构10，包括一或多个芯片堆110A。图4中该挡墙结构200可分为相连的梯形体部分200A与三角形体部分200B，分别紧靠芯片堆110A的两侧边。其中梯形体部分200A为梯形侧面的立体结构并具有一个斜坡面200AS，而与其相连的三角形体部分200B为具有三角形侧面的三角柱体结构并具有一个斜坡面200BS。其斜坡面200AS自堆叠芯片堆110A最上层沿着芯片一边(第二方向D2)斜向延伸、转折并以斜坡面200BS沿着芯片另一边(第三方向D3)继续延伸至基板100。以挡墙结构200A/200B侧面为直角三角形来举例，两斜坡面200AS与200BS的坡度(倾斜度)可以不同或相同。底胶填充灌注时利用此相连的两斜坡面200AS/200BS作为底胶流动通道，使底胶填充时可沿此两斜坡面200AS/200BS流动(底胶流动方向如箭头所示)。
图5仅显示出填充底胶之前的封装结构10，其包括一或多个芯片堆110A。图5中该挡墙结构200可分为不相连的三角形体部分200A’与三角形体部分200B’，分别紧靠芯片堆110A的两侧边。其中三角形体部分200A’为三角形侧面的三角柱体结构并具有一个斜坡面200AS’，斜坡面200AS’自堆叠芯片堆110A最上层沿着芯片一边(第二方向D2)斜向延伸至基板100。与其分离的三角形体部分200B’为具有三角形侧面的另一三角柱体结构并具有一个斜坡面200BS’。其斜坡面200BS’自堆叠芯片堆110A的中层沿着芯片另一边(第三方向D3)斜向延伸至基板100。两斜坡面200AS’与200BS’的坡度(倾斜度)并不相同。底胶填充灌注时可选择性利用两斜坡面200AS’/200BS’的任一者作为底胶流动通道。例如，先选择斜坡面200BS’来填充下两层芯片间的间隙，而底胶填充时沿斜坡面200BS’流动(底胶流动方向如箭头所示)。后续，可以选择相同或不相同的底胶材料，将另一底胶沿斜坡面200AS’流动而填入上层芯片间的间隙中。
如此，可以针对不同功能芯片或不同尺寸芯片，来提供不同的底胶材料，得以提供更好的封装功能。
本案实施例中该挡墙结构紧靠堆叠芯片堆的至少一侧边或两侧边，但是，该挡墙结构当然也可以设计成紧靠堆叠芯片堆的三侧边或四侧边。同样地，本案实施例中该挡墙结构是设计具有斜坡面以帮助底胶填充，但是，也可以理解的是，该挡墙结构200也可以设计成具有阶梯式的斜坡道200L(如图6A-图6B所示)以类似于上述实施例的配置方式紧靠配置于堆叠芯片堆110A的侧边，而以相同机制来帮助底胶填充。
本案所示的封装结构或方法特别适用于使用直通硅晶穿孔连接芯片的堆叠封装架构，因为其管芯间距狭窄，而一般底胶填充方式难以封填完全，故使用本案的挡墙结构可以帮助底胶填充完全，而强化封装结构。
一般而言，底胶胶体的材料可为热固性高分子例如是环氧树脂、氰酸脂树脂以及压克力树脂等。而本案所用以形成挡墙结构200的材料可以是具有高摇变性(thixotropy)的胶材，例如是：高摇变性环氧树脂类，一般来说，当此类环氧树脂受到剪切力作用时，其粘度可降成原来的50％以上，待其剪切作用力停止，此环氧树脂随即回复为原来的粘度特性，如此即可归类为高摇变性环氧树脂。本案挡墙结构200的高摇变性胶材的粘度范围在100,000cps～1,300,000cps应高于底胶胶体材料的粘度，其范围在5000cps～25,000cps左右。
由于挡墙结构是以高摇变性的胶材形成，可以利用例如点胶(dispensing)或灌模(molding)方式来形成。而若利用点胶方式形成，可使用点胶机(dispenser)来快速量产制作，与现行制作工艺相容。
本案堆叠芯片封装结构若后续制作工艺需要进行单体化或切割时，因挡墙结构是以高摇变性的胶材形成，此一挡墙结构可同样被切割而不损及堆叠芯片堆的整体结构，当然也不至于损及封装结构或芯片接点。
本案使用高摇变性胶体进行制作挡墙结构，而且评估至少两种不同高摇变性的胶材，以测试点胶法形成挡墙结构的可行性，结果显示于表1。
表1、以不同针孔直径进行制作工艺所形成的挡墙结构比较
结果发现需通过选择适当的点胶针孔孔径，方能得到理想的挡墙形状。当点胶针孔孔径介于0.8～1.6mm时，其所形成的挡墙高度可介于0.5～1.5mm。点胶所形成的挡墙结构高度能大于1mm，甚至高至2mm。因此，点胶法所形成的挡墙结构确实足够高且可以稳定紧靠芯片堆侧面。
以上实施例提供一种堆叠芯片的封装结构，通过整合挡墙结构至封装结构中，可以帮助底胶的填充完全并避免底胶填充时气泡或空隙残存，而可以提高封装结构接点可靠度。
虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。

Claims (12)

1.一种堆叠芯片封装结构，包含：
至少一芯片堆设置于一基板上，该芯片堆至少包括两个芯片以一第一方向堆叠构装于该基板上；
挡墙结构，其位于该基板上，其中该挡墙结构紧靠该芯片堆的至少一侧边，该挡墙结构具有至少一斜坡面，自该芯片堆中间高度以上沿着该芯片堆的该侧边斜向延伸至该基板；以及
底胶，其填充于该芯片堆相互堆叠的该芯片间。
2.如权利要求1所述的堆叠芯片封装结构，其中该挡墙结构为具有一直角三角形侧面的一三角柱体结构，其具有一斜坡面。
3.如权利要求1所述的堆叠芯片封装结构，其中该挡墙结构为具有一等腰三角形侧面的一三角柱体结构，其具有两斜坡面。
4.如权利要求1所述的堆叠芯片封装结构，其中该挡墙结构包括一梯形体部分以及与该梯形体部分相连的一三角形体部分，该梯形体部分紧靠该芯片堆的一侧边并具有第一斜坡面，而该三角形体部分紧靠该芯片堆的另一侧边并具有第二斜坡面，该第一斜坡面与其相连的该第二斜坡面分别自该芯片堆中间高度以上沿着该芯片堆的相连的该侧边与该另一侧边斜向延伸至该基板。
5.如权利要求1所述的堆叠芯片封装结构，其中该挡墙结构包括第一三角形体部分与第二三角形体部分，该第一三角形体部分紧靠该芯片堆的一侧边并具有第一斜坡面，而该第二三角形体部分紧靠该芯片堆的另一侧边并具有第二斜坡面，该第一斜坡面自该芯片堆中间高度以上沿着该芯片堆的该侧边斜向延伸至该基板，而该第二斜坡面自该芯片堆中层沿着该芯片堆的该另一侧边斜向延伸至该基板。
6.如权利要求1所述的堆叠芯片封装结构，其中该挡墙结构位于两个芯片堆之间，同时紧靠该两个芯片堆。
7.如权利要求1所述的堆叠芯片封装结构，其中该基板可为半导体基底、载板或印刷电路板。
8.如权利要求1所述的堆叠芯片封装结构，其中该挡墙结构的材料包括高摇变性胶材，该高摇变性胶材的粘度高于该底胶材料的粘度。
9.如权利要求1所述的堆叠芯片封装结构，其中该挡墙结构还包括阶梯式的斜坡道。
10.如权利要求1所述的堆叠芯片封装结构，其中该芯片为薄化芯片、存储器芯片或高射频芯片。
11.如权利要求1所述的堆叠芯片封装结构，其中该芯片堆至少包括两芯片，其通过覆晶方式电连接并以该第一方向堆叠构装于该基板上。
12.如权利要求1所述的堆叠芯片封装结构，其中该挡墙结构自该芯片堆最上层延伸至该基板。
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