CN102543960A - Integrated circuit for testing - Google Patents
Integrated circuit for testing Download PDFInfo
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- CN102543960A CN102543960A CN2012100304474A CN201210030447A CN102543960A CN 102543960 A CN102543960 A CN 102543960A CN 2012100304474 A CN2012100304474 A CN 2012100304474A CN 201210030447 A CN201210030447 A CN 201210030447A CN 102543960 A CN102543960 A CN 102543960A
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- 238000012360 testing method Methods 0.000 title claims abstract description 34
- 239000000523 sample Substances 0.000 claims abstract description 15
- 238000001514 detection method Methods 0.000 claims description 52
- 238000003466 welding Methods 0.000 claims description 52
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The invention discloses an integrated circuit for testing. The integrated circuit is positioned in a scribe line area of a wafer and comprises a plurality of groups of testing pads, wherein different groups of testing pads are placed in a staggered mode; and an interval between two adjacent testing pads in each testing pad group is not less than the minimum interval of probes. Therefore, by placing different groups of testing pads in the staggered mode, the area special for the testing pads is reduced under the condition that the minimum interval of the probes is unchanged, the space of an actual circuit is enlarged, and the space utilization rate of the integrated circuit is improved.
Description
Technical field
The present invention relates to a kind of integrated circuit structure, particularly relate to a kind of testing IC that improves space availability ratio.
Background technology
Before wafer fabrication was accomplished back, cutting encapsulation, a kind of wafer acceptance commonly used tested that (WaferAcceptance Testing, method WAT) measure the rate of finished products of the semiconductor element on the wafer.The method does,, just has a plurality of being parallel to each other on the vertical Cutting Road (Scribe line) on the eyeglass at the tube core (die) of wafer on every side, and a plurality of feeler switchs (Testkey) can be provided especially.The probe (Probe) that these feeler switchs can come electricity to be connected to circuit external or detecting card (Probe card) via weld pad (Pad) again carries out test job, to monitor the quality of each stage process.Usually, the component structure that generally on tube core, forms mainly is to be used for participating in logical operation or memory function, and on Cutting Road, also can form similar component structure simultaneously, as the feeler switch of test-purpose.
In general, for guaranteeing the minimum pin spacing of detecting card probe, the spacing of the test point of the test circuit of Cutting Road is all bigger with respect to production technology.Because the test circuit of Cutting Road generally all is positioned under the detection welding pad, the spacing of detection welding pad is also all bigger, as shown in Figure 1 in the prior art.Because the spacing of detection welding pad (A, B, C) is bigger, then need more place to place test circuit, the area of side circuit has just diminished like this, causes the waste of lsi space.
In sum, can know that prior art exists because the testing weld pad spacing causes the problem of lsi space waste greatly, therefore, be necessary to propose improved technological means in fact, solve this problem.
Summary of the invention
For overcoming the problems referred to above of above-mentioned prior art; Main purpose of the present invention is to provide a kind of testing IC; Its under the constant situation of the minimum spacing that guarantees probe, will be not on the same group detection welding pad be staggeredly placed, the special-purpose area of detection welding pad is reduced; Thereby the space of side circuit is increased, improved the space availability ratio of integrated circuit.
For reaching above-mentioned and other purpose; The present invention provides a kind of testing IC; Be positioned at the Cutting Road district of wafer, this testing IC comprises many group detection welding pads, wherein; Detection welding pad is not staggeredly placed on the same group, and the spacing of the detection welding pad of each detection welding pad group is at least the minimum spacing of probe.
Further, be not equidistant on the same group between the detection welding pad of detection welding pad.
Further, not on the same group the spacing between the detection welding pad of detection welding pad be at least the minimum safe distance of integrated circuit.
Compared with prior art; A kind of testing IC of the present invention; Its through will be not on the same group detection welding pad be staggeredly placed, under the constant situation of the minimum spacing that guarantees probe, reduced the special-purpose area of detection welding pad; Thereby the space of side circuit is increased, improved the space availability ratio of integrated circuit.
Description of drawings
Fig. 1 is the structural representation of a kind of testing IC in the prior art;
Fig. 2 is the structural representation of one of a kind of testing IC of the present invention preferred embodiment;
Fig. 3 is the structural representation of another preferred embodiment of a kind of testing IC of the present invention.
Embodiment
Below through specific instantiation and accompanying drawings execution mode of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.The present invention also can implement or use through other different instantiation, and each item details in this specification also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.
Fig. 2 is the structural representation of first preferred embodiment of a kind of testing IC of the present invention.As shown in Figure 1, the present invention's testing IC is positioned at the Cutting Road district of wafer, and it comprises many group detection welding pad (Ai, Bi; Ci), detection welding pad is not staggeredly placed on the same group, and the spacing of every group of detection welding pad is at least the minimum spacing of probe, and the probe of detecting card is disposable to be pressed on the Ai/Bi/Ci detection welding pad; Ai+1/Bi+1/Ci+1 is another detection welding pad group, Ai and Ai+1, Bi and Bi+1; The spacing of Ci and Ci+1 is the minimum safe distance of integrated circuit, and test circuit still is placed under the detection welding pad, like this; Detection welding pad special-purpose area just little a lot, thereby the side circuit space is just more, the space availability ratio of integrated circuit increases.With the present invention's first preferred embodiment is example, and it comprises four groups of detection welding pads, and first group of detection welding pad is A1, B1, C1; Second group of detection welding pad is A2, B2, and C2, the 3rd group of detection welding pad is A3, B3; C3, the 4th group of detection welding pad is A4, B4, C4; Detection welding pad A2, A3, A4 are placed between A1 and the B1, and detection welding pad B2, B3, B4 are placed between B1 and the C1, and wherein, the spacing of detection welding pad A1/B1/C1 is at least the minimum spacing of probe; Detection welding pad A2/B2/C2 is also promptly like this, and detection welding pad A1/A2/A3/A4, B1/B2/B3/B4, the spacing of C1/C2/C3/C4 is at least the minimum safe distance of integrated circuit.
Certainly, what and on-fixed of detection welding pad group, how many present invention can rationally arranging detection welding pad according to test circuit.Fig. 3 is the structural representation of second preferred embodiment of a kind of testing IC of the present invention.In the present invention's second preferred embodiment, comprise two groups of detection welding pads, first group of detection welding pad is A1, B1; C1, second group of detection welding pad is A2, B2, C2; Between detection welding pad A2 was placed among A1 and the B1, between detection welding pad B2 was placed among B1 and the C1, same, the spacing of detection welding pad A1/B1/C1 was at least the minimum spacing of probe; And detection welding pad A1/A2, B1/B2, the spacing of C1/C2 is at least the minimum safe distance of integrated circuit.
What this need explain be, in preferred embodiment of the present invention, though not on the same group the distance between the detection welding pad be equidistantly, the present invention is as limit, equidistantly or the minimum safe distance that meets integrated circuit all can.
In sum, a kind of testing IC of the present invention, its through will be not on the same group detection welding pad be staggeredly placed; Under the constant situation of the minimum spacing that guarantees probe; Reduce the special-purpose area of detection welding pad, thereby the space of side circuit is increased, improved the space availability ratio of integrated circuit.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, rights protection scope of the present invention should be listed like claims.
Claims (3)
1. testing IC; Be positioned at the Cutting Road district of wafer, it is characterized in that: this testing IC comprises many group detection welding pads, wherein; Detection welding pad is not staggeredly placed on the same group, and the spacing of the detection welding pad of each detection welding pad group is at least the minimum spacing of probe.
2. testing IC as claimed in claim 1 is characterized in that: be not equidistantly on the same group between the detection welding pad of detection welding pad.
3. testing IC as claimed in claim 1 is characterized in that: the spacing between the detection welding pad of detection welding pad is not at least the minimum safe distance of integrated circuit on the same group.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100304474A CN102543960A (en) | 2012-02-10 | 2012-02-10 | Integrated circuit for testing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100304474A CN102543960A (en) | 2012-02-10 | 2012-02-10 | Integrated circuit for testing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102543960A true CN102543960A (en) | 2012-07-04 |
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| CN2012100304474A Pending CN102543960A (en) | 2012-02-10 | 2012-02-10 | Integrated circuit for testing |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449598A (en) * | 2016-09-19 | 2017-02-22 | 上海华虹宏力半导体制造有限公司 | Test device |
| CN106680547A (en) * | 2015-11-10 | 2017-05-17 | 上海和辉光电有限公司 | Test pad layout structure and electrical property test method |
| CN113270393A (en) * | 2021-05-12 | 2021-08-17 | 武汉新芯集成电路制造有限公司 | Test key structure and wafer stacking structure |
| CN113571498A (en) * | 2021-09-24 | 2021-10-29 | 晶芯成(北京)科技有限公司 | Semiconductor structure and test structure thereof |
| CN115210035A (en) * | 2020-03-05 | 2022-10-18 | 松下知识产权经营株式会社 | Weld bead appearance inspection device, weld bead appearance inspection method, program, and weld bead appearance inspection system |
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| CN1886665A (en) * | 2003-12-01 | 2006-12-27 | 皇家飞利浦电子股份有限公司 | A ground-signal-ground (GSG) test structure |
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2012
- 2012-02-10 CN CN2012100304474A patent/CN102543960A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106680547A (en) * | 2015-11-10 | 2017-05-17 | 上海和辉光电有限公司 | Test pad layout structure and electrical property test method |
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| CN115210035A (en) * | 2020-03-05 | 2022-10-18 | 松下知识产权经营株式会社 | Weld bead appearance inspection device, weld bead appearance inspection method, program, and weld bead appearance inspection system |
| CN113270393A (en) * | 2021-05-12 | 2021-08-17 | 武汉新芯集成电路制造有限公司 | Test key structure and wafer stacking structure |
| CN113270393B (en) * | 2021-05-12 | 2024-03-15 | 武汉新芯集成电路制造有限公司 | Test key structure and wafer stacking structure |
| CN113571498A (en) * | 2021-09-24 | 2021-10-29 | 晶芯成(北京)科技有限公司 | Semiconductor structure and test structure thereof |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140425 |
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Effective date of registration: 20140425 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120704 |
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| RJ01 | Rejection of invention patent application after publication |