CN102543196B - Data reading method, memory storage device and controller thereof - Google Patents

Abstract

The invention discloses a data reading method, a memory storage device and a controller thereof. The data reading method is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity pages. The method comprises the steps of grouping the entity pages into a plurality of entity page groups; and sets a corresponding threshold voltage set for each physical page group. The method also includes reading data from the physical pages of the physical page groups using the corresponding threshold voltage sets, respectively. The method further includes updating the threshold voltage set corresponding to one of the physical page groups when data read from the one of the physical pages of the one of the physical page groups cannot be corrected by the error correction circuit. Therefore, the correctness of the read data can be effectively ensured.

Description

Data reading method, memory storage device and controller thereof

technical field

The invention relates to a data reading method for a rewritable nonvolatile memory, in particular to a method for readjusting when the data read from the rewritable nonvolatile memory cannot be corrected A method of reading voltage to correctly read data, and a memory controller and a memory storage device using the method.

Background technique

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for digital content storage also increase rapidly. Due to the characteristics of non-volatile data, power saving, small size and no mechanical structure, Flash Memory is suitable for users to carry as a storage medium for digital file transmission and exchange. A solid state drive (Solid State Drive, SSD) is an example of a flash memory as a storage medium, and has been widely used in computer host systems as a main hard drive.

The current flash memory is mainly divided into two types, which are NOR flash memory (NORFlash) and NAND flash memory (NAND Flash). Flash memory can also be divided into multi-level memory cell (Multi-Level Cell, MLC) flash memory and single-level memory cell (Single-Level Cell, SLC) flash memory according to the number of data bits that each memory cell can store. . Each storage unit of the SLC flash memory can only store 1 bit of data, while each storage unit of the MLC flash memory can store at least 2 or more bits of data. For example, taking the 4-layer memory unit flash memory as an example, each memory unit can store 2 bits of data (ie, “11”, “10”, “00” and “01”).

In flash memory, memory cells are connected in series by bit lines (Bit Line) and word lines (Word Line) to form a memory cell array (memory cell array). When the control circuit controlling the bit line and the word line reads or writes data to a specified memory cell of the memory cell array, the floating voltage of other unspecified memory cells may be disturbed (disturb), thereby causing an error bit (i.e. , the data read by the control circuit from the storage unit (also known as read data) is different from the data originally written (also known as written data). Or, when the flash memory may be idle for a long time, the memory In the event of wear caused by electric leakage, multiple erasing or writing, etc., the floating voltage in the memory cell may also change to cause an error bit.

Generally, memory storage devices are equipped with error correction circuits. When writing data, the error correction circuit will generate an error correction code for the written data, and when reading data, the error correction circuit will perform error correction decoding for the read data according to the corresponding error correction code ( Also known as the error correction procedure), whereby the erroneous bits are corrected. However, the number of error bits that can be corrected by the error correction circuit is limited. Once the number of error bits in the read data exceeds the number of error bits that can be corrected by the error correction circuit, the read data will not be corrected. is corrected. At this time, the host system cannot correctly read the correct data from the memory storage device. Due to the evolution of the process or the characteristics of the hardware architecture of the memory itself, there are more and more error bits (such as the number of bits that each memory cell of the multi-level memory cell flash memory can store is more, and the error bits that may be generated are also higher than those of SLC. Many), therefore, how to ensure the correctness of the read data has become a topic of concern to those skilled in the art.

Contents of the invention

The invention provides a data reading method, a memory controller and a memory storage device, which can correctly read the data stored in the rewritable non-volatile memory.

An exemplary embodiment of the present invention provides a data reading method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical pages. The data reading method includes grouping these physical pages into multiple physical page groups; and setting a corresponding threshold voltage group for each physical page group, wherein each bit group data reading voltage group includes multiple threshold voltages. The data reading method also includes reading data from the physical pages of the physical page groups using the corresponding threshold voltage groups respectively. The data reading method further includes, when the data read from one of the physical pages of one of the physical page groups cannot be corrected by the error correction circuit, updating the threshold voltage group corresponding to the physical page group.

An exemplary embodiment of the present invention provides a data reading method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical pages arranged in sequence. The data reading method includes: using at least a threshold voltage to obtain first data from a first physical page among the physical pages; and judging whether the first data can be corrected by an error correction circuit to generate a corresponding first physical page. The first corrected data for the page. The data reading method also includes, if the first data cannot be corrected by the error correction circuit to generate corrected data corresponding to the first physical page, obtaining the second data from the second physical page among the physical pages, Wherein the second physical page is adjacent to the first physical page, and the second data can be corrected by the error correction circuit to generate second corrected data corresponding to the second physical page. The data reading method also includes: obtaining error bit information by comparing the second data with the second corrected data corresponding to the second physical page; calculating at least one compensation voltage according to the error bit information; using the calculated Compensating the voltage to adjust the threshold voltage to an adjusted threshold voltage; and obtaining another first data from the first physical page using the adjusted threshold voltage and correcting the other first data by an error correction circuit to generate a corresponding first physical page The first corrected data for the page.

Exemplary embodiments of the present invention provide a memory controller for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical pages. The memory controller includes a memory management circuit, a host interface electrically connected to the memory management circuit, a memory interface, an error correction circuit and a read voltage update circuit. The memory management circuit is used to group these physical pages into a plurality of physical page groups, set a corresponding threshold voltage group for each physical page group, and respectively use the corresponding threshold voltage groups to read from the physical pages of these physical page groups fetching data, wherein each bit group data reading voltage group includes a plurality of threshold voltages. The memory interface is used to electrically connect to the rewritable non-volatile memory module. Here, when the data read by the memory management circuit from one of the physical pages of one of the physical page groups cannot be corrected by the error correction circuit, the read voltage update circuit updates the threshold voltage group corresponding to the physical page group.

An exemplary embodiment of the present invention provides a memory controller for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical pages arranged in sequence. The memory controller includes a memory management circuit, a host interface electrically connected to the memory management circuit, a memory interface, an error correction circuit and a read voltage update circuit. The memory interface is used to electrically connect to the rewritable non-volatile memory module. Here, the memory management circuit is used to obtain first data from the first physical page using at least one threshold voltage, and determine whether the error correction circuit can correct the first data to generate first corrected data corresponding to the first physical page. If the error correction circuit cannot correct the first data to generate corrected data corresponding to the first physical page, the memory management circuit is further configured to obtain the second data from the second physical page, wherein the second physical page is adjacent to the first physical page , and the second data can be corrected by the error correction circuit to generate second corrected data corresponding to the second physical page. The reading voltage updating circuit is used for comparing the second data with the second corrected data corresponding to the second physical page to obtain error bit information, calculate at least one compensation voltage according to the error bit information, and calculate the compensation voltage according to the calculated compensation voltage to adjust the threshold voltage to the adjusted threshold voltage. In addition, the memory management circuit is also used to obtain another first data from the first physical page using the adjusted threshold voltage, and the error correction circuit corrects the other first data to generate first corrected data corresponding to the first physical page.

An exemplary embodiment of the invention provides a memory storage device, which includes a connector, a rewritable non-volatile memory module, and a memory controller. The connector is used to electrically connect to the host system. The rewritable non-volatile memory module has multiple physical pages. The memory controller is electrically connected to the connector and the rewritable non-volatile memory module, and has an error correction circuit. The memory controller is used to group these physical pages into a plurality of physical page groups, set a corresponding threshold voltage group for each physical page group and use the corresponding threshold voltage group to read data from the physical pages of these physical page groups respectively , wherein each bit group data read voltage group includes a plurality of threshold voltages. When the data read by the memory controller from one of the physical pages of one of the physical page groups cannot be corrected by the error correction circuit, the memory controller updates the threshold voltage corresponding to the physical page group Group.

An exemplary embodiment of the invention provides a memory storage device, which includes a connector, a rewritable non-volatile memory module, and a memory controller. The connector is used to electrically connect to the host system. The rewritable non-volatile memory module has multiple physical pages. The memory controller is electrically connected to the connector and the rewritable non-volatile memory module, and has an error correction circuit. The memory controller is used to obtain first data from a first physical page among the physical pages by using at least a threshold voltage, and judge whether the error correction circuit can correct the first data to generate first corrected data corresponding to the first physical page . If the error correction circuit cannot correct the first data to generate corrected data corresponding to the first physical page, the memory controller is further configured to obtain second data from a second physical page among the physical pages, wherein the second physical page is adjacent to the first physical page, and the second data can be corrected by the error correction circuit to generate second corrected data corresponding to the second physical page. In addition, the memory controller is also used to compare the second data with the second corrected data corresponding to the second physical page to obtain error bit information, calculate at least one compensation voltage according to the error bit information, and calculate the compensation voltage according to the calculated compensation voltage. The above-mentioned threshold voltage is adjusted to an adjusted threshold voltage. Moreover, the memory controller is further configured to use the adjusted threshold voltage to obtain another first data from the first physical page, and the error correction circuit corrects the other first data to generate first corrected data corresponding to the first physical page .

Based on the above, the data reading method, the memory controller and the memory storage device of the exemplary embodiments of the present invention can effectively ensure the correctness of the read data.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention.

FIG. 1B is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment of the present invention.

FIG. 1C is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention.

FIG. 2 is a schematic block diagram illustrating the memory storage device shown in FIG. 1A .

FIG. 3 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

FIG. 4 is a statistical distribution diagram of floating voltages corresponding to written data stored in a memory cell array according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic diagram of a read operation for one of the memory cells according to the first exemplary embodiment of the present invention.

FIG. 6 is a schematic diagram of a read operation of an 8-layer memory unit according to another exemplary embodiment of the present invention.

FIG. 7 is a schematic block diagram of a memory controller according to an exemplary embodiment of the invention.

FIG. 8 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

FIG. 9 is an example of read data according to an exemplary embodiment of the present invention.

FIG. 10 is a schematic diagram illustrating error types of statistical error bits according to an exemplary embodiment of the present invention.

FIG. 11 is a flowchart of a data reading method according to an exemplary embodiment of the present invention.

Description of reference symbols

1000: host system

1100: computer

1102: Microprocessor

1104: random access memory

1106: Input/Output Device

1108: System bus

1110: data transmission interface

1202: Mouse

1204: keyboard

1206: display

1208: Printer

1212: Pen drive

1214: memory card

1216: SSD

1310: Digital camera

1312: SD card

1314: MMC card

1316: memory stick

1318: CF card

1320: Embedded Storage

100: memory storage device

102: Connector

104: memory controller

106: Rewritable non-volatile memory module

202: memory cell array

204: word line control circuit

206: Bit line control circuit

208: column decoder

210: Data input/output buffer

212: Control circuit

VA: first threshold voltage

VB: second threshold voltage

VC: the third threshold voltage

VD: fourth threshold voltage

VE: fifth threshold voltage

VF: sixth threshold voltage

VG: seventh threshold voltage

702: memory management circuit

704: host interface

706: memory interface

708: Error Correction Circuit

710: read voltage update circuit

752: buffer memory

754: Power management circuit

410(0)～410(N): Entity page group

400(0)-0~400(0)~K: Entity page

1002, 1004, 1006, 1008, 1010, 1012: blocks

S1101, S1103, S1105, S1107, S1109, S1111, S1113, S1115: Steps to read data

Detailed ways

In an exemplary embodiment of the present invention, the physical pages of the rewritable non-volatile memory module can be grouped into a plurality of physical page groups, and each physical page group is configured with a corresponding threshold voltage group. And, the data in the physical pages of the physical page group will be read using the corresponding threshold voltage set. Especially, when the read data cannot be corrected by the error correction circuit, the corresponding threshold voltage set is adjusted according to the error bit information obtained from adjacent physical pages. Since the threshold voltage group is adjusted according to the characteristics of its corresponding physical page group, the correctness of the read data can be more guaranteed. The following examples will illustrate the present invention in detail.

In general, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1A is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A , the host system 1000 generally includes a computer 1100 and an input/output (I/O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices.

In the embodiment of the present invention, the memory storage device 100 is electrically connected with other components of the host system 1000 through the data transmission interface 1110 . Data can be written into the memory storage device 100 or read from the memory storage device 100 by the operation of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a pen drive 1212, a memory card 1214, or a solid state drive (Solid State Drive, SSD) 1216 as shown in FIG. 1B.

In general, the host system 1000 can be virtually any system that can cooperate with the memory storage device 100 to store data. Although in this exemplary embodiment, the host system 1000 is described as a computer system, however, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host system is a digital camera (video camera) 1310, the rewritable nonvolatile memory storage device is an SD card 1312, an MMC card 1314, a memory stick (memory stick) 1316, and a CF card 1318. Or an embedded storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.

FIG. 2 is a schematic block diagram illustrating the memory storage device shown in FIG. 1A .

Referring to FIG. 2 , the memory storage device 100 includes a connector 102 , a memory controller 104 and a rewritable non-volatile memory module 106 .

In this exemplary embodiment, the connector 102 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connector 102 may also be a high-speed peripheral component connection interface (Peripheral Component Interconnect Express, PCI Express) that complies with the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard Standard, Universal Serial Bus (USB) standard, Secure Digital (Secure Digital, SD) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, small fast Flash (Compact Flash, CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standards.

The memory controller 104 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and write data in the rewritable non-volatile memory module 106 according to the instructions of the host system 1000, Read and erase operations.

The rewritable non-volatile memory module 106 is electrically connected to the memory controller 104 and used for storing data written by the host system 1000 . In this exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level cell (Multi Level Cell, MLC) NAND flash memory module. However, the present invention is not limited thereto, and the rewritable non-volatile memory module 106 can also be other flash memory modules or other memory modules with the same characteristics.

FIG. 3 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

The rewritable non-volatile memory module 106 includes a memory cell array 202 , a word line control circuit 204 , a bit line control circuit 206 , a column decoder 208 , a data input/output buffer 210 and a control circuit 212 .

The memory cell array 202 includes a plurality of memory cells (not shown) for storing data, a plurality of bit lines (not shown) connecting the memory cells, a plurality of word lines and a common source line (not shown). The memory cells are arranged in an array at intersections of bit lines and word lines. When receiving a write command or reading data from the memory controller 130, the control circuit 212 will control the word line control circuit 204, the bit line control circuit 206, the column decoder 208, and the data input/output buffer 210 to write data To the memory array 202 or read data from the memory array 202, wherein the word line control circuit 204 is used to control the word line voltage given to the word line, the bit line control circuit 206 is used to control the bit line, and the column decoder 208 according to the instruction The decoded column address in is used to select the corresponding bit line, and the data input/output buffer 210 is used to temporarily store data.

In this exemplary embodiment, the rewritable non-volatile memory module 106 is an MLC NAND flash memory module, which uses multiple floating voltages to represent multiple bits of data. Specifically, each memory cell of the memory cell array 202 has a plurality of storage states, and the storage states are distinguished by a plurality of threshold voltages.

FIG. 4 is a statistical distribution diagram of floating voltages corresponding to written data stored in a memory cell array according to an exemplary embodiment of the present invention.

Please refer to FIG. 4, taking the 4-level memory cell NAND flash memory as an example, the floating voltage in each memory cell can be divided into four types according to the first threshold voltage VA, the second threshold voltage VB and the third threshold voltage VC. storage states, and these storage states respectively represent "11", "10", "00" and "01". In other words, each storage state includes a Least Significant Bit (LSB) and a Most Significant Bit (MSB). In this exemplary embodiment, the value of the first bit from the left in the storage states (ie, "11", "10", "00" and "01") is LSB, and the value from the left The value of the 2nd bit of the MSB. Therefore, in the first exemplary embodiment, each memory cell can store 2 bits of data. It must be understood that the correspondence between the floating voltage and its storage state shown in FIG. 3 is just an example. In another exemplary embodiment of the present invention, the correspondence between the floating voltage and the storage state can also be arranged in "11", "10", "01" and "00" as the floating voltage increases. Alternatively, the storage state corresponding to the floating voltage can also be the value after mapping or inverting the actual storage value. In addition, in another example, the value of the first bit from the left can also be defined is the MSB, and the second bit from the left is the LSB.

In this exemplary embodiment, each memory cell can store 2 bits of data, so the memory cells on the same word line constitute the storage space of 2 physical pages (ie, the lower page and the upper page). That is, the LSB of each memory cell corresponds to the lower page, and the MSB of each memory cell corresponds to the upper page. In addition, several physical pages in the memory cell array 202 constitute a physical block, and the physical block is the smallest unit for performing erasing operations. That is, each physical block contains the minimum number of memory cells to be erased together.

The data writing of the memory cells of the memory cell array 202 is to use the injection voltage to change the floating voltage of the memory cells to present different storage states. For example, when the data of the lower page is 1 and the data of the upper page is 1, the control circuit 212 controls the word line control circuit 204 not to change the floating voltage of the memory cell, but to keep the storage state of the memory cell as “11”. When the data on the lower page is 1 and the data on the upper page is 0, the word line control circuit 204 changes the floating voltage in the memory cell under the control of the control circuit 212 to change the storage state of the memory cell to "10". When the data on the lower page is 0 and the data on the upper page is 0, the word line control circuit 204 changes the floating voltage in the memory cell under the control of the control circuit 212 to change the storage state of the memory cell to "00". And, when the data on the lower page is 0 and the data on the upper page is 1, the word line control circuit 204 will change the floating voltage in the memory cell under the control of the control circuit 212, and change the storage state of the memory cell to "01"

FIG. 5 is a schematic diagram of a read operation for one of the memory cells according to the first exemplary embodiment of the present invention.

Please refer to FIG. 5 , the data reading of the memory cells of the memory cell array 202 uses the threshold voltage to distinguish the floating voltage of the memory cells. In the operation of reading the data of the next page, the word line control circuit 204 will apply the second threshold voltage VB to the memory cell and determine whether the control gate of the memory cell is turned on and the corresponding formula (1) Values for the next page of data:

LSB＝(VB)Lower_pre1 (1)

Wherein (VB)Lower_pre1 represents the verification value of the first lower page obtained by applying the second threshold voltage VB.

For example, when the second threshold voltage VB is lower than the floating voltage of the memory cell, the control gate of the memory cell will not be turned on and output the first lower page verification value of '0', thus the LSB will be identified as 0. For example, when the second threshold voltage VB is greater than the floating voltage of the memory cell, the control gate of the memory cell will be turned on and output the first lower page verification value of '1', thus the LSB will be identified as 1. That is to say, the floating voltage used to represent LSB 1 and the floating voltage used to represent LSB 0 can be distinguished by the second threshold voltage VB.

In the operation of reading the data of the upper page, the word line control circuit 204 will respectively apply the third threshold voltage VC and the first threshold voltage VA to the memory cell and determine whether the control gate of the memory cell is turned on and the corresponding calculation formula (2) To judge the value of the data on the previous page:

MSB=((VA)Upper_pre2)xor(~(VC)Upper_pre1)(2)

Where (VC)Upper_pre1 represents the verification value of the first upper page obtained by applying the third threshold voltage VC, and (VA)Upper_pre2 represents the verification value of the second upper page obtained by applying the first threshold voltage VA, where symbols "~" stands for inversion. In addition, in this exemplary embodiment, when the third threshold voltage VC is lower than the floating voltage of the memory cell, the control gate of the memory cell is not turned on and the first upper page verify value ((VC)Upper_pre1 ), when the first threshold voltage VA is less than the floating voltage of the memory cell, the control gate of the memory cell will not be turned on and output the second upper page verify value ((VA)Upper_pre2) of '0'.

Therefore, in this exemplary embodiment, according to the formula (2), when both the third threshold voltage VC and the first threshold voltage VA are lower than the floating voltage of the memory cell, the control gate of the memory cell does not operate under the third threshold voltage VC. It will be turned on and output the first upper page verification value of '0' and the control gate of the memory cell will not be turned on and output the second upper page verification value of '0' under the first threshold voltage VA. At this time, the MSB will be recognized as 1.

For example, when the third threshold voltage VC is greater than the floating voltage of the memory cell and the first threshold voltage VA is smaller than the floating voltage of the memory cell, the control gate of the memory cell will be turned on at the third threshold voltage VC and The first upper page verification value of '1' is output, and the control gate of the memory cell is not turned on under the first threshold voltage VA and the second upper page verification value of '0' is output. At this time, the MSB will be recognized as 0.

For example, when both the third threshold voltage VC and the first threshold voltage VA are greater than the floating voltage of the memory cell, under the third threshold voltage VC, the control gate of the memory cell will be turned on and the first upper page of the value '1' will be output. verification value, and under the first threshold voltage VA, the control gate of the memory cell will be turned on and output the verification value of '1' on the second upper page. At this time, the MSB will be recognized as 1.

It must be understood that although the present invention is described with a 4-level storage unit NAND type flash memory. However, the present invention is not limited thereto, and other multi-level storage unit NAND flash memories can also read data according to the above principles.

For example, taking an 8-level storage unit NAND flash memory as an example (as shown in Figure 6), each storage state includes the least significant bit LSB of the first bit from the left, the second bit from the left The center significant bit (Center Significant Bit, CSB) of the ones digit and the most significant bit MSB of the third digit from the left, where the LSB corresponds to the lower page, the CSB corresponds to the middle page, and the MSB corresponds to the upper page. In this example, the floating voltage in each memory cell can be based on the first threshold voltage VA, the second threshold voltage VB, the third threshold voltage VC, the fourth threshold voltage VD, the fifth threshold voltage VE, the sixth threshold voltage VF 8 storage states (namely, “111”, “110”, “100”, “101”, “001”, “000”, “010” and “011”) are distinguished from the seventh threshold voltage VG.

FIG. 7 is a schematic block diagram of a memory controller according to an exemplary embodiment of the invention.

Referring to FIG. 7 , the memory controller 104 includes a memory management circuit 702 , a host interface 704 , a memory interface 706 , an error correction circuit 708 and a read voltage update circuit 710 .

The memory management circuit 702 is used to control the overall operation of the memory controller 104 . Specifically, the memory management circuit 702 has a plurality of control commands, and when the memory storage device 100 is operating, these control commands will be executed to read in the rewritable non-volatile memory module 106 according to the command of the host system 1000. fetch, write or erase data.

In this exemplary embodiment, the control commands of the memory management circuit 702 are implemented in the form of firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a ROM (not shown), and these control instructions are burned into the ROM. When the memory storage device 100 is operating, these control instructions are executed by the microprocessor unit.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 702 can also be stored in a specific area of the rewritable non-volatile memory module 106 (for example, a memory module dedicated to storing system data) system area). In addition, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has a driver code segment, and when the memory controller 104 is enabled, the microprocessor unit will first execute the driver code segment to store data in the rewritable non-volatile memory module 106. The control instructions are loaded into the random access memory of the memory management circuit 702 . Afterwards, the microprocessor unit runs these control instructions to execute data reading, writing and erasing. In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 702 can also be implemented in a hardware form.

The host interface 704 is electrically connected to the memory management circuit 702 and is used for receiving and identifying commands and data transmitted by the host system 1000 . That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 702 through the host interface 704 . In this exemplary embodiment, the host interface 704 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 704 can also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or Other suitable data transmission standards.

The memory interface 706 is electrically connected to the memory management circuit 702 and used for accessing the rewritable non-volatile memory module 106 . That is to say, the data to be written into the rewritable nonvolatile memory module 106 is converted into a format acceptable to the rewritable nonvolatile memory module 106 via the memory interface 706 .

The error correction circuit 708 is electrically connected to the memory management circuit 702 and used for performing error checking and correction procedures to ensure the correctness of data. Specifically, when the memory management circuit 702 receives a write command from the host system 1000, the error correction circuit 708 will generate a corresponding Error Checking and Correcting Code (ECC) for the data corresponding to the write command. Code), and the memory management circuit 702 writes the data corresponding to the write command and the corresponding ECC code into the rewritable non-volatile memory module 106 . Afterwards, when the memory management circuit 702 reads data from the rewritable non-volatile memory module 106, it will simultaneously read the error checking and correction code corresponding to the data, and the error correction circuit 708 will check and correct the code according to the error checking and correction code. The code performs error checking and correction procedures on the read data.

The read voltage update circuit 710 is electrically connected to the memory management circuit 702 and used for adjusting the threshold voltage set used by the memory management circuit 702 from the rewritable non-volatile memory module 106 . The method for adjusting the threshold voltage group will be described in detail below with reference to the accompanying drawings.

In an exemplary embodiment of the invention, the memory controller 104 further includes a buffer memory 752 . The buffer memory 752 is electrically connected to the memory management circuit 702 and used for temporarily storing data and instructions from the host system 1000 or data from the rewritable non-volatile memory module 106 .

In an exemplary embodiment of the invention, the memory controller 104 further includes a power management circuit 754 . The power management circuit 754 is electrically connected to the memory management circuit 702 and used for controlling the power of the memory storage device 100 .

FIG. 8 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

Referring to FIG. 8 , the memory management circuit 702 groups the physical pages of the rewritable non-volatile memory module 106 into physical page groups 400 ( 0 )˜400 (N). In this exemplary embodiment, the memory management circuit 702 groups the physical pages belonging to the same physical block into a physical page group. That is to say, in this exemplary implementation, the physical pages in a physical page group are exactly the physical pages of a physical block. However, the present invention is not limited thereto. In another exemplary embodiment of the present invention, the memory management circuit 702 may also group physical pages belonging to the same plane into a physical page group or treat each physical page as For a single entity page group.

In this exemplary embodiment, the memory management circuit 702 configures an independent threshold voltage set for each physical page group. For example, in an example where the rewritable non-volatile memory module 106 is a 4-level memory unit NAND memory module, each threshold voltage group includes a first threshold voltage VA, a second threshold voltage VB, and a third threshold voltage VC. Moreover, the memory management circuit 702 uses the corresponding threshold voltage set to read the data stored in the physical page of the corresponding physical page group.

For example, the memory management circuit 702 establishes a read voltage table to record a threshold voltage set corresponding to each physical page group. Moreover, whenever data is to be read from the physical page, the memory management circuit 702 will identify the corresponding threshold voltage group from the read voltage table and use the identified threshold voltage group to read data.

That is to say, when data is to be read from a physical page belonging to the physical page group 400(0), the memory management circuit 702 uses the first threshold voltage VA and the second threshold voltage VB corresponding to the physical page group 400(0). and the third threshold voltage VC to read data, and when data is to be read from a physical page belonging to the physical page group 400(N), the memory management circuit 702 will use the first threshold corresponding to the physical page group 400(N) The voltage VA, the second threshold voltage VB and the third threshold voltage VC are used to read data.

Especially, in this exemplary embodiment, when the error correction circuit 708 cannot correct the data read by the memory management circuit 702 from a physical page, the memory management circuit 702 will read data from other physical pages of the same physical page group. The data that can be corrected by the error correction circuit 708 is fetched, and the read voltage update circuit 710 obtains error bit information according to the correctable data to adjust the corresponding threshold voltage group.

FIG. 9 is an example of read data according to an exemplary embodiment of the present invention.

Referring to FIG. 9, if the memory management circuit 702 wants to read data from the first physical page (eg, physical page 400(0)-3) belonging to the first physical page group (eg, physical page group 400(0)) , the step shown by symbol (1) in FIG. 9 , the memory management circuit 702 will use the threshold voltage group corresponding to the physical page group 400 (0) to read uncorrected data from the first physical page (also called the second physical page a data). For example, if the first physical page is the lower page, the memory management circuit 702 will use the second threshold voltage VB corresponding to the physical page group 400(0) to identify the value of each bit in the physical page. For example, if the first physical page is the upper page, the memory management circuit 702 uses the first threshold voltage VA and the third threshold voltage VC corresponding to the physical page group 400(0) to identify the value of each bit in the physical page.

After reading the data, the error correction circuit 708 will perform an error correction procedure according to the error checking and correction code corresponding to the read uncorrected data, and the memory management circuit 702 will judge whether the read uncorrected data is valid is corrected to produce corrected data. If the read uncorrected data cannot be corrected, the memory management circuit 702 will spread from the first physical page to read data from other adjacent physical pages until the read data can be corrected by the error correction circuit 708 until correction.

For example, in the step indicated by symbol (2) in FIG. 9 , the memory management circuit 702 first reads uncorrected data from the physical page 400(0)-4. If the uncorrected data read from the physical page 400(0)-4 still cannot be corrected, the memory management circuit 702 will read from the physical page 400(0)- 2 to read uncorrected data. If the uncorrected data read from the physical page 400(0)-2 still cannot be corrected, the memory management circuit 702 will read from the physical page 400(0) Read uncorrected data in -5, and so on. Finally, if the uncorrected data (also referred to as second data) read from the second physical page (eg, physical page 400(0)-5) can be corrected to generate corrected data corresponding to the second physical page , the memory management circuit 702 transmits the uncorrected data and the corrected data corresponding to the second physical page to the read voltage update circuit 710 .

Afterwards, the read voltage update circuit 710 generates a compensation voltage according to the uncorrected data and the corrected data corresponding to the second physical page and updates the threshold voltage corresponding to the second physical page to the adjusted threshold voltage.

Specifically, the read voltage update circuit 710 sequentially compares each bit of the uncorrected data corresponding to the second physical page with the corrected data and identifies error bits therein. The so-called wrong bit here refers to a bit that should be in a certain state and is misjudged to belong to another state. Moreover, the read voltage update circuit 710 will count the error bit types of these error bits as error bit information and generate a compensation voltage according to the error bit information to adjust the threshold voltage.

FIG. 10 is a schematic diagram illustrating error types of statistical error bits according to an exemplary embodiment of the present invention.

Please refer to FIG. 10 , taking the 4-level memory cell NAND flash memory as an example, the first bit information reading voltage VA is used to distinguish the storage state "11" from the storage state "10", and the second threshold voltage VB is used for The storage state "10" is distinguished from the storage state "00" and the third threshold voltage VC is used to distinguish the storage state "00" from the storage state "01". Here, the state to the left of the threshold voltage is referred to as the first storage state, and the state to the right of the threshold voltage is referred to as the second storage state.

In particular, the read voltage update circuit 710 will count the number of memory cell bits (ie, the first error bit type) that should be in the first storage state but are misjudged as the second storage state for each threshold voltage, and count The number of memory cells that should be in the second storage state but are misjudged as the first storage state (ie, the second error bit type).

As shown in Figure 10, block 1002 represents the storage unit that should be in the storage state "10" but is misjudged as the storage state "11", and block 1004 represents that it should be in the storage state "11" but is misjudged as the storage state " 10" storage unit. In particular, the read voltage updating circuit 710 generates a compensation voltage corresponding to the first threshold voltage VA according to the number of error bits corresponding to the block 1002 and the number of error bits corresponding to the block 1004 among the identified error bits. Moreover, the read voltage update circuit 710 adds the calculated compensation voltage to the first threshold voltage to form a new first threshold voltage VA (ie, the adjusted threshold voltage).

For example, the read voltage update circuit 710 uses the following formula (3) to calculate the compensation voltage:

$\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; g</span>}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; log</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; error</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; error</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Where x represents the compensation voltage, g represents a constant, error2 represents the number of memory cells that should be in the second storage state but are misjudged as the first storage state, and error1 represents the number of memory cells that should be in the first storage state but are misjudged as the second storage state The number of memory cell bits.

Similarly, the read voltage update circuit 710 generates a compensation voltage VB corresponding to the second threshold voltage according to the number of error bits corresponding to the block 1006 and the number of error bits corresponding to the block 1008 among the identified error bits. Moreover, the reading voltage update circuit 710 adds the calculated compensation voltage to the second threshold voltage VB to form a new second threshold voltage VB.

Similarly, the read voltage update circuit 710 generates a compensation voltage VC corresponding to the third threshold voltage according to the number of error bits corresponding to the block 1010 and the number of error bits corresponding to the block 1012 among the identified error bits. Moreover, the reading voltage updating circuit 710 adds the calculated compensation voltage to the third threshold voltage VC to form a new third threshold voltage VC.

Then, the memory management circuit 702 will use the updated threshold voltage (that is, the adjusted threshold voltage) to read data from the first physical page again (as shown in (5) in FIG. 9 ) and the error correction circuit 708 will correct this data to obtain corrected data corresponding to the first physical page.

Specifically, since the adjacent physical pages have similar physical characteristics, when the data read by a certain physical page cannot be corrected, by analyzing the error bit information of its adjacent physical pages to adjust the threshold voltage, it will be possible Read data more correctly.

FIG. 11 is a flowchart of a data reading method according to an exemplary embodiment of the present invention.

Referring to FIG. 11 , in step S1101 , the memory management circuit 702 reads uncorrected data from a target physical page according to the corresponding threshold voltage group in the read voltage table. And in step S1103 , the memory management circuit 702 determines whether the uncorrected data can be corrected by the error correction circuit 708 to generate corrected data corresponding to the physical page.

If the uncorrected data can be corrected, in step S1105, the memory management circuit 702 outputs the corrected data.

If the uncorrected data cannot be corrected, in step S1107, the memory management circuit 702 reads the uncorrected data from adjacent physical pages. How to select adjacent physical pages to read data has been described above, and will not be repeated here.

Afterwards, in step S1109 , it is determined whether the read uncorrected data can be corrected by the error correction circuit 708 . If the read uncorrected data cannot be corrected, step S1107 will be executed again.

If the read uncorrected data can be corrected, in step S1111 , the read voltage update circuit 710 compares the corresponding uncorrected data with the corrected data, and obtains error bit information.

Afterwards, in step S1113 , the reading voltage update circuit 710 calculates a compensation voltage according to the generated error bit information, and adjusts the data bit reading voltage according to the calculated compensation voltage.

Then, in step S1115 , the memory management circuit 7002 updates the corresponding data bit read voltage group in the read voltage table according to the adjusted data bit read voltage.

Next, step S1101 will be executed to try to read data from the target entity page again.

For example, in an exemplary embodiment of the present invention, the memory management circuit 7002 will try to re-read the data in the target physical page according to the continuously adjusted data bit read voltage group, and may not be able to obtain the data corresponding to this page after reading a predetermined number of times. An error message is output when the corrected data of the target entity page is used.

To sum up, the data reading method of the exemplary embodiments of the present invention and the memory storage device and memory controller using the method can read data more accurately according to a more appropriate data bit reading voltage. In addition, when the error correction circuit cannot successfully correct the uncorrected data, by adjusting the data bit reading voltage according to the error bit information obtained from its adjacent physical pages, the corresponding corrected data can be obtained, thereby improving Stability of data storage.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is based on the claims of the present invention.

Claims (30)

1. A data reading method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical pages, the data reading method comprising: Group these entity pages into multiple entity page clusters; setting a threshold voltage set for each of the physical page groups, wherein each of the threshold voltage sets includes a plurality of threshold voltages; reading data from the physical pages of the groups of physical pages using the corresponding sets of threshold voltages, respectively; and When the data read from one of the physical pages of one of the physical page groups cannot be corrected by an error correction circuit, according to the correctable data in other physical pages of the same physical page group data to update the threshold voltage group corresponding to one of the physical page groups. 2. The data reading method as claimed in claim 1, further comprising: A reading voltage table is established to record the threshold voltage groups corresponding to the physical page groups. 3. The data reading method according to claim 1, wherein the step of updating the threshold voltage group corresponding to one of the physical page groups comprises: Retrieving an uncorrected data corresponding to the other physical page from another physical page of the one of the physical page groups using the threshold voltage set corresponding to the one of the physical page groups, wherein the other physical page is adjacent to the one of the physical pages page, and the uncorrected data corresponding to the other physical page can be corrected by the error correction circuit to generate a corrected data corresponding to the another physical page; Obtaining error bit information by comparing the uncorrected data corresponding to the other physical page with the corrected data; calculating at least one compensation voltage according to the error bit information; and At least one threshold voltage in the threshold voltage group corresponding to one of the physical page groups is adjusted by the at least one compensation voltage. 4. A data reading method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical pages arranged in sequence, the data reading method include: obtaining a first data from a first physical page among the physical pages using at least a threshold voltage; judging whether the first data can be corrected by an error correction circuit to generate a first corrected data corresponding to the first physical page; If the first data cannot be corrected by the error correction circuit to generate the corrected data corresponding to the first physical page, obtaining a second data from a second physical page among the physical pages, wherein the The second physical page is adjacent to the first physical page, and the second data can be corrected by the error correction circuit to generate a second corrected data corresponding to the second physical page; Obtaining error bit information by comparing the second data with the second corrected data corresponding to the second physical page; calculating at least one compensation voltage according to the error bit information; adjusting the at least one threshold voltage to at least one adjusted threshold voltage by the at least one compensation voltage; and Obtaining a further first data from the first physical page using the at least one adjusted threshold voltage and correcting the further first data by the error correction circuit to generate the first corrected corresponding to the first physical page data. 5. The data reading method as claimed in claim 4, wherein the second data has a plurality of bits, and each of these bits corresponds to one of a plurality of storage states of the rewritable non-volatile memory module , Wherein the storage states include a first storage state and a second storage state and a first threshold voltage among the at least one threshold voltage is used to distinguish the first storage state from the two storage states, The step of obtaining the error bit information by comparing the second data with the second corrected data corresponding to the second physical page includes: finding a plurality of error bits among the bits of the second data that are different from corresponding bits of the second corrected data; Counting the number of error bits belonging to a first error bit type among the error bits, wherein the error bits belonging to the first error bit type correspond to the first storage state but are mistakenly considered to correspond to the second storage state bit; Counting the number of error bits belonging to a second error bit type among the error bits, wherein the error bits belonging to the second error bit type correspond to the second storage state but are mistakenly considered to correspond to the first storage state bits; and The number of error bits belonging to the first error bit type and the number of error bits belonging to the second error bit type are used as the error bit information. 6. The data reading method according to claim 5, wherein the step of calculating the at least one compensation voltage according to the error bit information comprises: A first compensation voltage among the at least one compensation voltage is calculated according to the number of error bits belonging to the first error bit type and the number of error bits belonging to the second error bit type. 7. The data reading method according to claim 6, wherein the step of adjusting the at least one threshold voltage to the at least one adjusted threshold voltage by the at least one compensation voltage comprises: The first threshold voltage is adjusted to a first adjusted threshold voltage of the at least one adjusted threshold voltage using the first compensation voltage. 8. The data reading method as claimed in claim 4, further comprising: A reading voltage table is established to record the at least one adjusted threshold voltage. 9. The data reading method as claimed in claim 8, further comprising: Group these entity pages into entity page clusters, Wherein the first physical page and the second physical page belong to a first physical page group among the physical page groups, and the at least one adjusted threshold voltage corresponds to the first physical page group. 10. The data reading method as claimed in claim 9, further comprising: Other physical pages belonging to the first physical page group are read using the at least one adjusted threshold voltage according to the read voltage table. 11. A memory controller for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical pages, the memory controller comprising: a memory management circuit for grouping the physical pages into a plurality of physical page groups, setting a threshold voltage group for each of the physical page groups and using the corresponding reading data in a page, wherein each of the threshold voltage groups includes a plurality of threshold voltages; a host interface electrically connected to the memory management circuit; a memory interface electrically connected to the memory management circuit and used to electrically connect to the rewritable non-volatile memory module; an error correction circuit electrically connected to the memory management circuit; and a read voltage update circuit electrically connected to the memory management circuit, Wherein when the data read by the memory management circuit from one of the physical pages of one of the physical page groups cannot be corrected by the error correction circuit, the read voltage update circuit will be based on the same The correctable data in other physical pages of a physical page group is used to update the threshold voltage set corresponding to one of the physical page groups. 12. The memory controller as claimed in claim 11, wherein the memory management circuit is further used to establish a read voltage table to record the threshold voltage groups corresponding to the physical page groups. 13. The memory controller of claim 11 , wherein the memory management circuit uses the threshold voltage set corresponding to one of the physical page groups to obtain the corresponding physical page from another physical page of the one physical page group. an uncorrected data page, wherein the other physical page is adjacent to the one physical page, wherein the error correction circuit corrects the uncorrected data corresponding to the other physical page to generate a corrected data corresponding to the another physical page, Wherein the read voltage update circuit compares the uncorrected data and the corrected data corresponding to the other physical page to obtain error bit information, Wherein the reading voltage update circuit calculates at least one compensation voltage according to the error bit information, Wherein the read voltage update circuit uses the at least one compensation voltage to adjust at least one threshold voltage in the threshold voltage group corresponding to one of the physical page groups. 14. A memory controller for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical pages arranged in sequence, the memory controller comprising : a memory management circuit; a host interface electrically connected to the memory management circuit; a memory interface electrically connected to the memory management circuit and used to electrically connect to the rewritable non-volatile memory module; an error correction circuit electrically connected to the memory management circuit; and a read voltage update circuit electrically connected to the memory management circuit, Wherein the memory management circuit is used to obtain a first data from a first physical page among the physical pages using at least a threshold voltage, and judge whether the error correction circuit can correct the first data to generate corresponding to the first a first corrected data of the entity page, Wherein if the error correction circuit cannot correct the first data to generate the corrected data corresponding to the first physical page, the memory management circuit is also used to obtain a first physical page from a second physical page among the physical pages two data, wherein the second physical page is adjacent to the first physical page, and the second data can be corrected by the error correction circuit to generate a second corrected data corresponding to the second physical page, Wherein the read voltage update circuit is used to compare the second data with the second corrected data corresponding to the second physical page to obtain error bit information, and calculate at least one compensation voltage according to the error bit information, Wherein the read voltage update circuit is further used to adjust the at least one threshold voltage to at least one adjusted threshold voltage according to the at least one compensation voltage, Wherein the memory management circuit is further configured to use the at least one adjusted threshold voltage to obtain another first data from the first physical page and the error correction circuit corrects the other first data to generate a corresponding to the first physical page The first corrected data. 15. The memory controller as claimed in claim 14, wherein the second data has a plurality of bits, and each of these bits corresponds to one of a plurality of storage states of the rewritable non-volatile memory module, Wherein the storage states include a first storage state and a second storage state and a first threshold voltage among the at least one threshold voltage is used to distinguish the first storage state from the two storage states, Wherein the read voltage update circuit is used to find out a plurality of error bits among the bits of the second data that are different from the corresponding bits of the second corrected data, and count the error bits among the error bits belonging to a first error bit The number of error bits of the type, count the number of error bits belonging to a second error bit type among these error bits and compare the number of error bits belonging to the first error bit type with the number of error bits belonging to the second error bit type The number of error bits in the state is used as the error bit information, Wherein the erroneous bit belonging to the first erroneous bit type is a bit corresponding to the first storage state but misidentified as corresponding to the second storage state, The erroneous bits belonging to the second erroneous bit type are bits corresponding to the second storage state but misidentified as corresponding to the first storage state. 16. The memory controller as claimed in claim 15, wherein the read voltage updating circuit calculates according to the number of error bits belonging to the first error bit type and the number of error bits belonging to the second error bit type A first compensation voltage among the at least one compensation voltage. 17. The memory controller of claim 16, wherein the read voltage update circuit adjusts the first threshold voltage to a first adjusted threshold among the at least one adjusted threshold voltage using the first compensation voltage Voltage. 18. The memory controller of claim 14, wherein the memory management circuit is further configured to create a read voltage table to record the at least one adjusted threshold voltage. 19. The memory controller according to claim 18, wherein the memory management circuit is further configured to group the physical pages into a plurality of physical page groups, Wherein the first physical page and the second physical page belong to a first physical page group among the physical page groups, and the at least one adjusted threshold voltage in the read voltage table corresponds to the first physical page group . 20. The memory controller of claim 19, wherein the memory management circuit reads other physical pages belonging to the first physical page group using the at least one adjusted threshold voltage according to the read voltage table. 21. A memory storage device comprising: a connector for electrically connecting to a host system; a rewritable non-volatile memory module having a plurality of physical pages; and A memory controller electrically connected to the connector and the rewritable non-volatile memory module, wherein the memory controller includes: a memory management circuit; a host interface electrically connected to the memory management circuit; a memory interface electrically connected to the memory management circuit and used to electrically connect to the rewritable non-volatile memory module; an error correction circuit electrically connected to the memory management circuit; and a reading voltage update circuit electrically connected to the memory management circuit, Wherein the memory management circuit is used to group these physical pages into a plurality of physical page groups, set a threshold voltage group for each of these physical page groups, and use the corresponding threshold voltage groups to select from the entities of these physical page groups reading data in a page, wherein each of the threshold voltage groups includes a plurality of threshold voltages; Wherein when the data read by the memory management circuit from one of the physical pages of one of the physical page groups cannot be corrected by the error correction circuit, the read voltage update circuit will be based on the same The correctable data in other physical pages of a physical page group is used to update the threshold voltage set corresponding to one of the physical page groups. 22. The memory storage device as claimed in claim 21, wherein the memory management circuit is further used to establish a reading voltage table to record the threshold voltage groups corresponding to the physical page groups. 23. The memory storage device of claim 21 , wherein the memory management circuit uses the threshold voltage set corresponding to one of the physical page groups to obtain the corresponding physical page from another physical page of the one physical page group. an uncorrected data page, wherein the other physical page is adjacent to the one physical page, wherein the error correction circuit corrects the uncorrected data corresponding to the other physical page to generate a corrected data corresponding to the another physical page, Wherein the read voltage update circuit compares the uncorrected data and the corrected data corresponding to the other physical page to obtain error bit information, calculates at least one compensation voltage according to the error bit information, and uses the at least one compensation voltage to adjust at least one threshold voltage in the threshold voltage group corresponding to one of the physical page groups. 24. A memory storage device comprising: a connector for electrically connecting to a host system; A rewritable non-volatile memory module has a plurality of physical pages arranged in sequence; and A memory controller electrically connected to the connector and the rewritable non-volatile memory module, wherein the memory controller includes: a memory management circuit; a host interface electrically connected to the memory management circuit; a memory interface electrically connected to the memory management circuit and used to electrically connect to the rewritable non-volatile memory module; an error correction circuit electrically connected to the memory management circuit; and a read voltage update circuit electrically connected to the memory management circuit, Wherein the memory management circuit is used to obtain a first data from a first physical page among the physical pages using at least a threshold voltage, and judge whether the error correction circuit can correct the first data to generate corresponding to the first a first corrected data of the entity page, Wherein if the error correction circuit cannot correct the first data to generate the corrected data corresponding to the first physical page, the memory management circuit is also used to obtain a first physical page from a second physical page among the physical pages two data, wherein the second physical page is adjacent to the first physical page, and the second data can be corrected by the error correction circuit to generate a second corrected data corresponding to the second physical page, Wherein the read voltage update circuit is used to compare the second data with the second corrected data corresponding to the second physical page to obtain error bit information, calculate at least one compensation voltage according to the error bit information, and according to the at least one compensation voltage to adjust the at least one threshold voltage to at least one adjusted threshold voltage, Wherein the memory management circuit is further configured to use the at least one adjusted threshold voltage to obtain another first data from the first physical page and the error correction circuit corrects the other first data to generate a corresponding to the first physical page The first corrected data. 25. The memory storage device as claimed in claim 24, wherein the second data has a plurality of bits, and each of these bits corresponds to one of a plurality of storage states of the rewritable non-volatile memory module, Wherein the storage states include a first storage state and a second storage state and a first threshold voltage among the at least one threshold voltage is used to distinguish the first storage state from the two storage states, Wherein the read voltage update circuit is used to find out a plurality of error bits among the bits of the second data that are different from the corresponding bits of the second corrected data, and count the error bits among the error bits belonging to a first error bit The number of error bits of the type, count the number of error bits belonging to a second error bit type among these error bits and compare the number of error bits belonging to the first error bit type with the number of error bits belonging to the second error bit type The number of error bits in the state is used as the error bit information, Wherein the erroneous bit belonging to the first erroneous bit type is a bit corresponding to the first storage state but misidentified as corresponding to the second storage state, The erroneous bits belonging to the second erroneous bit type are bits corresponding to the second storage state but misidentified as corresponding to the first storage state. 26. The memory storage device of claim 25, wherein the read voltage updating circuit calculates according to the number of error bits belonging to the first error bit type and the number of error bits belonging to the second error bit type A first compensation voltage among the at least one compensation voltage. 27. The memory storage device of claim 26, wherein the read voltage update circuit uses the first compensation voltage to adjust the first threshold voltage to a first adjusted threshold among the at least one adjusted threshold voltage Voltage. 28. The memory storage device of claim 24, wherein the memory management circuit is further configured to create a read voltage table to record the at least one adjusted threshold voltage. 29. The memory storage device as claimed in claim 28, wherein the memory management circuit is further used to group the physical pages into a plurality of physical page groups, Wherein the first physical page and the second physical page belong to a first physical page group among the physical page groups, and the at least one adjusted threshold voltage in the read voltage table corresponds to the first physical page thereof group. 30. The memory storage device of claim 29, wherein the memory management circuit reads other physical pages belonging to the first physical page group using the at least one adjusted threshold voltage according to the read voltage table.