CN102521793A - Storage control device and method for realizing saving of image storage space - Google Patents
Storage control device and method for realizing saving of image storage space Download PDFInfo
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Abstract
The invention provides a storage control device and method for realizing saving of image storage space. The storage control device comprises an image storage unit, an image acquisition or processing circuit, a writing control unit, a writing data preparation unit and a plurality of line cache units. The method comprises the following steps: when the writing data preparation unit detects that the cache states of the line cache units are valid, one-line writing operation is started, then according to the word alignment condition of a writing target address, integration is carried out to form one word writing data which is sent to the writing control unit; the writing control unit operates the address of each-time writing action, sends a writing command, obtains writing data, writes the writing data to the target address in the image storage unit; the width of each-time writing operation is four bytes till the whole-line data is written to the target address; and circulating so, all the lines are written into the target address of the image storage unit. The invention has the advantages that when the width of image data is not integral multiple to the word, the data of the last pixels of one line and the former pixel of next line can be stored in one word, so that the image storage space is saved.
Description
[technical field]
The present invention relates to a kind of storage controlling method and device of realizing saving image storage space.
[background technology]
Development along with technology; User interface and image special effect are more and more gorgeous, and its corresponding needed picture material is also more and more, and the characteristics of these picture materials are that image is little and many; Caused when handling and show special efficacy, material image has taken a large amount of storage spaces.If the storage space of these images of minimizing that can try one's best will be very significant.
Present storage mode be when the view data width be not word (computer data unit " word "; Equal 32bit) integral multiple the time; Can use invalid data to fill part invalid among last word in the delegation; The data of next line begin storage from the address of word alignment again, and this storage mode is handled simple, but the invalid data in the image storage space can be wasted storage resources.
As shown in Figure 1, be the 14byte pictorial data of (8bit just is called a byte (Byte)) if need storage width, at first from the address write data of 0x0; When writing the position of 14byte, latter two byte uses invalid data to fill, the pictorial data that the data of next line begin to store next 14byte from the address of the address 0x10 of word alignment again; Equally; When writing the position of 14byte, latter two byte uses invalid data to fill, and the like; Each line latter two byte is to use invalid data to fill, and causes a large amount of waste of storage space.
As shown in Figure 2 again, be the pictorial data of 13byte if need storage width, at first from the address write data of 0x0; When writing the position of 13byte, last 3 byte use invalid data to fill, the pictorial data that the data of next line begin to store next 13byte from the address of the address 0x10 of word alignment again; Equally; When writing the position of 13byte, latter two byte uses invalid data to fill, and the like; Last 3 byte of each line are to use invalid data to fill, and cause a large amount of waste of storage space.
[summary of the invention]
One of technical matters that the present invention will solve; Be to provide a kind of memory control device of realizing saving image storage space; When the view data width is not the integral multiple of word, can with the starting pixel data storage of last several pixels of delegation and next line in a word, can save the storage space of resorting to trickery to serve oneself of image like this; Particularly when a large amount of little pictures need be stored, can save a large amount of storage resources.
The present invention solves the problems of the technologies described above through following technical proposals: a kind of memory control device of realizing saving image storage space is characterized in that: comprise line buffer unit, the write data preparatory unit that connects successively and write control module; Said line buffer unit also is connected with the IMAQ or the treatment circuit of external circuit, and the said control module of writing also is connected with the image storage unit of external circuit;
Said image storage unit is responsible for storing the view data of compact storage;
Said IMAQ or treatment circuit are responsible for generation needs the image stored data, and view data is deposited in the line buffer unit;
The said control module of writing is responsible for the address that action is write in computing at every turn, sends write order according to the sequential of writing of storage unit, and gets write data from the write data preparatory unit and write the image storage unit;
Whether the write data preparatory unit is responsible for detecting the row cache state is effective; If effectively just begin the write operation of delegation; Give after write operation row cache data are integrated and write control module and write in the image storage unit, calculate simultaneously and write the byte significance bit and it is sent to write operation unit;
Said line buffer unit comprises two row or the above image data storage space of two row; This row cache becomes effective status after the row cache data of delegation are filled up by the IMAQ of outside or treatment circuit; The write data preparatory unit has detected the row cache state when being effective; Just begin the write operation of delegation,, write the control module break-off and wait for that the row cache state becomes effectively when whole row caches all have when invalid; After any row cache state becomes effectively, begin the write operation of new delegation.
Two of the technical matters that the present invention will solve; Be to provide a kind of storage controlling method of realizing saving image storage space; When the view data width is not the integral multiple of word, can with the starting pixel data storage of last several pixels of delegation and next line in a word, can save the storage space of resorting to trickery to serve oneself of image like this; Particularly when a large amount of little pictures need be stored, can save a large amount of storage resources.
The present invention solves the problems of the technologies described above through following technical proposals: a kind of storage controlling method of realizing saving image storage space comprises the steps:
Whether the buffer status that step 2, write data preparatory unit begin to detect a plurality of line buffer unit of row is effectively, if effectively just begin the write operation of delegation, gets into step 3, otherwise continues to detect;
View data in step 3, the effective line buffer unit of the continuous write operation of write data preparatory unit, according to the word alignment situation of writing destination address, the write data that is integrated into 1 word is sent to one and writes control module again;
Step 4, write the address that action is write in the control module computing at every turn; The sequential of writing according to an image storage unit is sent write order; And obtain write data from the write data preparatory unit; And it is write the destination address in the image storage unit, each write operation width is 4 bytes, is write destination address up to the full line data;
Step 5, continuous circulation step 2～4 are write in the destination address of image storage unit up to all provisional capitals of image.
The present invention has following advantage: control method of the present invention and control device are when the view data width is not the integral multiple of word; Can be in a word with the starting pixel data storage of last several pixels of delegation and next line; Can save the storage space of image like this; Particularly when a large amount of little pictures need be stored, can save a large amount of storage resources; The control method clear thinking is convenient to the control device hardware circuit and is realized; The control device convenient configuration, external interface is friendly, and convenient outside demonstration or treatment circuit use.
[description of drawings]
Combine embodiment that the present invention is further described with reference to the accompanying drawings.
Fig. 1 is the storage organization synoptic diagram of the image storage space of an example in the prior art.
Fig. 2 is the storage organization synoptic diagram of the image storage space of another example in the prior art.
Fig. 3 is the storage organization synoptic diagram of the image storage space of one embodiment of the invention.
Fig. 4 is the storage organization synoptic diagram of the image storage space of another embodiment of the present invention.
Fig. 5 is a memory control device structural representation of the present invention.
Fig. 6 is a storage controlling method FB(flow block) of the present invention.
Fig. 7 is the storage organization synoptic diagram of the image storage space of yet another embodiment of the invention.
Fig. 8 is the storage organization synoptic diagram of the write operation process steps decomposing state of Fig. 7 embodiment.
[embodiment]
The present invention provides a kind of storage organization of realizing saving image storage space; When the view data width is not the integral multiple of word; Can be in a word with the starting pixel data storage of last several pixels of delegation and next line; The storage space of resorting to trickery to serve oneself of image can be saved like this, particularly when a large amount of little pictures need be stored, a large amount of storage resources can be saved.
As shown in Figure 3, be the pictorial data of 14byte if need storage width, at first from the address write data of 0x0; When writing the position of 14byte, latter two byte uses the data of next line to fill, i.e. the address of the data of next line 0xc from the address pictorial data that begins to store next 14byte; Equally, when writing the position of 14byte, last 4 byte use the data of next line to fill; And the like, there is not waste of storage space, can save a large amount of storage resources.
As shown in Figure 4 again, be the pictorial data of 13byte if need storage width, at first from the address write data of 0x0; When writing the position of 13byte, last 3 byte use the data of next line to fill, i.e. the address of the data of next line 0xd from the address pictorial data that begins to store next 13byte; Equally, when writing the position of 13byte, last 2 byte use the data of next line to fill; And the like, there is not waste of storage space, can save a large amount of storage resources.
In conjunction with Fig. 5 to Fig. 8, introduce control method of the present invention in detail.
At first as shown in Figure 5, the present invention provides a kind of memory control device of realizing saving image storage space, comprises line buffer unit, the write data preparatory unit that connects successively and writes control module; Said line buffer unit also is connected with the IMAQ or the treatment circuit of external circuit, and the said control module of writing also is connected with the image storage unit of external circuit;
Said image storage unit is responsible for storing the view data of compact storage;
Said IMAQ or treatment circuit are responsible for generation needs the image stored data, and view data is deposited in the line buffer unit;
The said control module of writing is responsible for the address that action is write in computing at every turn, sends write order according to the sequential of writing of storage unit, and gets write data from the write data preparatory unit and write the image storage unit;
Whether the write data preparatory unit is responsible for detecting the row cache state is effective; If effectively just begin the write operation of delegation; Give after write operation row cache data are integrated and write control module and write in the image storage unit, calculate simultaneously and write the byte significance bit and it is sent to write operation unit;
Said line buffer unit comprises two row or the above image data storage space of two row; This row cache becomes effective status after the row cache data of delegation are filled up by the IMAQ of outside or treatment circuit; The write data preparatory unit has detected the row cache state when being effective; Just begin the write operation of delegation,, write the control module break-off and wait for that the row cache state becomes effectively when whole row caches all have when invalid; After any row cache state becomes effectively, begin the write operation of new delegation.
As shown in Figure 6 again, the present invention provides a kind of storage controlling method of realizing saving image storage space again, can adopt above-mentioned memory control device to control, and specifically comprises the steps:
Whether step 2, write data preparatory unit begin to detect the row cache state is effectively, if effectively just begin the write operation of delegation, gets into step 3, otherwise continues to detect;
Wherein, The effective status of row cache is by IMAQ or treatment circuit decision; When IMAQ or treatment circuit any row cache in line buffer unit is filled view data when reaching delegation's view data; The state of this row can become effectively automatically, and the view data write operation finishes when delegation, and it is invalid that corresponding row cache state can be changed to.
View data in step 3, the effective row cache of the continuous write operation of write data preparatory unit is integrated out the write data of 1 word and is sent to and writes control module according to writing destination address again; Its rule is: the write data preparatory unit is according to the situation of writing destination address word alignment; Read the data that need from line buffer unit; If write destination address word alignment; Then run through whole word data, combine invalid data to become complete word data to be sent to and to write control module otherwise read required byte data according to the situation of not lining up.Such as destination address is that 0x1 rounds word and surpluss 1, then gets 3 byte valid data from row cache and combines 1 byte invalid data to become 1 complete word to be sent to and to write control module.
Step 4, write the address that action is write in the control module computing at every turn; The sequential of writing according to storage unit is sent write order; And obtain write data from the write data preparatory unit; And it is write the destination address in the image storage unit, each write operation width is 4 bytes, is write destination address up to the full line data.Its rule is: write control module and begin to write action from initial destination address; The data of each write operation are 1 word, when destination address is not the word alignment, only need partly write with last word data first of every row; So every row first with last word operation in control whether writing of 4 bytes among the word through writing the byte control bit; In the operation of each row of data, each write operation address 1 word that adds up is after having write delegation; Write address jumps to next line and continues beginning; Because data bit width is 1 word, storer supports 4 of the word alignment to write the write operation that the byte control bit is controlled each byte, so the automatic word alignment of control module all can be write in the address of each write operation.
Step 5, continuous circulation step 2～4 are write in the destination address of image storage unit up to all provisional capitals of image.
Now specifically introduce the operational method of the write operation address of each word, and writing method.
1, three variablees need using of introduction at first:
Three variablees are respectively line_align, next_line_start_addr and line_count;
Line_align: the word alignment situation that is used to represent the destination address of current action row; Line_align is an accumulation amount; Be each row of data amount (every capable number of pixels * each pixel words joint number) divided by the adding up of the remainder values of a word, initial value is the byte remainder of image object memory address divided by word, is 0 such as the line_align initial value; First row picture traverse 14 bytes are surplused 2 bytes divided by word (4 byte); The line_align=2 of first row then, low two bytes are first line data among this explanation first last word of row, remainder is the data of next line; Line_align has write the back at first word of every row and has upgraded.
Next_line_start_addr: the start address that is used to note delegation; Its initial value equals the image object memory address; Every afterwards calculating finishes delegation; Next_line_start_addr just carries out one-accumulate, and computing method are that the every capable number of pixels of next_line_start_addr=next_line_start_addr+ * each pixel accounts for byte number; This variable has been write the back at last word of every row and has been upgraded.
Line_count: be used to add up one's own profession and write how many byte datas; The line_count initial value is 0; Behind every row beginning write operation; Be used to calculate the byte number of writing away; Can be as judging that which time write action and write for last word of one's own profession, when the byte number of every row subtracts difference that line_count obtains smaller or equal to 4 bytes, can confirm to write to move next time and write for last word of one's own profession; Line_count zero clearing after every row is write release.
2, how to judge whether to have write last word in the delegation, can adopt following method to carry out:
1) the line_count initial value is 0;
2) when first word write operation of every row; The line_count accumulated value is calculated as line_count=line_count+ (4-line_align); Each write operation between every row first and last word write operation; Line_count adds up 4, and the write operation method of judging every last word of row to be exactly byte number when every row subtract difference that line_count obtains can be confirmed to write number next time and be last word write operation of one's own profession during smaller or equal to 4 bytes; Behind intact last word of every row of write operation, the line_count automatic clear;
3, the idiographic flow of control write operation address:
A) the next_line_start_addr initial value equals image storage destination address;
B) word write operation for the first time; The write operation address is the initial value (image storage destination address) of next_line_start_addr; Each word write operation of first row all adds a word side-play amount on the next_line_start_addr basis afterwards, up to first last word of row; After first last word write operation of row finished, next_line_start_addr upgraded, and computing method are that the every capable number of pixels of next_line_start_addr=next_line_start_addr+ * each pixel accounts for byte number; Then, first write operation address of next line begins from new next_line_start_addr again, and whenever next word side-play amount adds up, and has write up to next line, and next_line_start_addr upgrades again, and so circulation finishes up to the image write operation;
C) each final write operation address of exporting is rounded back output to 4, this is because a write operation data width is 1 word, so final write operation address of exporting need round 4.
4, how the write data preparatory unit is controlled from the row cache read data and is integrated write data and the byte significance bit is write in calculating:
(1) the line_align initial value is the byte remainder of image storage destination address divided by word;
(2) line_align upgrades in the intact back of first word write operation of every row, and update algorithm is line_align=(the every capable view data byte number %4 of line_align+) %4, and % is for getting surplus symbol in the formula;
(3) the word write operation first time of every row; Need judge that from row cache, reading how many bytes makes the word data integration according to the value of line_align; The byte number that from row cache, reads (4-line_align) byte for beginning from the row cache starting point; Add any invalid data of line_align byte again at low level; Write control module and carry out write operation thereby the write data of integrating out 1 word is sent to, write data to write the significance bit state of writing that invalid data is corresponding arbitrarily in the byte significance bit be invalid, other bytes all are effective.Line_align such as first first word of row is 0, then from row cache, reads 4 byte datas that starting point begins, and passes to these four byte datas as a word write data then and writes control module, writes byte significance bit position binary one 111; If line_align is 1 then from row cache, reads 3 byte datas that starting point begins; Then with 3 bytes as high position data; The write data that any invalid data of piece together going up 1 byte of low level again becomes a word is sent to be write control module and carries out write operation, and writing the byte significance bit is binary one 110;
(4) behind first word of every row; Each row cache before last word reads; All be directly on last basis of once reading, to read 4 bytes more backward, and these 4 bytes are sent to write operation unit as write data, writing the byte significance bit all is binary one 111;
(5) during last word, if line_align is 0 then reads 4 byte datas and deliver to write operation unit as write data from row cache; If be not 0; Then read line_align byte data from row cache, and with this line_align data as low level, any invalid data of (4-line_align) individual byte becomes 1 word data and is sent to write operation unit in the integration; The significance bit state of writing of writing any invalid data correspondence in the byte significance bit of write data is invalid; Other bytes all are effectively, be 1 such as line_align and read 1 byte data from row cache, and with these 1 data as low level; High-order 3 any invalid datas of byte become 1 word data and are sent to write operation unit in the integration, and writing the byte significance bit is Binary Zero 001.
Wherein, write the byte significance bit and refer to such data, each bit of these data is corresponding to each byte in the write data; 0 this byte write invalidate of expression; Just not with this byte write store, 1 this byte of expression is with effect, just with this byte write store; For 32 bit bit wides, writing the byte significance bit is 4 bits, corresponding to controlling with imitating of 4 bytes in the write data.Such as write data is 0x4321; Writing the byte significance bit is 2 bit binary number 0011; The data of destination address are 0x00000000; Then write data is through after writing byte significance bit control and writing, and low 2 bytes of write data are written into destination address, and the data of destination address 0x00000000 become 0x0021 after then writing action and accomplishing.
Please emphasis with reference to figure 7 and Fig. 8, introduce a concrete operations example below in detail:
This concrete operations example is to be that 10 bytes are example with a picture traverse, and expectation is write image in the storage space that initial destination address is 0x1 with compact form.
Concrete operations are as shown in Figure 7, among Fig. 7 in 4 bytes of write data the left side be low data, the right is a high position data.The view data location mode that is stored in the image storage unit preceding two capable and preceding 3 byte compact storage of the third line of its final expectation.
At the beginning; Detect the row cache state by the write data preparatory unit,, then do not have write operation if do not have the row cache state for effectively; When external image collection or treatment circuit row cache is filled full after the row cache state become effectively; After the write data preparatory unit detects, as shown in Figure 8, the beginning write operation:
The 1st write operation, line_align equals start address %4=1, and next_line_start_addr equals 0x1, and write address is that next_line_start_addr rounds 4 and is 0x0.Owing to be first word write operation in the delegation, the line_count accumulated value is (4-line_align), so be 3 after line_count adds up.The word write operation first time of every row; Need judge that from row cache, reading how many bytes does the word data and piece together according to the value of line_align; The byte number that from row cache, reads (4-line_align) byte for beginning from the row cache starting point adds any invalid data of line_align byte again at low level, write control module and carry out write operation thereby the write data of piecing together out 1 word is sent to; The significance bit state of writing of writing any invalid data correspondence in the byte significance bit of write data is invalid; Other bytes all are effectively, so 3 bytes that starting point begins in the row cache are read in operation for the first time, add any invalid data of 1 byte again at low level; Write control module and carry out write operation thereby the write data of piecing together out 1 word is sent to, the byte significance bit of writing of write data is a binary one 110.
The 2nd write operation adds 4 during write address and equals 0x4 on last write address basis, next_line_start_addr equals 1, and line_align upgrades in the intact back of first word write operation of every row, and update algorithm does
Line_align=(the every capable view data byte number %4 of line_align+) %4, so line_align=(1+10%4) %4=3, line_count adds up and 4 equals 7.Because be not first word or last word of one's own profession; So the read data preparatory unit reads in the row cache last 4 bytes that end point begins that read; And the write data of this 1 word is sent to writes control module and carry out write operation, the byte significance bit of writing of write data is a binary one 111.
The 3rd write operation, line_align equals 3, and write address adds 4 and equals 0x8 on last write address basis.Because the byte number 10 of every row subtracts difference 3 that line_count value 7 obtains less than 4 bytes, is last write data of one's own profession so judge current word, and line_count is in the zero clearing afterwards that finishes of this write operation.During last word, if line_align is 0 then reads 4 byte datas and deliver to write operation unit as write data from row cache; If be not 0, then read line_align byte data from row cache, and with this line_align data as low level, piecing together any invalid data of (4-line_align) individual byte becomes 1 word data and is sent to write operation unit.The significance bit state of writing of writing any invalid data correspondence in the byte significance bit of write data is invalid, and other bytes all are effective.Because this moment, line_align was 3, thus read 3 byte datas from row cache, and with these 3 data as low level, piecing together 1 any invalid data of byte becomes 1 word data and is sent to write operation unit.The byte significance bit of writing of write data is a Binary Zero 111, and at this moment, the first line data write operation finishes.Next_line_start_addr finishes the back in one's own profession and upgrades next_line_start_addr=1+10=11 (16 systems are 0xb).
At this moment, the write data preparatory unit continues to begin to detect the row cache state, if do not have the row cache state for effectively, does not then have write operation.When external image collection or treatment circuit row cache is filled full back row cache state and become effectively, after the write data preparatory unit detected, continuation began write operation.
The 4th write operation, line_align equals 3, and next_line_start_addr equals 0xb, and write address equals next_line_start_addr and rounds 4, just 0x8.The line_count accumulated value is (4-line_align), equals 1.The word write operation first time of every row; Need judge that from row cache, reading how many bytes does the word data and piece together according to the value of line_align; The byte number that from row cache, reads (4-line_align) byte for beginning from the row cache starting point; Add any invalid data of line_align byte again at low level; Write control module and carry out write operation thereby the write data of piecing together out 1 word is sent to, write data to write the significance bit state of writing that invalid data is corresponding arbitrarily in the byte significance bit be invalid, other bytes all are effective.So 1 byte that starting point begins in the row cache is read in operation for the first time; Add any invalid data of 3 bytes again at low level; Write control module and carry out write operation thereby the write data of piecing together out 1 word is sent to, the byte significance bit of writing of write data is a binary one 000.
The 5th write operation, write address add 4 and equal 0xc on last write address basis, next_line_start_addr equals 0xb, and line_align upgrades in the intact back of first word write operation of every row, and update algorithm does
Line_align=(the every capable view data byte number %4 of line_align+) %4; So line_align=(3+10%4) %4=1; Line_count adds up and 4 equals 5, because be not first word or last word of one's own profession, so the read data preparatory unit reads and lastly in the row cache reads 4 bytes that end point begins; And the write data of this 1 word is sent to writes control module and carry out write operation, the byte significance bit of writing of write data is a binary one 111.
The 6th write operation, write address add 4 and equal 0x10 on last write address basis, next_line_start_addr equals 0xb, and line_align equals 1.Line_count adds up and 4 equals 9. because be not first word or last word of one's own profession; So the read data preparatory unit reads in the row cache last 4 bytes that end point begins that read; And the write data of this 1 word is sent to writes control module and carry out write operation, the byte significance bit of writing of write data is a binary one 111.
The 7th write operation, line_align equals 1, and write address adds 4 and equals 0x14 on last write address basis.Because the byte number 10 of every row subtracts difference 1 that line_count value 9 obtains less than 4 bytes, is last write data of one's own profession so judge current word, and line_count is in the zero clearing afterwards that finishes of this write operation.During last word, if line_align is 0 then reads 4 byte datas and deliver to write operation unit as write data from row cache; If be not 0, then read line_align byte data from row cache, and with this line_align data as low level, piecing together any invalid data of (4-line_align) individual byte becomes 1 word data and is sent to write operation unit.The significance bit state of writing of writing any invalid data correspondence in the byte significance bit of write data is invalid; Other bytes all are effective. because this moment, line_align was 1; So read 1 byte data from row cache; And with these 1 data as low level, piecing together 3 any invalid datas of byte becomes 1 word data and is sent to write operation unit.The byte significance bit of writing of write data is a Binary Zero 001.At this moment, the second line data write operation finishes .next_line_start_addr at one's own profession end back renewal, next_line_start_addr=11+10=21 (16 systems are 0x15).
At this moment; The write data preparatory unit continues to begin to detect the row cache state; If do not have the row cache state for effective; Then there is not write operation. when external image collection or treatment circuit row cache is filled full back row cache state and become effectively, after the write data preparatory unit detected, continuation began write operation.
The 8th write operation, line_align equals 1, and next_line_start_addr equals 0x15, and write address equals next_line_start_addr and rounds 4, and just the 0x14.line_count accumulated value is (4-line_align), equals 3.The word write operation first time of every row; Need judge that from row cache, reading how many bytes does the word data and piece together according to the value of line_align; The byte number that from row cache, reads (4-line_align) byte for beginning from the row cache starting point; Add any invalid data of line_align byte again at low level; Write control module and carry out write operation thereby the write data of piecing together out 1 word is sent to, write data to write the significance bit state of writing that invalid data is corresponding arbitrarily in the byte significance bit be invalid, other bytes all are effective.So 3 bytes that starting point begins in the row cache are read in operation for the first time; Add any invalid data of 1 byte again at low level; Write control module and carry out write operation thereby the write data of piecing together out 1 word is sent to, the byte significance bit of writing of write data is a binary one 110.
This moment, first data write operation of the third line finished, and the data after the third line are all carried out write operation according to top rule with the data of all row of back, finish up to the entire image write operation.
Though more than described embodiment of the present invention; But the technician who is familiar with the present technique field is to be understood that; We described concrete embodiment is illustrative; Rather than being used for qualification to scope of the present invention, those of ordinary skill in the art are in the modification and the variation of the equivalence of doing according to spirit of the present invention, all should be encompassed in the scope that claim of the present invention protects.
Claims (8)
1. a memory control device of realizing saving image storage space is characterized in that: comprise line buffer unit, the write data preparatory unit that connects successively and write control module; Said line buffer unit also is connected with the IMAQ or the treatment circuit of external circuit, and the said control module of writing also is connected with the image storage unit of external circuit;
Said image storage unit is responsible for storing the view data of compact storage;
Said IMAQ or treatment circuit are responsible for generation needs the image stored data, and view data is deposited in the line buffer unit;
The said control module of writing is responsible for the address that action is write in computing at every turn, sends write order according to the sequential of writing of storage unit, and gets write data from the write data preparatory unit and write the image storage unit;
Whether the write data preparatory unit is responsible for detecting the row cache state is effective; If effectively just begin the write operation of delegation; Give after write operation row cache data are integrated and write control module and write in the image storage unit, calculate simultaneously and write the byte significance bit and it is sent to write operation unit;
Said line buffer unit comprises two row or the above image data storage space of two row; This row cache becomes effective status after the row cache data of delegation are filled up by the IMAQ of outside or treatment circuit; The write data preparatory unit has detected the row cache state when being effective; Just begin the write operation of delegation,, write the control module break-off and wait for that the row cache state becomes effectively when whole row caches all have when invalid; After any row cache state becomes effectively, begin the write operation of new delegation.
2. a storage controlling method of realizing saving image storage space is characterized in that: comprise the steps:
Step 1, beginning, at first being responsible for generation by IMAQ or treatment circuit needs the image stored data, and view data is deposited in a plurality of line buffer unit;
Whether the buffer status that step 2, write data preparatory unit begin to detect a plurality of line buffer unit of row is effectively, if effectively just begin the write operation of delegation, gets into step 3, otherwise continues to detect;
View data in step 3, the effective line buffer unit of the continuous write operation of write data preparatory unit, according to the word alignment situation of writing destination address, the write data that is integrated into 1 word is sent to writes control module again;
Step 4, write the address that action is write in the control module computing at every turn; The sequential of writing according to an image storage unit is sent write order; And obtain write data from the write data preparatory unit; And it is write the destination address in the image storage unit, each write operation width is 4 bytes, is write destination address up to the full line data;
Step 5, continuous circulation step 2～4 are write in the destination address of image storage unit up to all provisional capitals of image.
3. the storage controlling method of image storage space is saved in realization as claimed in claim 2; It is characterized in that: the effective status of the row cache of said a plurality of line buffer unit is by IMAQ or treatment circuit decision; When IMAQ or treatment circuit any row cache in line buffer unit is filled view data when reaching delegation's view data; The state of this line buffer unit can become effectively automatically; The view data write operation finishes when delegation, and it is invalid that corresponding row cache state can be changed to.
4. the storage controlling method of image storage space is saved in realization as claimed in claim 2; It is characterized in that: the method for the write data that is integrated into 1 word in the said step 3 is: the write data preparatory unit is according to the situation of writing destination address word alignment; Read the data that need from line buffer unit; If write destination address word alignment; Then run through whole word data, combine invalid data to become complete word data to be sent to and to write control module otherwise read required byte data according to the situation of not lining up.
5. the storage controlling method of image storage space is saved in realization as claimed in claim 2; It is characterized in that: in the said step 4 write the control module computing write at every turn action the address method be: write control module and begin to write action from initial destination address; The data of each write operation are 1 word, when destination address is not the word alignment, only need partly write with last word data first of every row; So every row first with last word operation in control whether writing of 4 bytes among the word through writing the byte control bit; In the operation of each row of data, each write operation address 1 word that adds up is after having write delegation; Write address jumps to next line and continues beginning; Because data bit width is 1 word, storer supports 4 of the word alignment to write the write operation that the byte control bit is controlled each byte, so the automatic word alignment of control module all can be write in the address of each write operation.
6. like the storage controlling method of claim 2 or 4 described realizations saving image storage spaces, it is characterized in that: the method for the write data that is integrated into 1 word in the said step 3 specifically comprises the steps:
Step 31, set the word alignment situation that a variable line_align is used to represent the destination address of current action row; Line_align is an accumulation amount, and upgrading the accumulation calculating formula is line_align=(the every capable view data byte number %4 of line_align+) %4, and % is for getting surplus symbol in the formula; Initial value is the byte remainder of image object memory address divided by word;
Which word in the delegation has been write in step 32, judgement, specifically be to judge it is the word between first word of every row, first word and last word, or last word's is any?
Step 33, carry out write operation according to judged result:
If first word of every row; Be earlier to judge that according to the value of line_align from row cache, reading how many bytes makes the word data and piece together during write operation; The byte number that from row cache, reads (4-line_align) byte for beginning from the row cache starting point; Add any invalid data of line_align byte again at low level; Write control module and carry out write operation thereby the write data of piecing together out 1 word is sent to, write data to write the significance bit state of writing that invalid data is corresponding arbitrarily in the byte significance bit be invalid, other bytes all are effective;
If between first word of every row and last word; Each row cache reads during write operation; All be directly on last basis of once reading, to read 4 bytes more backward, and these 4 bytes are sent to write operation unit as write data, writing the byte significance bit all is binary one 111;
If last word is during write operation, if line_align is 0 then reads 4 byte datas and deliver to write operation unit as write data from row cache; If be not 0; Then read line_align byte data from row cache; And with this line_align data as low level; Piecing together any invalid data of (4-line_align) individual byte becomes 1 word data and is sent to write operation unit, write data to write the significance bit state of writing that invalid data is corresponding arbitrarily in the byte significance bit be invalid, other bytes all are effective.
7. like the storage controlling method of claim 2 or 6 described realizations saving image storage spaces, it is characterized in that: the concrete deterministic process of said step 32 comprises:
321) setting a variable line_count is used to add up one's own profession and has write how many byte datas; The line_count initial value is 0;
322) when first word write operation of every row, the line_count accumulated value is calculated as line_count=line_count+ (4-line_align), the each write operation between every row first and last word write operation, and line_count adds up 4; When the byte number of every row subtracts difference that line_count obtains smaller or equal to 4 bytes, can confirm to write number next time and be last word write operation of one's own profession; Behind intact last word of every row of write operation, the line_count automatic clear.
8. the storage controlling method of image storage space is saved in realization as claimed in claim 5, it is characterized in that: the control module computing of writing in the said step 4 is write the method for the address of action at every turn and is:
41) set the start address that a variable next_line_start_addr is used to note delegation; Its initial value equals image storage destination address;
42) word write operation for the first time, the write operation address is the initial value of next_line_start_addr, each word write operation of first row all adds a word side-play amount on the next_line_start_addr basis afterwards, up to first last word of row; After first last word write operation of row finished, next_line_start_addr upgraded, and computing method are that the every capable number of pixels of next_line_start_addr=next_line_start_addr+ * each pixel accounts for byte number; Then, first write operation address of next line begins from new next_line_start_addr again, and whenever next word side-play amount adds up, and has write up to next line, and next_line_start_addr upgrades again, and so circulation finishes up to the image write operation;
43) each final write operation address of exporting is rounded back output to 4.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103150703A (en) * | 2012-11-15 | 2013-06-12 | 长沙景嘉微电子股份有限公司 | Hardware implementation for frame storage data transfer module applied to image processing |
| CN108257582A (en) * | 2018-01-30 | 2018-07-06 | 广东中星微电子有限公司 | A kind of display buffer method and apparatus of image |
| CN110782389A (en) * | 2019-09-23 | 2020-02-11 | 五八有限公司 | Image data byte alignment method and terminal |
| CN112950456A (en) * | 2021-02-25 | 2021-06-11 | 合肥宏晶微电子科技股份有限公司 | Image processing method and device, electronic equipment and computer readable medium |
| CN115374032A (en) * | 2022-10-24 | 2022-11-22 | 北京智芯微电子科技有限公司 | Non-aligned data transmission method, writing method and device in memory |
| CN117853312A (en) * | 2024-01-16 | 2024-04-09 | 上海为旌科技有限公司 | Method and device for extracting image data from memory |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1448871A (en) * | 2003-04-07 | 2003-10-15 | 西安交通大学 | Design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure |
| JP2007223184A (en) * | 2006-02-24 | 2007-09-06 | Canon Finetech Inc | Image recording apparatus and image data processing method |
| CN101038664A (en) * | 2006-03-17 | 2007-09-19 | 索尼株式会社 | Image processing apparatus and image processing method |
| JP2010033420A (en) * | 2008-07-30 | 2010-02-12 | Oki Semiconductor Co Ltd | Cache circuit and cache memory control method |
| JP2011203843A (en) * | 2010-03-24 | 2011-10-13 | Kyocera Mita Corp | Information processing apparatus |
-
2011
- 2011-12-01 CN CN201110393383.XA patent/CN102521793B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1448871A (en) * | 2003-04-07 | 2003-10-15 | 西安交通大学 | Design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure |
| JP2007223184A (en) * | 2006-02-24 | 2007-09-06 | Canon Finetech Inc | Image recording apparatus and image data processing method |
| CN101038664A (en) * | 2006-03-17 | 2007-09-19 | 索尼株式会社 | Image processing apparatus and image processing method |
| JP2010033420A (en) * | 2008-07-30 | 2010-02-12 | Oki Semiconductor Co Ltd | Cache circuit and cache memory control method |
| JP2011203843A (en) * | 2010-03-24 | 2011-10-13 | Kyocera Mita Corp | Information processing apparatus |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103150703A (en) * | 2012-11-15 | 2013-06-12 | 长沙景嘉微电子股份有限公司 | Hardware implementation for frame storage data transfer module applied to image processing |
| CN108257582A (en) * | 2018-01-30 | 2018-07-06 | 广东中星微电子有限公司 | A kind of display buffer method and apparatus of image |
| CN110782389A (en) * | 2019-09-23 | 2020-02-11 | 五八有限公司 | Image data byte alignment method and terminal |
| CN110782389B (en) * | 2019-09-23 | 2023-09-15 | 五八有限公司 | Image data byte alignment method and terminal |
| CN112950456A (en) * | 2021-02-25 | 2021-06-11 | 合肥宏晶微电子科技股份有限公司 | Image processing method and device, electronic equipment and computer readable medium |
| CN115374032A (en) * | 2022-10-24 | 2022-11-22 | 北京智芯微电子科技有限公司 | Non-aligned data transmission method, writing method and device in memory |
| CN115374032B (en) * | 2022-10-24 | 2023-02-17 | 北京智芯微电子科技有限公司 | Method and device for transmitting and writing non-aligned data in memory |
| CN117853312A (en) * | 2024-01-16 | 2024-04-09 | 上海为旌科技有限公司 | Method and device for extracting image data from memory |
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