CN100524170C - Controller for controlling memory to low power consumption mode and control method therefor - Google Patents

Abstract

The present invention provides a controller and a control method for controlling a memory to enter a low power consumption mode, the key point of which is that the state controller can automatically generate a low power consumption mode after the CPU completes the read/write operation on the memory with low power consumption function The control signal controls the memory to enter the low power consumption mode. When the read/write operation ends, the state controller outputs a reset signal to the interrupt generator, and the interrupt generator starts timing according to the reset signal, and outputs an interrupt signal to the state controller when the preset time value is reached, and the state controller outputs an interrupt signal according to the interrupt The signal generates a low-power mode control signal and sends it to the memory. By applying the scheme of the present invention, the power consumption of the memory when it is idle can be reduced during the process of using the memory, and the battery energy of the mobile device can be further saved.

Description

A controller and control method for controlling memory to enter low power consumption mode

technical field

The invention relates to low power consumption technology, in particular to a controller and a control method for controlling a memory to enter a low power consumption mode.

Background technique

Due to the limitation of battery power supply, mobile devices such as mobile phones have very high power consumption requirements for memory, such as Synchronous Dynamic Random Access Memory (SDRAM). SDRAM is an important storage device in mobile devices, which can provide special power-saving modes or low-power modes, such as power-off (POWERDOWN) mode, self-refresh (Selfrefresh) mode, etc.

Generally speaking, memory with low power consumption functions such as SDRAM only provides a low power consumption mode, and special software is required to control the memory to enter the low power consumption mode. The basic idea of using software to control the memory to enter the low-power mode is to detect in real time whether the mobile device needs to use the memory, and if necessary, control the memory to enter the normal working mode; otherwise, control the memory to enter the low-power mode. The use of memory mentioned here means that the mobile device needs memory to participate in the process of implementing a certain function. For example: MP4 video data is stored in SDRAM, when the mobile device implements the MP4 function, it will inevitably use SDRAM, that is, SDRAM is required to participate. At this time, when the software detects that the mobile device starts the MP4 video function, it will send a command to SDRAM to enter the normal working mode; when the software detects that the mobile device turns off the MP4 video function, it will send a command to SDRAM to enter the low power mode instruction. Of course, in practical applications, the software cannot directly send instructions to SDRAM. Generally, the CPU of the mobile device executes the instructions to control SDRAM to enter normal working mode or enter low power consumption mode, and the CPU sends control commands to SDRAM.

In practical applications, when a mobile device uses SDRAM, that is, when the software controls the SDRAM to enter the normal working mode, the CPU does not always perform read/write operations on the SDRAM, and there is generally a certain amount of idle time between two consecutive read/write operations . For example: when the mobile device is playing an MP4 video program, the CPU reads a batch of data from the SDRAM and stores the data in the cache. Afterwards, the CPU directly reads the data from the cache for playback, and waits until the data in the cache is played before reading the next batch of data from the SDRAM again, and so on.

That is to say, in the prior art, when the CPU reads/writes data from/to the memory twice in a row, the memory is actually in an idle state, but the power consumption is still relatively high because it is in the working mode controlled by software.

It can be seen that, when the mobile device needs to use the memory, the prior art cannot reduce the power consumption of the memory in idle time.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a controller for controlling the memory to enter the low power consumption mode, which can make the memory enter the low power consumption mode during the use of the memory, and reduce the power consumption of the memory when it is idle.

For the device proposed by the present invention, the present invention also provides a method for controlling the memory to enter the low power consumption mode, which can make the memory enter the low power consumption mode during the use of the memory, and reduce the power consumption of the memory when it is idle.

For the first object of the invention, the technical solution proposed by the present invention is:

A controller for controlling a memory to enter a low power consumption mode, the controller at least includes:

The interrupt generator is used to receive a reset signal from the state controller and start timing, and output an interrupt signal to the state controller when the preset time value is reached;

The state controller is used to output a reset signal to the interrupt generator at the end of the memory read and write operations, receive the interrupt signal from the interrupt generator, determine the number of the low power consumption mode that the memory will enter, and according to the low power consumption mode The serial number generates a low-power mode control signal and outputs it to the memory;

Wherein, the state controller includes:

The core controller is configured to output a reset signal to the interrupt generator, receive the interrupt signal input by the interrupt generator, and output the number of the low power consumption mode to be entered by the memory to the control signal generator;

The control signal generator is used to generate a low power consumption mode control signal according to the mode number input by the core controller, and output it to the memory.

Preferably, the interrupt generator includes:

The timer is used to receive a reset signal from the state controller and start counting, and output an interrupt signal to the state controller when the preset time value provided by the timer configuration register is reached;

The timer configuration register is used to save the preset time value solidified in itself or written by the CPU in advance, and provide the preset time value to the timer.

Preferably, the timer is a timer including one or more comparators;

The timer configuration register is a timer configuration register storing one or more preset time values.

Preferably, the state controller further includes:

The memory status register is used to record the mode number of the current low power consumption mode of the memory;

The core controller is further used to read the mode number of the current low power consumption mode of the memory from the memory status register, use the next number of the number of the current low power consumption mode as the number of the low power mode to be entered, and set the memory The number of the low power mode to enter is output to the memory status register.

Preferably, the memory is a Synchronous Dynamic Random Access Memory (SDRAM).

For the second purpose of the invention, the technical solution proposed by the present invention is:

A method for controlling a memory to enter a low power consumption mode, first setting a preset time value, and when the memory read and write operation ends, the method further includes the following steps:

A. The state controller sends a reset signal to the interrupt generator;

B. The interrupt generator starts timing according to the reset signal, and sends an interrupt signal to the state controller when the preset time value is reached;

C, the state controller determines the number of the low power consumption mode that the memory will enter according to the interrupt signal, including: directly using the mode number in the memory state register stored in the state controller in advance as the number of the low power consumption mode that the memory will enter , or, first query the mode number of the current low power consumption mode of the memory recorded in the memory state register in the state controller, and then use the next number of the current mode number as the number of the low power consumption mode to be entered by the memory;

Generate a low power mode control signal according to the number of the low power mode and send it to the memory.

Preferably, the preset time value is one or more preset time values.

Preferably, the method for setting the preset time value is: solidifying the preset time value in the interrupt generator, or writing the preset time value into the interrupt generator by the CPU.

Preferably, the memory is SDRAM.

In summary, a controller and a control method for controlling a memory to enter a low power consumption mode proposed by the present invention have the following advantages:

(1) Since the state controller can send a low-power mode control signal to the memory after the CPU completes the read/write operation to the memory, that is, control the memory to enter the low-power mode, so even if the memory is being used by the mobile device, as long as When the idle time between two consecutive read/write operations reaches a certain limit, it can enter the low power consumption mode, so as to further save the battery energy of the mobile device.

(2) In the present invention, a plurality of preset time values can be set in the interrupt generator, and the state controller controls the memory to enter different low power consumption modes according to the difference in the idle time of the memory. When the idle time is short, the memory enters a low-power mode with high power consumption but a simple process. The longer the idle time, the memory enters a low-power mode with lower power consumption but a complicated process. In this way, if the memory needs to be read/written after a short idle time, it can quickly exit the low power mode and enter the normal working mode; if the memory is idle for a long time, it can enter the low power mode with lower power consumption, To achieve the purpose of minimizing power consumption.

(3) The preset time value in the interrupt generator can not only be solidified in advance, but also can be written by the CPU, which can flexibly set the conditions for controlling the memory to enter the low power consumption mode.

Description of drawings

FIG. 1 is a schematic diagram of a system structure where a controller that controls a memory to enter a low power consumption mode is located;

FIG. 2 is a schematic diagram of the basic structure of a controller that controls a memory to enter a low power consumption mode in the present invention;

Fig. 3 is a schematic diagram of the basic structure of the first embodiment of the device;

Fig. 4 is the flowchart of the scheme of the present invention;

Fig. 5 is a flowchart of an embodiment of a scheme applying the scheme of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

In the present invention, the low power consumption mode controller generates a low power consumption mode control signal after the CPU finishes reading/writing the memory, and controls the memory to enter a corresponding low power consumption mode.

FIG. 1 shows a schematic structural diagram of a system in which a low power consumption mode controller is located in the present invention. As shown in Figure 1, the system includes a CPU, a low-power mode controller, and a memory. In practical applications, when the CPU wants to read/write the memory, it will send a read/write control signal to the memory, perform a read/write operation on the memory, read data from the memory or write data into the memory. Since the number of bytes to be read/written is specified in the read/write control signal, the time to read/write a byte is generally fixed, approximately several clock cycles. Therefore, when the CPU performs a read/write operation on the memory, the low-power mode controller can determine the exact time when the read/write operation ends, so as to control the memory to enter the low-power mode when the read/write operation ends.

The memory described here is a memory with a power saving function, that is, a memory that can provide a low power consumption function, such as SDRAM, mobile RAM, etc.

Among them, the basic structure of the low power consumption mode controller is shown in Fig. 2 . In the present invention, the low power mode controller includes at least an interrupt generator 201 and a state controller 202 .

The interrupt generator 201 is configured to receive a reset signal from the state controller 202 and start timing, and output an interrupt signal to the state controller 202 when a preset time value is reached.

The state controller 202 is configured to output a reset signal to the interrupt generator 201 when the memory read/write operation ends, receive the interrupt signal from the interrupt generator 201, generate a low power consumption mode control signal and output it to the memory.

When the memory read/write operation ends, the state controller 202 outputs a reset signal to the interrupt generator 201; the interrupt generator 201 starts timing after receiving the reset signal from the state controller 202, and sends a reset signal to the interrupt generator 201 when the preset time value is reached. The state controller 202 outputs an interrupt signal; when the state controller 202 receives the interrupt signal from the interrupt generator 201, it generates a low power consumption mode control signal and outputs it to the memory. When the state controller 202 sends the low power consumption mode control signal to the memory, the memory can enter a corresponding low power consumption mode according to the low power consumption mode control signal.

In practical application, a memory with low power consumption function may provide one or more low power consumption modes. If the memory can provide more than one low power consumption mode, the state controller 202 will generate a control signal instructing the memory to enter a certain low power consumption mode. The form of the low power consumption mode control signal is related to the specific memory, as long as the memory with the low power consumption function can recognize the low power consumption mode control signal sent by the state controller 202 .

For example, if the SDRAM is controlled to enter the low power consumption mode, the low power consumption mode control signal sent by the state controller 202 to the SDRAM not only complies with the JEDEC standard of the Federation of Electronic Components Industries, but also supports specific standards proposed by the manufacturer of the SDRAM used. How the SDRAM enters the low power consumption mode belongs to the prior art, and will not be described in detail in the present invention.

Fig. 3 shows a schematic diagram of the basic structure of a device embodiment of the present invention. In this embodiment, the low power mode controller controls the SDRAM to enter the low power mode. As shown in FIG. 3 , the interrupt generator 201 includes a timer configuration register 301 and a timer 302 , and the state controller 202 includes a core controller 303 , a control signal generator 304 , and an SDRAM state register 305 . in,

The timer configuration register 301 is configured to store a preset time value written by the CPU, and provide the preset time value to the timer 302 .

The timer 302 is configured to receive a reset signal from the core controller 303 and start timing, and output an interrupt signal to the core controller 303 when the preset time value provided by the timer configuration register 301 is reached.

The core controller 303 is used to output a reset signal to the timer 302; receive the interrupt signal input by the timer 302, read the mode number of the SDRAM current low power consumption mode in the SDRAM status register 305, and determine that the SDRAM will enter low power consumption next time The mode number of mode, the mode number that SDRAM will enter low power mode next time is output to control signal generator 304, and the mode number that SDRAM will enter low power mode next time is recorded in SDRAM status register as the current state of SDRAM 305 in.

The control signal generator 304 is configured to generate a low power consumption mode control signal according to the mode number input by the core controller 303 and output it to the SDRAM.

Here, the low power consumption mode control signal is in one-to-one correspondence with the mode number, and the corresponding relationship between the mode number and the low power consumption mode control signal to be generated can be stored in the control signal generator 304 in advance. When the control signal generator 304 receives the mode number input by the core controller 303, it can directly generate a corresponding low power consumption mode control signal according to the corresponding relationship.

The SDRAM status register 305 is used to record the mode number of the current low power consumption mode of the SDRAM.

When the SDRAM read and write operations ended, the core controller 303 output a reset signal to the timer 302; the timer 302 started counting, and when reaching the preset time value, output an interrupt signal to the core controller 303; the core controller 303 reads the SDRAM The mode number of the SDRAM current low power mode in the status register 305 determines the mode number of the SDRAM to enter the low power mode next time, and outputs the mode number of the SDRAM to enter the low power mode next time to the control signal generator 304, and Record the mode number of the SDRAM that will enter the low power mode next time as the current state of the SDRAM in the SDRAM status register 305; the control signal generator 304 generates a low power mode control signal according to the mode number, and outputs it to the SDRAM.

In practical applications, the timer configuration register 301 may or may not be included in the interrupt generator 201 . If there is no timer configuration register 301, the timer 302 can represent the preset time value by means of grounding and power supply. For example: the bit connected to the power supply represents "1", and the bit connected to the ground represents "0". If the preset time value is 5, which is expressed as 101 in binary, then the 2nd and 0th bits of the timer input can be connected to the power supply, and the 1st bit can be grounded. At this time, the timer 302 itself can act as an interrupt generator.

If there is a timer configuration register 301, the preset time value can be fixed in the timer configuration register 301 in advance, and the preset time value will not be changed during the operation of the controller, or it can be written by the CPU according to the actual situation The preset time value, the timer 302 works according to the preset time value written by the CPU. After that, the CPU can also write a new preset time value into the timer configuration register 301 according to the actual situation, and the timer 302 works according to the new preset time value.

In practical applications, SDRAM can provide one or more low power consumption modes. If SDRAM provides a low power consumption mode, there is only one comparator in the timer 302 , and there is only one preset time value in the timer configuration register 301 , and the SDRAM status register 305 may not be present. That is to say, after the timer 302 receives the reset signal of the core controller 303, the timer 302 starts counting, and when the comparator determines that the current timing value is equal to the preset time value, the timer 302 sends to the core controller 303 Interrupt signal; the core controller 303 directly outputs the mode number that the SDRAM stored in itself in advance will enter the low power mode to the control signal generator 304; the control signal generator 304 generates a low power mode control signal according to the mode number, And output to SDRAM. Here, since SDRAM only provides a low power consumption mode, the core controller 303 can send a fixed number to the control signal generator 304, and the control signal generator 304 only generates a low power consumption mode control signal . Of course, what number the core controller 303 uses to indicate the low power consumption mode can be determined by the user applying the present invention, as long as the control signal generator 304 can identify it.

If SDRAM can provide more than one low power consumption mode, more than one comparator is included in the timer 302, there is more than one preset time value in the timer configuration register 301, and SDRAM for recording the current state of SDRAM is needed status register 305 . Here, there is a one-to-one correspondence between the preset time value, the comparator in the timer 302 and the low power consumption mode. Take SDRAM can provide three low power consumption modes as an example: the timer 302 includes three comparators, the timer configuration register 301 has three preset time values Ta, Tb and Tc, and Ta<Tb<Tc. Assume that there is a corresponding relationship between the preset time value Ta, comparator 1 and low power consumption mode 1; there is a corresponding relationship between the preset time value Tb, comparator 2 and low power consumption mode 2; the preset time value Tc, comparison There is a corresponding relationship between device 3 and low power consumption mode 3. After the timer 302 receives the reset signal from the core controller 303, the timer 302 starts timing. During the timing, Ta is provided to the comparator 1 for comparison, Tb is provided to the comparator 2 for comparison, and Tc is provided to the comparator 3 for comparison. When the comparator 1 determines that the current timing value is equal to Ta, the timer 302 sends an interrupt signal to the core controller 303, and the core controller 303 controls the SDRAM to enter the first low power consumption mode. Afterwards, the timer 302 still continued timing, and when the comparator 2 determined that the current timing value was equal to Tb, the timer 302 sent an interrupt signal to the core controller 303, and the core controller 303 controlled the SDRAM to enter the low power consumption mode two, and sequentially Inference.

By applying the solution of this embodiment, the SDRAM can be controlled to enter different low power consumption modes. In practical applications, it can also control mobile RAM and other memories with low power consumption functions to enter low power consumption mode, so as to achieve the purpose of further saving battery energy of mobile devices. Of course, at this time, the state controller 202 does not include the SDRAM state register 305, but is replaced with a memory state register 305 that records the states of other memories with low power consumption functions.

For the device provided by the invention, the invention also proposes a control method for controlling the memory to enter the low power consumption mode.

The basic idea of the present invention is: the state controller sends a low power consumption mode control signal to the memory after the memory read/write operation is completed, and controls the memory to enter the low power consumption mode.

Fig. 4 shows a flowchart of the present invention. In the present invention, the time value is preset in the interrupt generator earlier, and when the CPU finishes reading and writing operations on the memory, the method for controlling the memory to enter the low power consumption mode of the present invention includes the following steps:

Step 401: the state controller outputs a reset signal to the interrupt generator;

Step 402: The interrupt generator starts timing after receiving the reset signal, and outputs an interrupt signal to the state controller when the preset time value is reached;

Step 403: The state controller generates a low power consumption mode control signal according to the interrupt signal, and sends it to the memory.

The memory described in the present invention is a memory with low power consumption function, such as: SDRAM and the like.

In practical applications, a memory with a low power consumption function may provide one or more than one low power consumption mode, then in the present invention, the state controller generates control signals corresponding to different low power consumption modes according to the interrupt signal, and the memory can be based on Different low-power mode control signals enter different low-power modes. The form of the low power consumption mode control signal is related to the specific memory, as long as the memory with low power consumption function can recognize the low power consumption mode control signal.

For example, the low power consumption mode control signal sent to SDRAM should follow the standard of the used SDRAM manufacturer in addition to the JEDEC standard of the Electronic Components Industry Association. As for how memory such as SDRAM enters the low power consumption mode, it belongs to the prior art, and will not be described in detail in the present invention.

In practical applications, the number and size of preset time values set in advance can be determined by the user who applies the solution of the present invention. Generally, the number of preset time values is equal to the number of low power consumption modes provided by the memory. For example, if the memory provides three low power consumption modes, three preset time values need to be set, and each preset time value corresponds to a low power consumption mode. The value of the preset time can be determined according to actual conditions such as the time interval T between two adjacent read/write operations of the CPU on the memory. Generally speaking, at least one preset time value should be shorter than the time interval between two adjacent read/write operations of the memory. Certainly, if the time interval between two adjacent read/write operations of the memory is relatively long, more than one time preset value may be set to a value shorter than the time interval between two adjacent read/write operations of the memory.

Figure 5 shows a flow chart of one embodiment of the method of the present invention. In this embodiment, the low-power mode controller will send a low-power mode control signal to the SDRAM, that is, control the SDRAM to enter different low-power modes. SDRAM can provide three low power consumption modes, namely mode 1, mode 2 and mode 3; the CPU writes three preset time values into the interrupt generator in advance, and these three preset time values are Ta, Tb and Tc respectively, And Ta<Tb<Tc. In this embodiment, Ta corresponds to mode one, Tb corresponds to mode two, and Tc corresponds to mode three. That is to say, if the timing value reaches Ta, the state control will control the SDRAM to enter the first low-power mode; if the timing value reaches Tb, the state control will control the SDRAM to enter the second low-power mode; if the timing value reaches Tc, The state control will control SDRAM to enter the third low power consumption mode.

In addition, in this embodiment, the low power consumption mode of the SDRAM is represented by numbers, that is, 000 represents the normal working mode, 001 represents the mode one, 010 represents the mode two, and 011 represents the mode three. When the CPU performs read/write operations on SDRAM, the state controller records the current state of SDRAM as 000; when controlling SDRAM to enter different low power consumption modes, it records the current state of SDRAM as 001, 010 or 011.

As shown in Figure 5, when the reading/writing of the SDRAM by the CPU ends, the method for controlling the SDRAM to enter the low power consumption mode in this embodiment includes the following steps:

Step 501: the state controller sends a reset signal to the interrupt generator, and the interrupt generator starts timing;

Step 502: the interrupt generator sends an interrupt signal to the state controller when the current timing value reaches the preset time value;

Step 503: the state controller inquires and records the mode number of the current low power consumption mode of the SDRAM, and then uses the next number of the current mode number as the mode number of the SDRAM to enter the low power consumption mode next time;

Step 504: The state controller generates a low power consumption mode control signal according to the mode number, and sends it to the SDRAM.

This embodiment has three different preset time values Ta, Tb, and Tc. According to the size of the interval T between the CPU reading/writing operations on the SDRAM twice adjacently, the SDRAM is controlled to enter the low power consumption mode with the following three differences: Case:

If Ta<T<Tb, steps 502 to 504 only need to be performed once. That is to say, the interrupt generator starts timing after reset, and sends an interrupt signal to the state controller when the timing reaches Ta; the state controller inquires and records the mode number of the current low power consumption mode of SDRAM, and determines that the current mode number of SDRAM is 000, Use the next number of the current mode number, namely 001, as the mode number for SDRAM to enter the low-power mode next time; the state controller generates a corresponding low-power mode control signal according to the mode number 001, and sends it to SDRAM to control SDRAM to enter the mode one. After SDRAM enters mode 1, the interrupt generator will continue to count, but since the CPU initiates a read/write operation to SDRAM before Tb time is reached, SARAM is immediately controlled to enter the working mode, and the current mode number of SDRAM is re-recorded as 000.

If Tb<T<Tc, it is necessary to repeat step 502 to step 504 once. That is to say, control the SDRAM to enter the low power consumption mode according to the above-mentioned first case first, since the CPU has not yet initiated the read/write operation to the SDRAM, the interrupt generator will continue timing, and when the timing reaches Tb, it will switch to the state again. The controller sends an interrupt signal; the state controller inquires and records the mode number of the current low-power mode of the SDRAM again, determines that the current mode number of the SDRAM is 001, and uses the next number, namely 010, as the mode for the SDRAM to enter the low-power mode next time Number; the state controller generates a corresponding low power mode control signal according to the mode number 010, sends it to SDRAM, and controls SDRAM to enter mode 2. When the SDRAM enters mode 2, the interrupt generator will continue to count, but since the CPU initiates a read/write operation to the SDRAM before the Tc time is reached, the SARAM is immediately controlled to enter the working mode, and the current mode number of the SDRAM is re-recorded as 000 .

If Tb<T<Tc, step 502 to step 504 need to be repeated twice, that is, the SDRAM will first enter low power consumption mode 1, then low power consumption mode 2, and finally low power consumption mode 3. That is to say, after the SDRAM is controlled to enter the low power mode 2 according to the above second situation, since the CPU has not yet initiated the read/write operation to the SDRAM, the interrupt generator will continue to count, and when the timing reaches Tc, it will switch to the state control again. The device sends an interrupt signal; the state controller queries and records the mode number of the current low-power mode of SDRAM again, determines that the current mode number of SDRAM is 010, and uses the next number, that is, 011, as the mode number for SDRAM to enter the low-power mode next time ; The state controller generates a corresponding low-power mode control signal according to the mode number 011, and sends it to the SDRAM to control the SDRAM to enter mode three. After entering mode 3, SDRAM will always be in a low power consumption state until the CPU initiates a read/write operation to SDRAM.

In practical applications, which low power consumption mode of the SDRAM each preset time value corresponds to can be determined by the user applying the solution of the present invention. Generally speaking, the mode that consumes less power is more complex, and the transition from low power mode to normal mode is more time-consuming. Therefore, the mode with low energy consumption can be associated with a relatively large preset time value. That is to say, SDRAM can first enter a high-energy-consuming but relatively simple low-power mode, and wait until the CPU is still not reading/writing for a long time, and then SDRAM enters a low-energy but relatively complex low-power mode. In this way, if the SDRAM needs to perform read/write operations after a short idle time, it can quickly exit the low power mode and enter the normal working mode; if the SDRAM idle time is very long, it can enter the low power mode with lower power consumption, To achieve the purpose of minimizing power consumption.

In practical applications, if SDRAM only provides one low-power mode, the state controller does not need to record which low-power mode SDRAM is currently in, and only needs to send a fixed mode number to SDRAM directly after receiving an interrupt signal. That is, directly use the mode number stored in itself in advance as the number for the SDRAM to enter the low power consumption mode next time. For example: "1" can be specified as the low-power mode number of SDRAM, and when the state controller receives the interrupt signal, it will directly generate a low-power mode control signal according to the number "1".

In addition, in practical applications, when the state controller receives the read/write control signal from the CPU, it can immediately send the control signal to SDRAM to exit the low power consumption mode, and then enter the normal working mode control signal to control the read/write to SDRAM operate.

To sum up, the above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (9)

1. A controller for controlling memory to enter a low power consumption mode, characterized in that the controller at least includes: The interrupt generator is used to receive a reset signal from the state controller and start timing, and output an interrupt signal to the state controller when the preset time value is reached; The state controller is used to output a reset signal to the interrupt generator at the end of the memory read and write operations, receive the interrupt signal from the interrupt generator, determine the number of the low power consumption mode that the memory will enter, and according to the low power consumption mode The serial number generates a low-power mode control signal and outputs it to the memory; Wherein, the state controller includes: The core controller is configured to output a reset signal to the interrupt generator, receive the interrupt signal input by the interrupt generator, and output the number of the low power consumption mode to be entered by the memory to the control signal generator; The control signal generator is used to generate a low power consumption mode control signal according to the mode number input by the core controller, and output it to the memory. 2. The controller according to claim 1, wherein the interrupt generator comprises: The timer is used to receive a reset signal from the state controller and start counting, and output an interrupt signal to the state controller when the preset time value provided by the timer configuration register is reached; The timer configuration register is used to save the preset time value solidified in itself or written by the CPU in advance, and provide the preset time value to the timer. 3. The controller according to claim 2, wherein the timer is a timer including one or more comparators; The timer configuration register is a timer configuration register storing one or more preset time values. 4. The controller according to claim 1, wherein the state controller further comprises: The memory status register is used to record the mode number of the current low power consumption mode of the memory; The core controller is further used to read the mode number of the current low power consumption mode of the memory from the memory status register, use the next number of the number of the current low power consumption mode as the number of the low power mode to be entered, and set the memory The number of the low power mode to enter is output to the memory status register. 5. The controller according to any one of claims 1 to 4, wherein the memory is a Synchronous Dynamic Random Access Memory (SDRAM). 6. A method for controlling a memory to enter a low power consumption mode, characterized in that the preset time value is first set, and when the memory read and write operation ends, the method also includes the following steps: A. The state controller sends a reset signal to the interrupt generator; B. The interrupt generator starts timing according to the reset signal, and sends an interrupt signal to the state controller when the preset time value is reached; C, the state controller determines the number of the low power consumption mode that the memory will enter according to the interrupt signal, including: directly using the mode number in the memory state register stored in the state controller in advance as the number of the low power consumption mode that the memory will enter , or, first query the mode number of the current low power consumption mode of the memory recorded in the memory state register in the state controller, and then use the next number of the current mode number as the number of the low power consumption mode to be entered by the memory; Generate a low power mode control signal according to the number of the low power mode and send it to the memory. 7. The method according to claim 6, wherein the preset time value is one or more than one preset time value. 8. The method according to claim 6, wherein the method for setting the preset time value is: solidify the preset time value in the interrupt generator, or write the preset time value into the interrupt generator by the CPU. 9. The method according to any one of claims 6-8, wherein the memory is SDRAM.

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