CN102468842A

CN102468842A - Synchronous counter circuit and realization method thereof

Info

Publication number: CN102468842A
Application number: CN2010105468683A
Authority: CN
Inventors: 余秋芳
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2010-11-16
Filing date: 2010-11-16
Publication date: 2012-05-23

Abstract

The invention discloses a synchronous counter circuit and a realization method thereof. The circuit comprises a trigger cascade circuit, a numerical value comparison circuit and a clock gate-controlled cascade circuit, wherein the trigger cascade circuit realizes basic counting function; when a counted numerical value reaches to a preset value, the numerical value comparison circuit generates a corresponding control signal; the control signal is an enable signal of a gate-controlled unit of the clock gate-controlled cascade circuit; and at the moment, the clock gate-controlled cascade circuit generates an input clock of the trigger cascade circuit so as to realize a preset counting function. By using the circuit provided by the invention, the power consumption of the synchronous counter circuit is reduced effectively.

Description

A kind of coincidence counter circuit and its implementation

Technical field

The present invention relates to a kind of coincidence counter circuit and method.Can be used for needs and realize tally function, and have in the IC design of low-power consumption requirement.

Background technology

Counter circuit is one of basic circuit of often using in the IC design.According to the difference of clock pulse input mode, can be divided into coincidence counter and asynchronous counter.All triggers all are operated in counting clock in the coincidence counter circuit, and the control logic relative complex, so power consumption is bigger.The asynchronous counter circuit has only first order flip-flop operation usually at counting clock, and power consumption is less relatively.

In common asynchronous counter circuit structure, after count value arrived design load, the reset signal that decoding circuit produces can reset to trigger flip-flop, made circuit restart counting.In the circuit of this structure, have two problems: 1. the reset signal of decoding circuit generation itself possibly burr occur because of the race hazard of combinational logic, causes false reset signal to produce, thereby makes circuit working unstable.2. it is different that reset signal arrives time of individual count trigger, some trigger may occur and be reset, the situation that the trigger of some also is not reset.At this moment, the reset signal that decoding circuit produces disappears, and the situation that also can cause circuit function to be made mistakes occurs.

Adopt the circuit stability of Synchronization Design good, all used the coincidence counter circuit to design at present a lot of IC design.

Along with the application of portable consumer electronic product is increasingly extensive, power problems is more and more outstanding.For the pursuit of satisfying the user demand of new experience more, increasing function is integrated in the portable product, performance of products is required also high more than in the past.The lifting of these functions and performance all can consume more energy.In battery powered portable product, except function and performance, also be the factor that will consider emphatically the service time of battery.Simultaneously, the restriction of system cost also makes the increasing concern low power dissipation design of designer.At integrated circuit card, especially in the application of non-contact card, the energy that card-reading apparatus can provide is limited, in order to guarantee integrated circuit card ability operate as normal, also requires IC card chip to reduce power consumption.

The present invention is intended to propose a kind of both stable and the lower coincidence counter circuit of power consumption.

Summary of the invention

Content of the present invention is to provide a kind of coincidence counter circuit and implementation thereof, and purpose is in order to reduce the power consumption of coincidence counter circuit in the prior art.

Technical scheme of the present invention is following:

A kind of coincidence counter circuit, comprising trigger cascade circuit, numerical value comparison logic and gate cascade circuit.

The data input pin of triggers at different levels connects the data output end of oppisite phase of self respectively in the trigger cascade circuit.According to position preface from low to high, can the trigger in the trigger cascade circuit be divided into many groups.The clock termination input clock of first group of trigger, the output of the clock termination door control unit of the every group of trigger in back.

The numerical value comparison circuit compares the data output valve and the desired value of each group trigger, output multidigit enable signal.All output valves and desired value like first group of trigger compare, output enable signal a1; All output valves and the desired value of first group and second group trigger compare, output enable signal a2; All output valves and the desired value of first group, second group and the 3rd group trigger compare, output enable signal a3; The rest may be inferred, or the like.

The gate cascade circuit of counter is made up of a plurality of door control units, the clock termination input clock of first order door control unit, and the clock end of back one-level door control unit connects the output of one-level door control unit.The output a1 that enables the termination comparison circuit of first order door control unit, the output a2 that enables the termination comparison circuit of second level door control unit, the rest may be inferred, or the like.Each door control unit comprises a latch and one and door, latch be input as a clock and a clock enable signal, with the output of the same clock of being input as of door and latch, through with door after can produce the clock signal of a process gate.

A kind of coincidence counter circuit provided by the invention and its implementation through the gate cascade circuit, have effectively reduced the clock frequency that is connected to each trigger, thereby have reduced the power consumption of counter.

Utilize coincidence counter circuit provided by the invention, the bit wide of counter is wide more, and the power consumption of reduction is many more.

Description of drawings

Fig. 1 coincidence counter circuit diagram provided by the invention

Fig. 2 door control unit circuit diagram of the present invention

Fig. 3 1024 system tally function oscillograms of the present invention

Embodiment

Below in conjunction with accompanying drawing, specific embodiment of the present invention is carried out detailed explanation.

Fig. 1 is the circuit structure diagram of the synchronous count-up counter of 1024 systems that designed according to disclosed circuit of the present invention and method.

In this practical implementation example; Trigger cascade circuit is made up of the d type flip flop DFF0-DFF9 that ten trailing edges trigger; These triggers of reversed-phase output

that the D end of each trigger connects self respectively can be divided into 4 groups; Form by DFF0 for first group; Form by DFF1-DFF3 for second group, form by DFF4-DFF6 for the 3rd group, form by DFF7-DFF9 for the 4th group.The clock termination input clock of first group of trigger; The output CO0 of the clock termination gate cascade circuit of second group of trigger; The output CO1 of the clock termination gate cascade circuit of the 3rd group of trigger, the output CO2 of the clock termination gate cascade circuit of the 4th group of trigger.When the rising edge of input clock arrived, DFF0 overturn; When 1 to 0 upset took place the Q of previous stage trigger end, the input of back one-level trigger was overturn.

The numerical value comparison circuit is made up of with door two four inputs, and first input signal with door is a1, Q1, Q2, Q3, and second input signal with door is a2, Q4, Q5, Q6.When the value of the data output end Q0 of trigger DFF0 becomes 1, receive the gate 0 output CO0 of Q0 control just can produce a clock pulse; When the value of the data output end Q0Q1Q2Q3 of trigger DFF0-DFF3 becomes 1111, receive the gate 1 output CO1 of a2 control just can produce a clock pulse; When the value of the data output end Q0Q1Q2Q3Q4Q5Q6 of trigger DFF0-DFF6 becomes 1111111, receive the gate 2 output CO2 of a3 control just can produce a clock pulse;

The gate cascade circuit of counter is made up of three door control units, the clock termination input clock of first order door control unit, and the clock end of back one-level door control unit connects the output of one-level door control unit.The output a1 of first group of trigger of Enable Pin of first order door control unit, the output a2 that enables the termination comparison circuit of second level door control unit, the output a3 that enables the termination comparison circuit of third level door control unit.Each door control unit comprises a latch and one and door; Latch be input as a clock and a clock enable signal; With the output of same clock of being input as of door and latch, through producing afterwards a clock signal C O through gate with door.

As stated, the data output end Q9Q8Q7Q6Q5Q4Q3Q2Q1Q0 of trigger DFF9-DFF0 is according to 0000000000,0000000001; 0000000010 ..., 1111111111; 0000000000 order changes, and has realized the counts function of 1024 systems.

Coincidence counter circuit provided by the invention has effectively reduced the clock frequency that is connected to each trigger, thereby has reduced the power consumption of counter.And the bit wide of counter is wide more, and the power consumption of reduction is many more.

Should be understood that; Above-mentioned description to embodiment is comparatively concrete; Just in order better disclosed circuit of the present invention and method to be set forth; Can not therefore think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with accompanying claims.

Claims

1. a coincidence counter circuit is characterized in that comprising trigger cascade circuit, numerical value comparison circuit and Clock gating cascade circuit, wherein:

A plurality of triggers cascade each other in the said trigger cascade circuit, the anti-phase output of every grade of trigger self is as the data input of this trigger;

Said numerical value comparison circuit compares the output of the trigger in the trigger cascade circuit with desired value, output multidigit enable signal;

A plurality of door control units cascade each other in the said Clock gating cascade circuit; The enable signal of door control unit inputs at different levels is the output of numerical value comparison circuit; The output of previous stage door control unit is also imported as the clock of one group of trigger as the clock input of back one-level door control unit simultaneously.

2. coincidence counter circuit according to claim 1; The door control unit that it is characterized in that said clock gate cascade circuit comprises a latch and one and door; Latch be input as a clock and a clock enable signal; With the output of same clock of being input as of door and latch, through producing afterwards a clock signal through gate with door.

3. the implementation method of a coincidence counter is applied in the coincidence counter circuit as claimed in claim 1, it is characterized in that comprising following steps:

(1), input clock is connect the clock end of first order door control unit, with the output of the clock termination previous stage door control unit of back one-level door control unit;

(2), data output valve and the desired value with trigger compares output multidigit clock enable signal;

(3), the clock signal that will pass through gate is connected to the clock end of relative trigger device.