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CN102456658A - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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Publication number
CN102456658A
CN102456658A CN2011102907823A CN201110290782A CN102456658A CN 102456658 A CN102456658 A CN 102456658A CN 2011102907823 A CN2011102907823 A CN 2011102907823A CN 201110290782 A CN201110290782 A CN 201110290782A CN 102456658 A CN102456658 A CN 102456658A
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China
Prior art keywords
substrate
metal pattern
illusory
chip
opening
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Granted
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CN2011102907823A
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CN102456658B (zh
Inventor
金沅槿
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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Abstract

本发明提供一种半导体封装件及其制造方法。该半导体封装件包括电路基板、在电路基板上的半导体芯片、在电路基板和半导体芯片之间的内部焊球以及填充电路基板的基板绝缘层和芯片绝缘层中的至少一个层中的虚设开口的虚设焊料。虚设焊料不将半导体芯片与基板电连接。电路基板可以包括基础基板、在基础基板上的基板连接端子和覆盖基础基板的基板绝缘层。半导体芯片可以包括芯片连接端子和暴露芯片连接端子的芯片绝缘层。内部焊球可以设置在基板连接端子和芯片连接端子之间，以将电路基板电连接到半导体芯片。

Description

半导体封装件及其制造方法
本申请要求于2010年10月20日提交的10-2010-0102563号韩国专利申请的优先权，所述韩国申请的全部内容通过引用被结合于此。
技术领域
本公开在此涉及一种半导体封装件和一种制造该半导体封装件的方法。
背景技术
随着电子装置中使用的半导体集成电路变得更密集化和高度集成化，半导体芯片中的电极端子朝着多引脚(pin)和窄节距的趋势愈演愈烈。此外，在将半导体芯片安装在电路基板(或者布线基板)上时，广泛地使用倒装芯片键合安装(flip chip bonding mounting)来减小布线延迟(wiring delay)。对与半导体封装件的制造方法相关的更可靠和更简单的倒装芯片键合安装方法进行了各种研究。
发明内容
本公开提供一种可靠的半导体封装件。
本公开还提供一种半导体封装件的可靠的制造方法。
根据示例实施例，一种半导体封装件可以包括电路基板和在电路基板上的半导体芯片。在示例实施例中，电路基板可以包括基础基板、在基础基板上的基板连接端子和在基础基板上的基板绝缘层。在示例实施例中，基板绝缘层可暴露基板连接端子。在示例实施例中，半导体芯片可包括芯片连接端子和芯片绝缘层，芯片绝缘层可暴露芯片连接端子。半导体封装件还可以包括在基板连接端子和芯片连接端子之间的内部焊球。在示例实施例中，内部焊球可将基板连接端子电连接至芯片连接端子。半导体封装件还可包括在虚设开口中的虚设焊料，虚设开口可以在基板绝缘层和芯片绝缘层的至少一个层中。在示例实施例中，虚设焊料可不将半导体芯片电连接至电路基板。
根据示例实施例，一种制造半导体封装件的方法可包括下述步骤：形成电路基板，该电路基板包括基础基板、在基础基板上的基板连接端子和覆盖基础基板并暴露基板连接端子的基板绝缘层；在电路基板上形成混合物层，该混合物层包括粘结树脂和多个焊料颗粒；在混合物层上设置半导体芯片，半导体芯片包括芯片连接端子和暴露芯片连接端子的芯片绝缘层；在基板连接端子和芯片连接端子之间形成内部焊球；在虚设开口中形成虚设焊料，虚设开口在基板绝缘层和芯片绝缘层中的一个层中。
根据示例实施例，一种制造半导体封装件的方法可包括下述步骤：在半导体芯片的绝缘层和基板的绝缘层中的至少一个层中形成至少一个虚设开口；在基板和半导体芯片之间形成内部焊球，内部焊球将半导体芯片的芯片连接端子电连接至基板的基板连接端子；在至少一个虚设开口中形成虚设焊料，虚设焊料不将基板电连接至半导体芯片。
本发明构思的示例实施例提供半导体封装件，所述半导体封装件包括：电路基板，包括基础基板、在基础基板上的基板连接端子和覆盖基础基板并暴露基板连接端子的基板绝缘层；半导体芯片，包括芯片连接端子和暴露芯片连接端子的芯片绝缘层，半导体芯片安装在电路基板上；内部焊球，设置在基板连接端子和芯片连接端子之间，内部焊球将芯片连接端子电连接到基板连接端子；虚设焊料，填充虚设开口，虚设开口形成在基板绝缘层和芯片绝缘层中的至少一个层中，其中，虚设焊料不将半导体芯片与基板电连接。
在一些示例实施例中，电路基板还可以包括穿过电路基板的通孔和覆盖通孔的内侧壁的金属图案；形成在基板绝缘层中的虚设开口暴露通孔金属图案；虚设焊料接触通孔金属图案并填充通孔。
在其他的示例实施例中，电路基板还可包括电连接至基板连接端子的电路金属图案；形成在基板绝缘层中的虚设开口暴露电路金属图案；虚设焊料接触电路金属图案。
在另一些其他的示例实施例中，虚设开口的宽度可以较电路金属图案的宽度宽。
在又一些其他的示例实施例中，电路基板还可以包括基板虚设金属图案；形成在基板绝缘层中的虚设开口可以暴露基板虚设金属图案；虚设焊料可以接触虚设金属图案。
在再一些其他的示例实施例中，虚设开口的宽度可以比基板虚设金属图案的宽度宽。
在进一步的示例实施例中，电路基板还可以包括凹进区域和覆盖凹进区域的侧壁和底部的凹进金属图案；形成在基板绝缘层中的虚设开口暴露虚设金属图案；虚设焊料接触凹进金属图案并填充凹进区域。
在更进一步的示例实施例中，半导体芯片还可以包括芯片虚设金属图案；形成在芯片绝缘层中的虚设开口暴露芯片虚设金属图案；虚设焊料接触芯片虚设金属图案。
在再进一步的示例实施例中，半导体芯片还可以包括接触芯片连接端子的突起；内部焊球可以覆盖突起的至少一个侧面。
在又进一步的示例实施例中，半导体芯片还可以包括穿过半导体芯片的过孔。
在又进一步的示例实施例中，半导体封装件还可以包括安装在半导体芯片上并电连接到过孔的上部半导体芯片。
在本发明构思的其他的示例实施例中，制造半导体封装件的方法包括下述步骤：形成电路基板，该电路基板包括基础基板、在基础基板上的基板连接端子和覆盖基础基板并暴露基板连接端子的基板绝缘层；形成混合物层，混合物层设置在电路基板上，并包含粘结树脂和多个焊料颗粒；在混合物层上设置半导体芯片，半导体芯片包括芯片连接端子和暴露芯片连接端子的芯片绝缘层；在基板连接端子和芯片连接端子之间形成内部焊球，其中，将基板绝缘层和芯片绝缘层中的至少一个层形成为包括虚设开口；形成内部焊球的步骤包括：形成填充虚设开口的虚设焊料。
在一些示例实施例中，形成混合物层的步骤可以包括涂覆包含粘结树脂和分散在粘结树脂中的焊料颗粒的混合物。
在其他的示例实施例中，形成混合物层的步骤可以包括：设置混合多层，该混合多层包括由粘结树脂形成的粘结树脂层和由焊料颗粒形成的焊料颗粒层。
在另一些其他的示例实施例中，形成内部焊球的步骤可以包括以高于焊料颗粒熔点的温度执行加热工艺。
在又一些其他的示例实施例中，形成电路基板的步骤可以包括：准备基础基板；在基础基板上形成基板连接端子；形成覆盖基础基板并暴露基板连接端子的基板绝缘层。
在再一些其他的示例实施例中，该方法还包括：在基础基板上形成电路金属图案，其中，基板绝缘层包括暴露电路金属图案的虚设开口。
在进一步的示例实施例中，暴露电路金属图案的虚设开口的宽度可形成为比电路金属图案的宽度宽。
在另外进一步的示例实施例中，所述方法还可包括：通过图案化基础基板形成通孔；形成覆盖通孔的侧壁的通孔金属图案，其中，基板绝缘层包括暴露通孔金属图案的虚设开口。
在更进一步的示例实施例中，所述方法还可包括：在基础基板上形成凹进区域，形成覆盖凹进区域的侧壁和底部的凹进金属图案，其中，基板绝缘层形成为具有暴露凹进金属图案的虚设开口。
在再进一步的示例实施例，所述方法还可包括：在基础基板上形成基板虚设金属图案，其中，基板绝缘层形成有暴露基板虚设金属图案的虚设开口。
在再进一步的示例实施例中，暴露基板虚设金属图案的虚设开口可以形成为具有比基板虚设金属图案的宽度宽的宽度。
在再进一步的示例实施例中，所述方法还可包括：在半导体芯片上形成上部混合层；提供上部半导体芯片，该上部半导体芯片配置在上部混合层上，并包括上部芯片连接端子和暴露上述芯片连接端子的上部芯片绝缘层；在芯片连接端子和上部芯片连接端子之间形成上部内部焊球；
在再进一步的示例实施例中，可同时执行形成内部焊球的步骤和形成上部内部焊球的步骤。
附图说明
包括附图以提供对本发明构思的进一步理解，且附图被纳入并构成本说明书的一部分。附图示出了本发明构思的示例实施例，并与描述一起用于解释本发明构思的原理。在附图中：
图1是根据本发明构思的第一示例实施例的半导体封装件的平面图；
图2是沿图1的II-II’线截取的剖视图；
图3到图8、图9A、图10A和图12是示出根据本发明构思的示例实施例的具有图2的剖面的半导体封装件的顺序制造过程的制造剖视图；
图9B是图9A的A部分的放大透视图；
图10B是图10A的B部分的放大剖视图；
图11A是示出根据本发明构思的另一示例实施例的具有图2的剖面的半导体封装件的制造剖视图；
图11B是图11A的C部分的放大剖视图；
图13是根据本发明构思的第二示例实施例的半导体封装件的平面图；
图14A是沿图13的XIVA-XIVA’线截取的剖视图；
图14B是沿图13的XIVB-XIVB’线截取的剖视图；
图15A到图19A是示出具有14A的剖面的半导体封装件的顺序制造过程的制造剖视图；
图15B到图19B是示出具有14B的剖面的半导体封装件的顺序制造过程的制造剖视图；
图18C是图18A的D部分的放大透视图；
图20是根据第三示例实施例的半导体封装件的剖视图；
图21是根据本发明构思的第四示例实施例的半导体封装件的剖视图；
图22是根据第五示例实施例的半导体封装件的剖视图；
图23到图26是示出根据本发明构思的示例实施例的具有图22的剖面的半导体封装件的顺序制造过程的制造剖视图；
图27是示出根据本发明构思的另一示例实施例的具有图22的剖面的半导体封装件的顺序制造过程的制造剖视图；
图28是示出包括应用本发明构思的技术的半导体封装件的封装件模块的示例的示图；
图29是示出包括应用本发明构思的技术的半导体封装件的电子装置的示例的框图；
图30是示出具有应用本发明构思的技术的半导体封装件的存储系统的框图。
具体实施方式
在下文中，将参照附图更充分地描述示例实施例，在附图中示出了示例实施例。然而，本发明可以以许多不同的形式来实施，且不应被解释为局限于这里阐述的实施例。相反，提供这些示例实施例使得该公开将是彻底和完整的，并将把本发明的范围充分地传达给本领域技术人员。在附图中，为了清晰起见，可夸大层和区域的大小和相对大小。
应该理解的是，当元件或层被称为“在”另一元件或层“上”或“连接到”另一元件或层或“结合到”另一元件或层时，它可以直接在另一元件或层上或直接连接到另一元件或层或直接结合到另一元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在”另一元件或层“上”、“直接连接到”另一元件或层或“直接结合到”另一元件或层时，不存在中间元件或层。相同的标号始终指示相同的元件。如在此使用的，术语“和/或”包含一个或者多个相关所列项目的任何和所有的组合。
应该理解的是，虽然术语第一、第二、第三等可以在此用来描述多种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应受到这些术语的限制。这些术语仅用来将一个元件、一个组件、一个区域、一个层或一个部分与另一区域、另一层或另一部分分开。因此，在不脱离本发明的教导的情况下，在下面讨论的第一元件、第一组件、第一区域、第一层或第一部分可被称作第二元件、第二组件、第二区域、第二层或第二部分。
为了描述方便，例如“在......下”、“在......下方”、“下面的”、“在......上方”和“上面的”等的空间相关术语，可在此用来描述如图所示的一个元件或者特征与其他的元件或者特征的关系。应该理解的是，除了附图中描述的方位以外，空间相关术语还旨在包括所述装置在使用或者操作中的不同方位。例如，如果在附图中的装置被翻转，则被描述为“在”其他元件或特征“下方”或“在”其他元件或特征“下”的元件将被定位为“在”其他元件或特征“上方”。因此，示例性术语“在......下方”可以包括在......上方和在......下方的两个方位。装置可以被另外定位(旋转90度或者在其他方位)，并相应地解释在此使用的空间相对描述符。
在此使用的术语仅是为了描述示例实施例的目的，且不是意在限制本发明。如在此使用的，除非上下文另有明确表示，否则单数形式也旨在包括复数形式。还应该理解的是，当在说明书中使用术语“包含”和/或“包括”时，明确了存在所述特征、整体、步骤、操作、元件，和/或组件，但不排除存在或者增加一个或者更多其他的特征、整体、步骤、操作、元件、组件和/或它们的组。
这里参照作为理想化的示例实施例(和中间结构)的示意图的剖视图来描述示例实施例。如此，预计会出现例如由制造技术和/或公差引起的示出的形状的变化。因此，示例实施例不应该被解释为局限于在此示出的区域的具体形状，而是应该包括例如由制造导致的形状的变形。例如，所示为矩形的注入区域在其边缘通常具有圆形或者弯曲的特征和/或注入浓度的梯度，而不是从注入区域到非注入区域的二元变化。同样，通过注入形成的埋置区域可导致在埋置区域和通过其发生注入的表面之间的区域中出现一定程度的注入。因此，在图中所示的区域在本质上是示意性的，它们的形状并不意图示出装置的区域的实际形状，也不意图限制本发明的范围。
除非另有定义，否则在此使用的所有术语(包括技术和科学术语)具有与本发明所属领域的普通技术人员所通常理解的意思相同的意思。还应该理解的是，除非这里明确定义，否则诸如在通用的字典中定义的术语应被解释为意思与他们在相关领域的上下文中的意思是一致，且不应理想化或过于正式地解释它们。
以下将参照附图更加详细地描述本发明构思的示例实施例。本发明构思可以以不同的形式来实施，且不应被解释为局限于这里阐述的示例实施例。相反，提供这些示例实施例使得该公开将是彻底和完整的，并将把本发明构思的范围充分地传达给本领域技术人员。在附图中，为了清楚起见，夸大了层和区域的大小。还应该理解的是，当层(或膜)被称为“在”另一层或基板“上”时，它可以直接在另一层或基板上，或者也可以存在中间层。此外，应该理解的是，当层被称为“在”另一层“之下”时，它可以直接位于之下，或者也可以存在一个或者多个中间层。此外，还应该理解的是，当层被称为“在”两层“之间”时，它可以是在所述两层之间的唯一的层，或者也可以是存在一个或多个中间层。相同的标号始终指示相同的元件。
<实施例1>
图1是根据本发明构思的第一示例实施例(实施例1)的半导体封装件的平面图。图2是沿图1的II-II’线截取的剖视图。
参照图1和图2，实施例1的半导体封装件300包括电路基板100和安装在电路基板100上的半导体芯片200。电路基板100包括基础基板1。基础基板1可以由双马来酰亚胺三嗪树脂(Bismaleimide triazine resin)、氧化铝基陶瓷(alumina based ceramic)、玻璃基陶瓷(glass based ceramic)、或者硅(silicon)形成。
基础基板1包括第一侧面2a和与第一侧面2a面对的第二侧面2b。基础基板1包括穿过第一侧面2a和第二侧面2b的通孔5。金属板3设置于第一侧面2a和第二侧面2b上，种子层7设置在金属板3和通孔5上。金属板3可以是铜板。例如，种子层7可以由非电镀图案形成。电镀图案9a、9b、9c和9d设置在种子层7上。电镀图案9a、9b、9c和9d可以包括基板连接端子9a，通孔金属图案9b，电路金属图案9c和球连接盘(ball land)9d。基板连接端子9a设置在第一侧面2a上并电连接至半导体芯片200的芯片连接端子122。通孔金属图案9b设置为覆盖通孔5的内侧壁。电路金属图案9c设置在第一侧面2a上并和基板连接端子9a电连接，以传递信号。球连接盘9d设置在第二侧面2b上，外部焊球40附着在球连接盘9d上。种子层7和电镀图案9a、9b、9c和9d可以包含铜。第一基板绝缘层13设置在第一侧面2a上，第二基板绝缘层17设置在第二侧面2b上。第一基板绝缘层13和第二基板绝缘层17可以对应于阻焊层，且可以由光敏的光致抗蚀剂层形成。第一基板绝缘层13包括暴露基板连接端子9a的基板连接端子开口15a。第一基板绝缘层13还可以包括虚设基板开口(dummy substrate opening)15b和15c。虚设基板开口15b和15c可包括通孔虚设开口15b和电路虚设开口15c，通孔虚设开口15b暴露通孔金属图案9b的预定部分，电路虚设开口15c暴露电路金属图案9c的预定部分。本示例实施例的电路虚设开口15c具有在平面上的矩形线形式，但是本发明构思不限于此，因此，电路虚设开口15c可以具有沿着电路金属图案9c的多种平面形式。第二基板绝缘层17可以包括暴露球连接盘9d的球连接盘开口19。虚设基板开口15b和15c填充有虚设焊料132b和132c。虚设焊料132b和132c包括通孔虚设焊料132b和电路虚设焊料132c。通孔虚设焊料132b填充通孔虚设开口15b，电路虚设焊料132c填充电路虚设开口15c。
在电路基板100上设置半导体芯片200。在半导体芯片200的底表面处设置芯片连接端子122。在半导体芯片200的底表面处安装具有暴露芯片连接端子122的芯片连接端子开口135a的芯片绝缘层124。芯片连接端子122设置在与基板连接端子9a重叠的部分。在芯片连接端子122与基板连接端子9a之间设置内部焊球133以便于内部焊球133将芯片连接端子122电连接至基板连接端子9a。虚设焊料132b和132c可由与内部焊球133相同的材料形成，所述相同的材料可以是金属，例如Pb、Sn、In、Bi、Sb、Ag或者它们的混合物。树脂层131设置在芯片绝缘层124和第一基板绝缘层13之间，以保护内部焊球133。在芯片绝缘层124中在与虚设焊料132b和132c叠置的位置没有设置开口。成型层42可以覆盖在电路基板100上的半导体芯片200。
图3到图8、图9A、10A和图12是示出根据本发明构思的示例实施例的具有图2的剖面的半导体封装件的顺序制造过程的制造剖视图。
参照图3，准备具有第一侧面2a和与第一侧面2a面对的第二侧面2b的基础基板1。将金属板3堆叠在基础基板1的第一侧面2a和第二侧面2b上。可以通过结合和/或压紧的方法将金属板3固定在基础基板1上。金属板3可以是铜板。可以执行半蚀刻工艺以减小金属板3的厚度。
参照图4，通过蚀刻和钻孔工艺形成穿过金属板3和基础基板1的通孔5。
参照图5，在具有通孔5的基础基板1上形成种子层7。可以通过非电镀方法形成种子层7。种子层7可以含有铜。将种子层7形成为覆盖在第一侧面2a和第二侧面2b上的金属板3以及通孔5的内侧壁上。
参照图6，在种子层7上形成电镀层9。可通过电镀覆方法形成电镀层9。电镀层9可以包含铜。在种子层7上形成电镀层9，从而在通孔5的内侧壁上也形成电镀层9。
参照图7，在电镀层9上覆盖干膜，在干膜上执行曝光和显影工艺，以形成干膜掩模11。干膜掩模11可以形成为覆盖通孔5。
参照图8，通过利用干膜掩模11作为蚀刻膜并蚀刻在干膜掩模11下的电镀层9，从而形成基板连接端子9a，通孔金属图案9b，电路金属图案9c，和球连接盘9d。同时蚀刻在电镀层9下的种子层7和金属板3，从而暴露基础基板1的表面。而后，去除干膜掩模11。可以通过湿蚀刻方法去除干膜掩模11。
图9B是图9A的A部分的放大透视图。
参照图9A和图9B，在基础基板1的第一侧面2a上形成第一基板绝缘层13，在第二侧面2b上形成第二基板绝缘层17。作为阻焊层的基板绝缘层13和基板绝缘层17可以由光敏的光致抗蚀剂形成，且也可以通过光刻工艺(photolithography process)形成。将第一基板绝缘层13形成为具有暴露基板连接端子9a的基板连接端子开口15a。将第一基板绝缘层13形成为包括虚设基板开口15b和15c。虚设基板开口15b和15c可以包括分别暴露通孔金属图案9b的预定部分和电路金属图案9c的预定部分的通孔虚设开口15b和电路虚设开口15c。可以将电路虚设开口15c形成为具有比电路金属图案9c的宽度W2宽的宽度W1，如图9B所示。因此，通过电路虚设开口15c可以暴露基础基板1的与电路金属图案9c的两个侧壁相邻的表面。此外，可以暴露电路金属图案9c的两个侧面。可以在第二基板绝缘层17中形成暴露球连接盘9d的球连接盘开口19。因此，可以完成电路基板100。
图10B是图10A的B部分的放大剖视图。
参照图10A、图10B和图12，在电路基板100上涂覆包括焊料颗粒132和粘结树脂130的混合物134。在混合物134中，可以以体积比约1∶9到约5∶5混合焊料颗粒132和粘结树脂130。例如，焊料颗粒132的直径可以为约0.1μm到约100μm。焊料颗粒132可以是诸如Cu、Pb、Sn、In、Bi、Sb、Ag以及它们的混合物的金属的颗粒。粘结树脂130可以具有焊剂的功能(fluxfunction)。一旦加热粘结树脂130，粘结树脂130可以具有去除在焊料颗粒132的表面上的氧化层的功能。粘结树脂130可以具有粘结功能。例如，粘结树脂130可以是环氧基树脂，作为更详细的示例，粘结树脂130可以包含双酚A(bisphenol A)和3-氯-1，2-环氢氧丙烷(epichlorohydrin)等。混合物134还可以包含还原剂、形变剂、溶剂和/或硬化剂。硬化剂可以是硅类、酚类、酸酐类和胺类。混合物134还可包含热凝剂、热塑剂和/或UV硬化材料。
和上面相同，在涂覆混合物134之后，在混合物134上设置半导体芯片200。而后，加热电路基板100。此时，按照高于焊料颗粒132的熔点的温度加热电路基板100。加热后的粘结树脂130可以去除焊料颗粒132的表面上的氧化层。此外，混合物134可以包含形变剂，形变剂可以抑制在混合物134中产生气体，从而形变剂有助于焊料颗粒132在金属表面上展现浸润特性。粘结树脂130在粘结树脂130的溶剂因加热工艺而蒸发之后硬化，从而可以形成树脂层131。此外，如图10B所示，在粘结树脂130中沿虚线箭头流动的焊料颗粒132移动至并附着到分别暴露于开口15a、15b和15c的金属图案(即，基板连接端子9a的表面、通孔金属图案9b的表面、电路金属图案9c的表面和芯片连接端子122的表面)。因此，在芯片连接端子122和基板连接端子9a之间形成内部焊球133。同时，没有变成将基板连接端子9a与芯片连接端子122连接的内部焊球133且余留在外围区域上的焊料颗粒132变成分别填充通孔虚设开口15b和电路虚设开口15c的通孔虚设焊料132b和电路虚设焊料132c。由于如图9B所示地以比电路金属图案9c的宽度W2宽的宽度W1来形成电路虚设开口15c，所以焊料颗粒132附着到暴露的电路金属图案9c的顶表面和两个侧壁。相应地，因为将电路虚设开口15c形成为具有比电路金属图案9c的宽度W2宽的宽度W1，所以焊料颗粒132附着到电路金属图案9c上的面积扩大。因此，可以解决诸如因余留的焊料颗粒导致的电短路和漏电流的限制，从而提供可靠的半导体封装件。此外，因为在虚设开口15b和15c中形成虚设焊料132b和132c来填充虚设开口15b和15c，所以它们没有过量地突出到第一基板绝缘层13的顶表面。因此，与在基板绝缘层上设置虚设焊料而没有虚设开口的情况相比，根据本发明构思，虚设焊料132b和132c的顶表面变得远离半导体芯片200。结果，可减轻诸如因耦合效应引起的信号干扰的影响。因此，可以实现可靠的半导体封装件。
接着，可以通过成型工艺形成成型层42。
图11A是示出根据本发明构思的另一示例实施例的具有图2的剖面的半导体封装件的制造剖视图。图11B是图11A的C部分的放大剖视图。
参照图11A，图11B和图12，混合多层134a(混合多层134a可以被称为焊料箔)设置在图9A的电路基板100上。混合多层134a包括焊料颗粒层132a和粘结树脂层130a，焊料颗粒层132a由焊料颗粒132(将参照图10A来描述)形成，粘结树脂层130a由设置在焊料颗粒层132a的两侧面上的粘结树脂130(将参照图10A来描述)形成。此外，在混合多层134a上设置半导体芯片200。加热电路基板100。粘结树脂层130a在其溶剂通过加热工艺而蒸发之后硬化，从而可形成树脂层131。此外，如图11B所示，在粘结树脂层130a中沿虚线箭头流动的焊料颗粒层132a移动至并附着到暴露于开口15a、15b和15c的金属图案(即，基板连接端子9a的表面、通孔金属图案9b的表面、电路金属图案9c的表面和芯片连接端子122的表面)。因此，在芯片连接端子122和基板连接端子9a之间形成内部焊球133。同时，没有变成将基板连接端子9a与芯片连接端子122连接的内部焊球133且余留在外围区域上的焊料颗粒层132a变成分别填充通孔虚设开口15b和电路虚设开口15c的通孔虚设焊料132b和电路虚设焊料132c。因此，可以解决诸如因余留的焊料颗粒导致的电短路和漏电流的限制，从而可以提供可靠的半导体封装件。此外，可以使用混合多层134a来执行用于更简单的倒装芯片键合的自组装焊料键合工艺(self-assembly solder bonding process)。
根据本发明构思的示例实施例，因为电路虚设开口15c形成用于暴露电路金属图案的预定部分(即，信号传输路径)，所以可以不需要专门形成虚设金属图案。因此，可以不需要改变电路基板的信号布线设计。因此，在不改变电路基板的信号布线设计的情况下，仅在期望的位置形成基板绝缘层的电路虚设开口，就可以实现可靠的半导体封装件。
<实施例2>
图13是根据本发明构思的第二示例实施例(实施例2)的半导体封装件的平面图。图14A是沿图13的XIVA-XIVA’线截取的剖视图。图14B是沿图13的XIVB-XIVB’线截取的剖视图。
参照图13、图14A和图14B，在根据实施例2的半导体封装件301中，在电路基板101的第一侧面2a上另外设置基板虚设金属图案9f和凹进金属图案9e。基板虚设金属图案9f可以设置在两个相邻的基板连接端子9a之间。凹进区域5a形成在电路基板101的基础基板1中，凹进金属图案9e设置在凹进区域5a中，从而填充凹进区域5a。凹进金属图案9e可以设置在两个相邻的基板连接端子9a之间和两个相邻的基板虚设金属图案9f之间。基板虚设金属图案9f和凹进金属图案9e的位置不限于此，且可以进行改变。第一基板绝缘层13设置在第一侧面2a上。基板连接端子开口15a和虚设开口15b、15c、15e和15f形成在第一基板绝缘层13中。虚设开口15b、15c、15e和15f可以包括通孔虚设开口15b，电路虚设开口15c，凹进虚设开口15e和基板虚设开口15f，其中，通孔虚设开口15b暴露通孔金属图案9b的预定部分，电路虚设开口15c暴露电路金属图案9c的预定部分，凹进虚设开口15e暴露凹进金属图案9e的预定部分，基板虚设开口15f暴露基板虚设金属图案9f的预定部分。虚设开口15b、15c、15e和15f可以分别填充有通孔虚设焊料132b，电路虚设焊料132c，凹进虚设焊料132e，基板虚设焊料132f。除此之外的构造与实施例1的构造相同/相似。
图15A到图19A是示出具有图14A的剖面的半导体封装件的顺序制造过程的制造剖视图。图15B到图19B是示出具有图14B的剖面的半导体封装件的顺序制造过程的制造剖视图。
参照图15A和图15B，准备包括第一侧面2a和与第一侧面2a面对的第二侧面2b的基础基板1。可以在基础基板1的第一侧面2a和第二侧面2b上堆叠金属板3。金属板3可以是铜板。可以执行半蚀刻工艺来减小金属板3的厚度。通过蚀刻和钻孔工艺形成穿过金属板3和基础基板1的通孔5。此时，通过去除金属板3和基础基板1的预定部分形成凹进区域5a。可以同时或分别形成通孔5和凹进区域5a。
参照图16A和图16B，在具有通孔5和凹进区域5a的基础基板1上形成种子层7。可以通过非电镀方法形成种子层7。种子层7可以包括铜。将种子层7形成为覆盖第一侧面2a和第二侧面2b、通孔5的内侧壁、凹进区域5a的内侧壁和底部上的金属板3。在种子层7上形成电镀层9。可通过电镀方法形成电镀层9。电镀层9可以包含铜。因为在种子层7上形成电镀层9，所以在通孔5的内侧壁和凹进区域5a的内侧壁和底部上形成电镀层9。
参照图17A和图17B，通过利用干膜掩模作为蚀刻掩模蚀刻电镀层9形成基板连接端子9a、通孔金属图案9b、电路金属图案9c、球连接盘9d、凹进金属图案9e和基板虚设金属图案9f。同时蚀刻在电镀层9下的种子层7和金属板3，从而暴露基础基板1的表面。而后，去除干膜掩模。
图18C是图18A的D部分的放大透视图。
参照图18A、图18B和图18C，在基础基板1的第一侧面2a上形成第一基板绝缘层13，在基础基板1的第二侧面2b上形成第二基板绝缘层17。作为阻焊层的基板绝缘层13和17可以由光敏的光致抗蚀剂形成，且也可以通过光刻工艺形成。将第一基板绝缘层13形成为具有暴露基板连接端子9a的基板连接端子开口15a。将第一基板绝缘层13形成为具有包括虚设基板开口15b、15c、15e和15f。虚设基板开口15b、15c、15e和15f可以包括分别暴露通孔金属图案9b的预定部分、电路金属图案9c的预定部分、凹进金属图案9e的预定部分和基板虚设金属图案9f的预定部分的通孔虚设开口15b、电路虚设开口15c、凹进虚设开口15e和基板虚设开口15f。如图18C所示，可以将基板虚设开口15f形成为具有比基板虚设金属图案9f的宽度W4宽的宽度W3。因此，可以通过基板虚设开口15f来暴露基础基板1的与基板虚设金属图案9f的两侧壁相邻的表面。此外，可以暴露基板虚设金属图案9f的三个侧面。可以在第二基板绝缘层17中形成暴露球连接盘9d的球连接盘开口19。至此，可以完成电路基板101。
参照图19A和图19B，在电路基板101上涂覆包括焊料颗粒132和粘结树脂130的混合物134。在涂覆混合物134之后，在混合物134上设置半导体芯片200。而后，加热电路基板101。此时，按照高于焊料颗粒132的熔点的温度加热电路基板101。因此，参照图14A和图14B，粘结树脂130在粘结树脂130的溶剂通过加热工艺而蒸发之后硬化，从而可以形成树脂层131。此外，在粘结树脂130中流动的焊料颗粒132移动至并附着到暴露于开口15a、15b、15c、15e和15f的金属图案(即，基板连接端子9a的表面、通孔金属图案9b的表面、电路金属图案9c的表面、凹进金属图案9e的表面、虚设金属图案9f的表面和芯片连接端子122的表面)。因此，在芯片连接端子122和基板连接端子9a之间形成内部焊球133。同时，没有变成将基板连接端子9a与芯片连接端子122连接的内部焊球133且仍然留在周围区域上的焊料颗粒132变成分别填充虚设开口15b、15c、15e、和15f的通孔虚设焊料132b、电路虚设焊料132c、凹进虚设焊料132e和基板虚设焊料132f。
如参照图11A所描述的，可以使用混合多层来执行自组装焊料键合工艺。其形成工艺可以与实施例1的形成工艺相同/类似。
在本示例实施例中，根据基板虚设金属图案和凹进金属图案的添加，电路基板的信号布线设计发生了改变。然而，根据本示例实施例，因为虚设开口形成在第一基板绝缘层中以允许虚设焊料填充虚设开口，所以可以实现在实施例1中描述的可靠的半导体封装件。
<实施例3>
图20是根据第三示例实施例(实施例3)的半导体封装件的剖视图。
参照图20，关于根据实施例3的半导体封装件302，芯片连接端子122和芯片虚设金属图案126设置在安装于电路基板102上的半导体芯片200的底表面处。而后，包括暴露芯片连接端子122的芯片连接端子开口135a和暴露芯片虚设金属图案126的芯片虚设开口135g的芯片绝缘层124设置在半导体芯片200的底表面处。芯片虚设开口135g填充有芯片虚设焊料132g。这可以是本示例实施例的特征。
选择性地，具有基板虚设金属图案132f和暴露基板虚设金属图案132f的基板虚设开口15f的第一基板绝缘层13可以设置在电路基板102上。芯片虚设开口135g和基板虚设开口15f的位置可以不相互叠置。第一基板绝缘层13不会暴露电路金属图案9c和通孔金属图案9b。与实施例2(实施例2中的通孔5填充有通孔虚设焊料132b)不同，跟据本示例实施例，通孔5可以填充有导电胶21。
本示例实施例的电路基板102可以被实施例1的电路基板100替代。除此之外的构造和生产方法可以与实施例1的构造和生产方法相同/相似。
<实施例4>
图21是根据本发明构思的第四示例实施例(实施例4)的半导体封装件的剖视图。
参照图21，关于根据本示例实施例的半导体封装件303，突起(bump)128附着在芯片连接端子122上，芯片连接端子122设置在半导体芯片200的底表面处，半导体芯片200安装在电路基板103上。将基板连接端子9a和芯片连接端子122电连接的内部焊球133形成为覆盖突起128的至少一个侧面。内部焊球133可以覆盖突起128的底部。
在半导体封装件303的形成工艺中的自组装焊料键合工艺期间，暴露突起128的侧面和底部，从而焊料颗粒附着的面积增加。因此，可以改善内部焊球133和突起128之间的粘结性。此外，因突起128的高度而可以均匀地保持半导体芯片200和电路基板103之间的间隔。因此，可以实现可靠的半导体封装件。在本示例实施例中，电路基板103可以与实施例2的电路基板101相同。除此之外的构造和制造方法可以与实施例1到实施例3的构造和制造方法相同/相似。
<实施例5>
图22是根据第五示例实施例(实施例5)的半导体封装件的剖视图。
参照图22，关于实施例5的半导体封装件304，两个以上的半导体芯片200和201堆叠和安装在电路基板104上。即，下部半导体芯片201堆叠在电路基板104上，而上部半导体芯片202堆叠在下部半导体芯片201上。穿过内部的过孔142可形成于下部半导体芯片201中。接触过孔142的底部的第一下部芯片连接端子146和暴露第一下部芯片连接端子146的第一下部芯片绝缘层148设置在下部半导体芯片201的底表面处。接触过孔142的顶部的第二下部芯片连接端子144和暴露第二下部芯片连接端子144的第二下部芯片绝缘层149设置在下部半导体芯片201的顶表面上。上部芯片连接端子122和上部芯片虚设金属图案126设置在上部半导体芯片202的底部处。此外，暴露上部芯片连接端子122和上部芯片虚设金属图案126的上部芯片绝缘层124设置在上部半导体芯片202的底部处。上部芯片虚设焊料152g附着至上部芯片虚设金属图案126。第一内部焊球133设置在电路基板104的基板连接端子9a和第一下部芯片连接端子146之间。第二内部焊球152a设置在上部芯片连接端子122和第二下部芯片连接端子144之间。
本示例实施例的电路基板104可以与如图14所示的电路基板101相同/相似。此外，芯片虚设金属图案126设置在半导体芯片202的底表面上，但是可以设置在下部半导体芯片201的顶表面或底表面处。当芯片虚设金属图案126设置在下部半导体芯片201的底表面处时，它可以设置在不与电路基板104的虚设开口15a、15b、15c和15f叠置的位置处。
图23到图26是示出根据本发明构思的示例实施例的具有图22的剖面的半导体封装件的顺序制造过程的制造剖视图。
参照图23，在电路基板104上设置第一混合多层134a。第一混合多层134a包括由图10A中的焊料颗粒132形成的第一焊料颗粒层132a和设置在第一焊料颗粒层132a的两侧处并由图10A中的粘结树脂130形成的第一粘结树脂层130a。此外，在第一混合多层134a上设置下部半导体芯片201。
参照图24，加热电路基板104。第一粘结树脂层130a在第一粘结树脂层130a的溶剂因加热工艺而蒸发之后硬化，从而可以形成第一树脂层131。第一焊料颗粒层132a移动到且附着至暴露于粘结树脂层130a中的开口15a、15b、15c和15f的金属图案(即，基板连接端子9a的表面、通孔金属图案9b的表面、电路金属图案9c的表面、基板虚设金属图案9f的表面和第一下部芯片连接端子146的表面)。因此，在第一下部芯片连接端子146和基板连接端子9a之间形成第一内部焊球133。同时，没有变成将基板连接端子9a与第一下部芯片连接端子146连接的第一内部焊球133且余留在外围区域上的焊料颗粒层132a变成分别填充虚设开口15b、15c、和15f的通孔虚设焊料132b、电路虚设焊料132c和基板虚设焊料132f。
参照图25，在下部半导体芯片201上设置第二混合多层154。第二混合多层154包括：第二焊料颗粒层152，由图10A的焊料颗粒132形成；第二粘结树脂层150，设置在第二焊料颗粒层152的两侧处，并由图10A的粘结树脂130形成。此外，在第二混合多层154上设置上部半导体芯片202。
参照图26，加热电路基板104。第二粘结树脂层150在第二粘结树脂层150的溶剂通过加热工艺而蒸发之后硬化，从而可以形成第二树脂层151。第二焊料颗粒层152移动到并附着至金属图案(即，第二下部芯片连接端子144的表面、上部芯片连接端子122的表面和上部芯片虚设金属图案126的表面)。因此，在第二下部芯片连接端子144和上部芯片连接端子122之间形成第二内部焊球152a，在上部芯片虚设金属图案126中形成上部芯片虚设焊料152g。
接下来，在附着外部焊球40和形成成型层42之后，可以完成具有图22的剖面的半导体封装件304。
图27是示出根据本发明构思的另一示例实施例的具有图22的剖面的半导体封装件的顺序制造过程的制造剖视图。
参照图27，在电路基板104上顺序叠置第一混合多层134a、下部半导体芯片201、第二混合多层154和上部半导体芯片202。之后，加热电路板104，从而可以更简单地生产具有图26的剖面的结构。
参照图10A、图10B和图12所描述的，虽然在本示例实施例的制造方法中使用混合多层，但是可以为了接下来的工艺而应用混合物134。当利用混合物134将下部半导体芯片201连接到上部半导体芯片202时，可以通过使混合物134硬化而使溶剂挥发时同时叠置下部半导体芯片201和上部半导体芯片202。
在实施例1到实施例5中的半导体封装件中，虽然在电路基板上安装半导体芯片，外部焊球40附着到电路基板，但是电路基板本身可以相当于母板，因而可以不附着外部焊球40。
半导体封装件技术可以应用于多种半导体装置和包括半导体装置的半导体模块。
图28是示出包括应用本发明构思的技术的半导体封装件的封装件模块的示例的示图。参照图28，封装件模块1200可以包括半导体集成电路芯片1220和应用半导体集成电路芯片的四面扁平封装件(QFP)1230。当在基板1210上安装应用本发明构思的半导体封装件技术的半导体装置1220和半导体装置1230时，可以形成封装件模块1200。封装件模块1200可以通过在基板1210的一侧处的外部连接端子1240连接到外部电子装置。
上面的半导体封装件技术可以应用于电子系统。图29是示出包括应用本发明构思的技术的半导体封装件的电子装置的示例的框图。参照图29，电子系统1300可以包括控制器1310、如键区、键盘和显示器的输入/输出装置(或I/O)1320和存储装置1330。可以通过总线1350结合控制器1310，输入/输出装置1320和存储装置1330。总线1350是数据传输所通过的路径。例如，控制器1310可以包括微处理器、数字信号处理器、微控制器、或者与它们相似的其他处理器中的至少一种。控制器1310和存储装置1330可以包括根据本发明构思的半导体封装件。输入/输出装置1320可以包括键盘、键区或者显示装置。存储装置1330存储数据。存储装置1330可以存储由控制器1310执行的数据和/或命令。存储装置1330可以包括易失性存储装置和/或非易失性存储装置。或者，存储装置1330可以由闪速存储器形成。例如，应用本发明构思的技术的闪速存储器可以安装在诸如移动装置或台式计算机的信息处理系统上。这样的闪速存储器可以包括半导体盘装置(SSD)。在这种情况下，电子系统1300可以在闪速存储器系统中稳定地存储大量数据。电子系统1300还可以包括用于将数据发送至网络或从网络接收数据的接口1340。接口1340可以是有线形式/无线形式。例如，接口1340可以包括天线或有线/无线收发器。虽然在附图中未示出，但是对本领域技术人员来说明显的是，电子系统1300还可以包括应用芯片组(application chipset)、相机图像处理器(CIS)以及输入/输出装置。
可以以移动系统、个人计算机、工业计算机或执行多种功能的系统来实现电子系统1300。例如移动系统可以是个人数字助理(PDA)、便携式计算机、网络平板机(web tablet)、移动电话、无线电话、膝上计算机、存储卡、数字音乐系统或信息发送/接收系统。如果电子系统1300是用于无线通信的装置，则电子系统1300可以使用第三代通信系统的通信界面协议，例如码分多址(CDMA)、全球移动通信系统(GSM)、增强时分多址(E-TDMA)、宽带码分多址(W-CDMA)和CDMA1000。
可以以存储卡的形式来设置应用本发明构思的技术的半导体装置。图30是示出具有应用本发明构思的技术的半导体封装件的存储系统的框图。参照图30，存储卡1400包括非易失性存储装置1410和存储控制器1420。非易失性存储装置1410和存储控制器1420可以存储数据或读取存储的数据。非易失性存储装置1410可以包括至少一个应用本发明构思的技术的非易失性存储装置。响应于来自主机的读/写请求，存储控制器1420可以控制闪速存储器装置1410读取已存储的数据或存储数据。存储卡1400可以与主机1430接口连接，主机1430可以利用存储卡1400来存储或取回数据。
根据本发明构思的示例实施例，基板绝缘层和芯片绝缘层中的至少一个层包括虚设开口。在用于倒装芯片键合的自组装焊料键合工艺期间，通过利用没有变成内部焊球且因此余留在外围区域上的焊料颗粒填充虚设开口来形成虚设焊料。因此，与在基板绝缘层上设置虚设焊料而没有虚设开口的情况相比，根据本发明的构思，虚设焊料的顶表面没有过量地突出，从而虚设焊料的顶表面变得远离半导体芯片。结果，可以减小诸如因耦合效应导致的信号干扰的影响。因此，可以解决例如因余留的焊料颗粒引起的电短路和泄露电流的限制，从而可以提供可靠的半导体封装件。
根据本发明构思的示例实施例，因为电路虚设开口形成为暴露电路金属图案的预定部分(即，信号传输路径)，所以可以不需要专门形成虚设金属图案。因此，可以不需要改变电路基板的信号布线设计。因此，在不改变电路基板的信号线设计的情况下，仅在期望的位置上形成基板绝缘层的虚设开口，从而可以实现可靠的半导体封装件。
上面公开的主题应该被认为是示意性的而非限制性的，并且权利要求旨在覆盖落入本发明构思的真正的精神和范围内的所有这样的修改、增强和其他的示例实施例。因此，在法律允许的最大程度上，本发明构思的范围是由权利要求及其等同物的最广泛的可允许的解释来确定的，而不应被限制或受限于上述的详细描述。

Claims (30)

1.一种半导体封装件，包括：
电路基板，包括基础基板、在基础基板上的基板连接端子和在基础基板上的基板绝缘层，基板绝缘层暴露基板连接端子；
第一半导体芯片，位于电路基板上，第一半导体芯片包括芯片连接端子和芯片绝缘层，芯片绝缘层暴露芯片连接端子；
内部焊球，在基板连接端子和芯片连接端子之间，内部焊球将基板连接端子电连接到芯片连接端子；
虚设焊料，在虚设开口中，虚设开口在基板绝缘层和芯片绝缘层中的至少一个层中，虚设焊料不将第一半导体芯片电连接到电路基板。
2.如权利要求1所述的半导体封装件，其中，
电路基板还包括通孔金属图案，通孔金属图案在穿透电路基板的通孔的内侧壁上，虚设开口在基板绝缘层中，虚设开口暴露通孔金属图案，虚设焊料接触通孔金属图案，虚设焊料至少部分地填充通孔。
3.如权利要求1所述的半导体封装件，其中，
电路基板还包括电路金属图案，电路金属图案电连接到基板连接端子，
基板绝缘层包括虚设开口，虚设开口暴露电路金属图案。
4.如权利要求3所述的半导体封装件，其中，虚设开口的宽度宽于电路金属图案的宽度。
5.如权利要求1所述的半导体封装件，其中，
电路基板还包括基板虚设金属图案，
基板绝缘层包括虚设开口，
虚设开口暴露基板虚设金属图案，
虚设焊料接触所述基板虚设金属图案。
6.如权利要求5所述的半导体封装件，其中，虚设开口的宽度宽于基板虚设金属图案的宽度。
7.如权利要求1所述的半导体封装件，其中，
电路基板还包括凹进金属图案，凹进金属图案在电路基板的凹进区域的侧壁和底部上，
基板绝缘层包括虚设开口，虚设开口暴露凹进金属图案，
虚设焊料接触凹进金属图案，虚设焊料至少部分地填充凹进区域。
8.如权利要求1所述的半导体封装件，其中，第一半导体芯片还包括芯片虚设金属图案，虚设开口在芯片绝缘层中，虚设开口暴露芯片虚设金属图案，虚设焊料接触芯片虚设金属图案。
9.如权利要求1所述的半导体封装件，其中，第一半导体芯片还包括突起，突起位于芯片连接端子上，所述内部焊球覆盖突起的至少一个侧面。
10.如权利要求1所述的半导体封装件，其中，第一半导体芯片还包括穿透第一半导体芯片的过孔。
11.如权利要求10所述的半导体封装件，所述半导体封装件还包括：
第二半导体芯片，位于第一半导体芯片上，其中，第二半导体芯片电连接到过孔。
12.一种制造半导体封装件的方法，该方法包括下述步骤：
形成包括基础基板、在基础基板上的基板连接端子和覆盖基础基板并暴露基板连接端子的基板绝缘层的电路基板；
在电路基板上形成混合物层，混合物层包含粘结树脂和多个焊料颗粒；
在混合物层上设置第一半导体芯片，第一半导体芯片包括芯片连接端子和暴露芯片连接端子的芯片绝缘层；
在基板连接端子和芯片连接端子之间形成内部焊球；
在虚设开口中形成虚设焊料，虚设开口在基板绝缘层和芯片绝缘层中的一个层中。
13.如权利要求12所述的方法，其中，焊料颗粒分散在粘结树脂中。
14.如权利要求12所述的方法，其中，形成混合物层的步骤包括设置包括由粘结树脂形成的粘结树脂层和由焊接颗粒形成的焊接颗粒层的混合多层。
15.如权利要求12所述的方法，其中，形成内部焊球的步骤包括：将混合物层加热到高于焊料颗粒的熔点的温度。
16.如权利要求12所述的方法，其中，形成电路基板的步骤包括：
准备基础基板；
在基础基板上形成基板连接端子；
在基础基板上形成基板绝缘层，将基板绝缘层形成为暴露基板连接端子。
17.如权利要求16所述的方法，所述方法还包括下述步骤：
在基础基板上形成电路金属图案，其中，基板绝缘层包括虚设开口，虚设开口暴露电路金属图案。
18.如权利要求17所述的方法，其中，虚设开口的宽度比电路金属图案的宽度宽。
19.如权利要求16所述的方法，所述方法还包括下述步骤：
通过图案化基础基板来形成通孔；
在通孔的侧壁上形成通孔金属图案，其中，基板绝缘层包括虚设开口，虚设开口暴露通孔金属图案。
20.如权利要求16所述的方法，所述方法还包括下述步骤：
在基础基板中形成凹进区域；
形成覆盖凹进区域的侧壁和底部的凹进金属图案，
其中，将基板绝缘层形成为具有暴露凹进金属图案的虚设开口。
21.如权利要求16所述的方法，所述方法还包括下述步骤：
在基础基板上形成基板虚设金属图案，其中，将基板绝缘层形成为具有虚设开口，并将虚设开口形成为暴露基板虚设金属图案。
22.如权利要求21所述的方法，其中，将虚设开口形成为具有比基板虚设金属图案的宽度宽的宽度。
23.如权利要求12所述的方法，所述方法还包括下述步骤：
在第一半导体芯片上形成上部混合物层；
在上部混合物层上设置第二半导体芯片，第二半导体芯片包括上部芯片连接端子和暴露上部芯片连接端子的上部芯片绝缘层；
在芯片连接端子和上部芯片连接端子之间形成上部内部焊球。
24.如权利要求23所述的方法，其中，同时执行形成内部焊球的步骤和形成上部内部焊球的步骤。
25.一种制造半导体封装件的方法，该方法包括下述步骤：
在半导体芯片的绝缘层和基板的绝缘层中的至少一个层中形成至少一个虚设开口；
在基板和半导体芯片之间形成内部焊球，内部焊球将半导体芯片的芯片连接端子电连接到基板的基板连接端子；
在所述至少一个虚设开口中形成虚设焊料，虚设焊料不将基板电连接至半导体芯片。
26.如权利要求25所述的方法，所述方法还包括下述步骤：
在基板上形成电路金属图案、通孔金属图案以及虚设基板金属图案中的至少一种图案，其中，
将所述至少一个虚设开口形成为暴露电路金属图案、通孔金属图案和虚设基板金属图案中的至少一种图案。
27.如权利要求25所述的方法，所述方法还包括下述步骤：
在基板上形成电路金属图案、通孔金属图案和虚设基板金属图案，其中，
所述至少一个虚设开口是形成为暴露电路金属图案、通孔金属图案和虚设基板金属图案的多个虚设开口。
28.如权利要求25所述的方法，所述方法还包括下述步骤：
在基板上形成混合物层，混合物层包含粘结树脂和多个焊料颗粒，其中，
通过加热混合物层来同时形成内部焊球和虚设焊料。
29.如权利要求28所述的方法，其中，焊料颗粒分散在粘结树脂中。
30.如权利要求28所述的方法，其中，形成混合物层的步骤包括设置包括由粘结树脂形成的粘结树脂层和由焊料颗粒形成的焊料颗粒层的混合多层。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515336A (zh) * 2012-06-27 2014-01-15 英飞凌科技股份有限公司 芯片封装、芯片布置、电路板以及用于制造芯片封装的方法
CN103533218A (zh) * 2012-06-29 2014-01-22 Lg伊诺特有限公司 相机模块
CN103715165A (zh) * 2012-10-02 2014-04-09 矽品精密工业股份有限公司 半导体封装件及其制法
CN105280834A (zh) * 2014-06-13 2016-01-27 思鹭科技股份有限公司 封装结构以及封装结构的制作方法
CN105744740A (zh) * 2014-12-29 2016-07-06 三星电机株式会社 印刷电路板及其制造方法
CN113130457A (zh) * 2019-12-31 2021-07-16 Tcl集团股份有限公司 光源板及其制备方法和显示器

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9553040B2 (en) 2012-03-27 2017-01-24 Mediatek Inc. Semiconductor package
JP2014072494A (ja) * 2012-10-01 2014-04-21 Toshiba Corp 半導体装置及びその製造方法
KR20140081193A (ko) * 2012-12-21 2014-07-01 삼성전기주식회사 고밀도 및 저밀도 기판 영역을 구비한 하이브리드 기판 및 그 제조방법
KR102111739B1 (ko) * 2013-07-23 2020-05-15 삼성전자주식회사 반도체 패키지 및 그 제조방법
TWI514530B (zh) * 2013-08-28 2015-12-21 Via Tech Inc 線路基板、半導體封裝結構及線路基板製程
KR101665242B1 (ko) 2015-03-20 2016-10-11 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이의 제조 방법
KR102732538B1 (ko) * 2020-06-08 2024-11-19 삼성전자주식회사 반도체 패키지

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020059A (en) * 1997-07-24 2000-02-01 Sony Chemicals Corporation Multilayer anisotropic electroconductive adhesive and method for manufacturing same
US20090057378A1 (en) * 2007-08-27 2009-03-05 Chi-Won Hwang In-situ chip attachment using self-organizing solder
WO2009044695A1 (ja) * 2007-10-05 2009-04-09 Nec Corporation 電子部品の実装方法等
US20090230546A1 (en) * 2005-03-07 2009-09-17 Matsushita Electric Industrial Co., Ltd Mounted body and method for manufacturing the same
JP4401411B2 (ja) * 2005-03-17 2010-01-20 パナソニック株式会社 半導体チップを備えた実装体およびその製造方法
US20100059872A1 (en) * 2006-08-25 2010-03-11 Satoru Katsurayama Adhesive Tape, Connected Structure and Semiconductor Package
US20100244283A1 (en) * 2009-03-24 2010-09-30 Panasonic Corporation Method of joining electronic component and the electronic component

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006080333A (ja) * 2004-09-10 2006-03-23 Toshiba Corp 半導体装置
JP3955302B2 (ja) 2004-09-15 2007-08-08 松下電器産業株式会社 フリップチップ実装体の製造方法
JP4402717B2 (ja) * 2005-03-16 2010-01-20 パナソニック株式会社 導電性粒子を用いたフリップチップ実装方法およびバンプ形成方法
US7215026B2 (en) * 2005-04-14 2007-05-08 Samsung Electonics Co., Ltd Semiconductor module and method of forming a semiconductor module
WO2006123554A1 (ja) 2005-05-17 2006-11-23 Matsushita Electric Industrial Co., Ltd. フリップチップ実装体およびフリップチップ実装方法
JP4887997B2 (ja) 2006-09-19 2012-02-29 日本電気株式会社 電子部品の実装方法
KR101079946B1 (ko) * 2006-11-28 2011-11-04 파나소닉 주식회사 전자 부품 실장 구조체와 그 제조 방법
KR100842921B1 (ko) * 2007-06-18 2008-07-02 주식회사 하이닉스반도체 반도체 패키지의 제조 방법
US8338945B2 (en) * 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020059A (en) * 1997-07-24 2000-02-01 Sony Chemicals Corporation Multilayer anisotropic electroconductive adhesive and method for manufacturing same
US20090230546A1 (en) * 2005-03-07 2009-09-17 Matsushita Electric Industrial Co., Ltd Mounted body and method for manufacturing the same
JP4401411B2 (ja) * 2005-03-17 2010-01-20 パナソニック株式会社 半導体チップを備えた実装体およびその製造方法
US20100059872A1 (en) * 2006-08-25 2010-03-11 Satoru Katsurayama Adhesive Tape, Connected Structure and Semiconductor Package
US20090057378A1 (en) * 2007-08-27 2009-03-05 Chi-Won Hwang In-situ chip attachment using self-organizing solder
WO2009044695A1 (ja) * 2007-10-05 2009-04-09 Nec Corporation 電子部品の実装方法等
US20100244283A1 (en) * 2009-03-24 2010-09-30 Panasonic Corporation Method of joining electronic component and the electronic component

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515336A (zh) * 2012-06-27 2014-01-15 英飞凌科技股份有限公司 芯片封装、芯片布置、电路板以及用于制造芯片封装的方法
US9859198B2 (en) 2012-06-27 2018-01-02 Infineon Technologies Ag Chip packages, chip arrangements, a circuit board, and methods for manufacturing chip packages
CN103533218A (zh) * 2012-06-29 2014-01-22 Lg伊诺特有限公司 相机模块
CN103533218B (zh) * 2012-06-29 2018-04-10 Lg伊诺特有限公司 相机模块
CN103715165A (zh) * 2012-10-02 2014-04-09 矽品精密工业股份有限公司 半导体封装件及其制法
CN103715165B (zh) * 2012-10-02 2018-02-02 矽品精密工业股份有限公司 半导体封装件及其制法
CN105280834A (zh) * 2014-06-13 2016-01-27 思鹭科技股份有限公司 封装结构以及封装结构的制作方法
CN105744740A (zh) * 2014-12-29 2016-07-06 三星电机株式会社 印刷电路板及其制造方法
CN113130457A (zh) * 2019-12-31 2021-07-16 Tcl集团股份有限公司 光源板及其制备方法和显示器

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