CN102456607A - Manufacturing method for shallow trench isolation structure - Google Patents
Manufacturing method for shallow trench isolation structure Download PDFInfo
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- CN102456607A CN102456607A CN2010105186348A CN201010518634A CN102456607A CN 102456607 A CN102456607 A CN 102456607A CN 2010105186348 A CN2010105186348 A CN 2010105186348A CN 201010518634 A CN201010518634 A CN 201010518634A CN 102456607 A CN102456607 A CN 102456607A
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Abstract
The invention provides a manufacturing method for a shallow trench isolation structure. The manufacturing method comprises the following steps of: providing a semiconductor substrate, wherein a buffer oxide layer and an etching barrier layer are formed on the semiconductor substrate, and a trench opening is formed in the buffer oxide layer and the etching barrier layer; etching the semiconductor substrate along the trench opening by taking the buffer oxide layer and the etching barrier layer as a mask to form a shallow trench in the semiconductor substrate; repairing and annealing the shallow trench; sequentially filling a pad oxide layer and an insulating oxide layer in the shallow trench; and removing the etching barrier layer and the buffer oxide layer to form the shallow trench isolation structure. By the method, the problem that the sidewall and bottom of the trench are rough after the shallow trench is etched is solved, and the isolation effect of the shallow trench isolation structure is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the manufacture method of fleet plough groove isolation structure.
Background technology
In 0.18 micron and following semiconductor fabrication process, the isolation structure between the semiconductor device adopts fleet plough groove isolation structure (STI) usually.The manufacture method of existing fleet plough groove isolation structure please refer to Fig. 1 to Fig. 4.
At first; Please refer to Fig. 1, Semiconductor substrate 100 is provided, be formed with buffer oxide layer 102, etching barrier layer 104 on the said Semiconductor substrate 100 successively; Be formed with groove opening 120 in said buffer oxide layer 102 and the etching barrier layer 104, said groove opening 120 has defined the position of shallow trench.
Then, please refer to Fig. 2, is mask with said buffer oxide layer 102 with etching barrier layer 104, along the said Semiconductor substrate 100 of said groove opening 120 etchings, in said Semiconductor substrate 100, forms shallow trench 110.
Then, please refer to Fig. 3, in shallow trench 110, form cushion oxide layer 112, the material of said cushion oxide layer 112 is a silica; Method (HDPCVD) with high density plasma CVD forms insulating oxide 114 on said etching barrier layer 104, and insulating oxide 114 is filled full shallow trench 110; Insulating oxide 114 is carried out planarization.
At last,, remove etching barrier layer 104 and buffering oxide layer 102, form the fleet plough groove isolation structure 115 that constitutes by cushion oxide layer 112 and insulating oxide 114 with reference to figure 4.
, number of patent application can find more information relevant in being 200710094466.2 one Chinese patent application, the formation fleet plough groove isolation structure with technique scheme.
Find that in reality the isolation effect of the fleet plough groove isolation structure that technique scheme forms is undesirable, makes device have leakage current, has influenced the performance of device.
Summary of the invention
The technical problem that the present invention solves has provided a kind of manufacture method of fleet plough groove isolation structure, has improved the isolation effect of fleet plough groove isolation structure, has reduced the leakage current of device, has improved the performance of device.
In order to address the above problem, the present invention provides a kind of manufacture method of fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided, is formed with buffer oxide layer, etching barrier layer on the said Semiconductor substrate, be formed with groove opening in said buffer oxide layer and the etching barrier layer;
With said buffer oxide layer and etching barrier layer is mask, along the said Semiconductor substrate of said groove opening etching, in said Semiconductor substrate, forms shallow trench;
Said shallow trench is repaired annealing;
In said shallow trench, fill cushion oxide layer and insulating oxide successively;
Remove said etching barrier layer and buffering oxide layer, form fleet plough groove isolation structure.
Alternatively, said reparation is annealed into rapid thermal annealing.
Alternatively, the gas of said reparation annealing is hydrogen, and its range of flow is 10～1000sccm.
Alternatively, the temperature range of said reparation annealing is 800～1200 degrees centigrade.
Alternatively, the pressure limit of said reparation annealing is 10～70 holders.
Alternatively, the time of said reparation annealing is 1～120 second.
Alternatively, the heating rate of said annealing is 5～150 degrees centigrade/second.
Alternatively, the rate of temperature fall of said annealing is-5～-150 degrees centigrade/second.
Alternatively, the material of said buffer oxide layer is a silica, and the material of etching barrier layer is a silicon nitride, and said cushion oxide layer is a silica with the material of buffering oxide layer.
Compared with prior art, the invention provides the Semiconductor substrate that is formed with shallow trench, said shallow trench is repaired annealing; Repaired because the defective that etching technics causes in the sidewall and the bottom of shallow trench has been improved the roughness of shallow trench sidewall and bottom, made that follow-up liner oxidation layer thickness is even; Form reliable fleet plough groove isolation structure; Improve the isolation effect of fleet plough groove isolation structure, reduced the leakage current of device, improved the performance of device.
Description of drawings
Fig. 1～Fig. 4 is the shallow groove isolation structure manufacturing method cross-sectional view of prior art.
Fig. 5 is a shallow groove isolation structure manufacturing method schematic flow sheet of the present invention.
Fig. 6～Fig. 9 is a shallow groove isolation structure manufacturing method cross-sectional view of the present invention.
Figure 10 is the pattern sketch map of groove before annealing is repaired.
Figure 11 is the pattern sketch map that the back groove is repaired in annealing.
Embodiment
The inventor finds that the isolation effect of the fleet plough groove isolation structure that existing method is made is undesirable, makes device have leakage current.The unfavorable reason of isolation effect that causes fleet plough groove isolation structure is because Semiconductor substrate is carried out etching when forming shallow trench; Damaged the silicon of trenched side-wall and bottom; Make the silicon of trenched side-wall and bottom produce a large amount of dangling bonds; Cause shallow trench sidewall and bottom rough, made that the cushion oxide layer of follow-up filling is in uneven thickness, influenced the isolation effect of fleet plough groove isolation structure.
The inventor proposes a kind of manufacture method of shallow trench through creative work, with reference to figure 5, is shallow groove isolation structure manufacturing method schematic flow sheet of the present invention.Said method comprises:
Step S1 provides Semiconductor substrate, is formed with buffer oxide layer, etching barrier layer on the said Semiconductor substrate, is formed with groove opening in said buffer oxide layer and the etching barrier layer;
Step S2 is a mask with said buffer oxide layer and etching barrier layer, along the said Semiconductor substrate of said groove opening etching, in said Semiconductor substrate, forms shallow trench;
Step S3 repairs annealing to said shallow trench;
Step S4 fills cushion oxide layer and insulating oxide successively in said shallow trench;
Step S5 removes said etching barrier layer and buffering oxide layer, forms fleet plough groove isolation structure.
To combine specific embodiment that technical scheme of the present invention is carried out detailed explanation below.
At first,, Semiconductor substrate 200 is provided, is formed with buffer oxide layer 202, etching barrier layer 204 on the said Semiconductor substrate 200, be formed with groove opening 220 in said buffer oxide layer 202 and the etching barrier layer 204 with reference to figure 6.
Said Semiconductor substrate 200 can be silicon or silicon-on-insulator (SOI).
Said buffer oxide layer 202 is used to reduce the stress between Semiconductor substrate 200 and the etching barrier layer 204.As an embodiment, the material of said buffer oxide layer 202 is a silica.As other embodiment, said buffer oxide layer 202 can also be fluorine silex glass (FSG), a kind of or its combination in phosphorosilicate glass (PSG), Pyrex (BSG) or the boron-phosphorosilicate glass (BPSG).Said buffer oxide layer 202 can utilize low-pressure chemical vapor deposition (LPCVD), high density plasma CVD (HDPCVD) or plasma enhanced chemical vapor deposition equipment such as (PECVD) to obtain.
The material of said etching barrier layer 204 selects to have with buffer oxide layer 202 material of different etching speed.As an embodiment, the material of said etching barrier layer 204 is a silicon nitride, can utilize low-pressure chemical vapor deposition (LPCVD) equipment, under the condition of high temperature (for example 600～900 degrees centigrade), by reaction generates the silicon nitride acquisition with dichlorosilane on schedule.
Usually, after forming said buffer oxide layer 202 and etching barrier layer 204, need carry out etching technics, in said buffer oxide layer 202 and etching barrier layer 204, form groove opening 220.
Said groove opening 220 is used to define the position of shallow trench, and the Semiconductor substrate 200 that said groove opening 220 is exposed will be removed in follow-up etch step, to form shallow trench.
Then, with reference to figure 7, be mask with etching barrier layer 204 with said buffer oxide layer 202, along the said Semiconductor substrate 200 of said groove opening 220 etchings, in said Semiconductor substrate 200, form shallow trench 210.
Said etching is anisotropic plasma etching, and for example said etching can be with the mist of hydrogen bromide, helium, oxygen and the sulphur hexafluoride plasma etching as etching gas.Wherein the range of flow of hydrogen bromide can be 10～50sccm, for example is 30sccm, and the flow of helium-oxygen gas mixture body is 30～50sccm, and distance is 37sccm for example, and the flow of sulphur hexafluoride is 4～10sccm, for example is 6sccm.The pressure of etching is 10～20mTorr, for example is 15mTorr, and the power that adopts during etching can 800～1500W, for example is 1200W; 300V during etching voltage, the time of etching is 4～30 seconds, for example is 9 seconds.
Because plasma etching has damaged the sidewall of shallow trench 210 and the silicon of bottom, makes the semiconductor substrate surface of shallow trench 210 sidewalls and bottom produce the dangling bonds of a large amount of silicon, has caused shallow trench 210 sidewalls and bottom rough.Because cushion oxide layer utilizes oxidation technology usually, promptly under the environment of high temperature, aerating oxygen utilizes the pasc reaction of interior (sidewall and the bottom) Semiconductor substrate of oxygen and groove, in groove, forms silica.Said oxidation technology meeting consume silicon; Not only can not improve the trenched side-wall of etching groove generation and the coarse situation of bottom; And, make that the silicon oxide layer that forms is follow-up inhomogeneous because the sidewall and the bottom of groove are comparatively coarse, influence the isolation effect of fleet plough groove isolation structure.
In order to eliminate the damage that plasma etching causes Semiconductor substrate, said shallow trench 210 is repaired annealing.Said reparation annealing can be annealed for boiler tube, also can be rapid thermal annealing (RTP).
The inventor finds that heating rate and rate of temperature fall during annealing are influential to repairing effect, and promptly heating rate and rate of temperature fall are big more, and the effect of repairing semiconductor substrate is good more, and the sidewall and the bottom of the shallow trench 210 after the reparation are smooth more.Because therefore the heating rate of boiler tube annealing and rate of temperature fall, as preferred embodiment, utilize rapid thermal annealing that shallow trench 210 is repaired annealing all less than the heating rate and the rate of temperature fall of rapid thermal annealing.The heating rate of said annealing is 5～150 degrees centigrade/second, and the rate of temperature fall of said annealing is-5～-150 degrees centigrade/second.And said annealing is not carried out before in groove, filling cushion oxide layer and insulating oxide, and trenched side-wall and bottom because the defective that etching forms is eliminated, are formed smooth trenched side-wall and bottom, more helps the deposition of cushion oxide layer.With fill cushion oxide layer and insulating oxide in the groove after anneal and compare, the adhesion effect of cushion oxide layer and trenched side-wall and bottom is good, the isolation effect of the shallow trench of formation is good.
As preferred embodiment, utilize the gas of hydrogen as annealing.Because the molecule of hydrogen have volume little, in light weight, have a bigger mean free path; When heating, can in Semiconductor substrate, spread; The molecule of hydrogen is brought great amount of heat into Semiconductor substrate, and the silicon of Semiconductor substrate moves under the environment of hydrogen, and lattice is arranged again; Reduce the dangling bonds that form owing to etching, improve the coarse phenomenon of sidewall and bottom of shallow trench 210.
In the present embodiment, the range of flow of said hydrogen is 10～1000sccm, is preferably 50～800sccm.Because hydrogen has inflammable and explosive property; In reality, carry out and repair before the annealing steps; Need promptly feed the cavity of repairing annealing, certain time to the cavity of the board of repairing annealing to cleaning with high-purity nitrogen or inert gas; So that the residual oxygen in the said cavity is got rid of, guarantee the safety of technology.As preferred embodiment, the range of flow of said nitrogen is 100～1000sccm, and cleaning continues 5～50 seconds.After cleaning was accomplished, the Semiconductor substrate 200 that will have shallow trench 210 was positioned over the cavity of repairing annealing, repairs annealing.
The temperature range of said reparation annealing is 800～1200 degrees centigrade.The temperature of repairing annealing is high more, and the effect of repairing annealing is good more.Temperature is high more, and hydrogen diffusion Shaoxing opera is strong, and more hydrogen diffuses in the Semiconductor substrate 200, and the effect of reparation is good more.
As preferred embodiment, the pressure limit of said reparation annealing is 10～70 holders.The pressure of repairing annealing is more little, and the migration velocity of silicon atom is fast more, and the sidewall of shallow trench and the repairing effect of bottom are good more.As an embodiment, the time of said reparation annealing is 1～120 second.In reality, those skilled in the art can select as required.
Then, with reference to figure 8, in said shallow trench 210, fill cushion oxide layer 212 and insulating oxide 214 successively.As an embodiment, the material of said cushion oxide layer 212 is a silica, and its formation method is an oxidation technology; Promptly under the environment of high temperature; Aerating oxygen utilizes the pasc reaction of (sidewall and bottom) Semiconductor substrate in oxygen and the shallow trench, in groove, forms silica.Because the sidewall and the bottom of annealed shallow trench 210 are smooth, the thickness of the cushion oxide layer 212 of formation is even, thereby has improved the isolation effect of the fleet plough groove isolation structure of final formation, has reduced the leakage current of device.
After forming said cushion oxide layer 212, need in groove 210, fill insulating oxide 214.The material of said insulating oxide 214 is a silica, and its formation method is the high density plasma chemical vapor deposition method.Usually; Silicon oxide layer so that the high density plasma chemical vapor deposition method forms can be filled full shallow trench 210 and covered said etching barrier layer 204; Need carry out flatening process afterwards; Removal is positioned at the silicon oxide layer of etching barrier layer 204 tops, the final insulating oxide 214 of filling full shallow trench 210 that forms.
At last,, remove said etching barrier layer 204 and buffering oxide layer 202, form fleet plough groove isolation structure 215 with reference to figure 9.The method of removing said etching barrier layer 204 and buffering oxide layer 202 can be dry etching or wet etching, and is identical with prior art, as those skilled in the art's known technology, do not do detailed explanation at this.
To repair the improvement of annealing in order explaining, to please refer to Figure 10 and Figure 11 the roughness of the sidewall of shallow trench and bottom.Wherein Figure 10 is for before repairing annealing, and the pattern sketch map of shallow trench, Figure 11 are after repairing annealing, the pattern sketch map of shallow trench.From figure, find out that obviously after the reparation annealing, the sidewall and the bottom of obvious more preceding than the reparation annealing shallow trench of the sidewall of shallow trench and bottom are smooth.
To sum up; The present invention provides through shallow trench is annealed; Eliminated etching technics to the damage that Semiconductor substrate causes, improved the rough surface in the shallow trench, made that the liner oxidation layer thickness in the shallow trench is even; Improve the isolation effect of fleet plough groove isolation structure, reduced the leakage current of device.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (9)
1. the manufacture method of an a kind of fleet plough groove isolation structure is characterized in that, comprising:
Semiconductor substrate is provided, is formed with buffer oxide layer, etching barrier layer on the said Semiconductor substrate, be formed with groove opening in said buffer oxide layer and the etching barrier layer;
With said buffer oxide layer and etching barrier layer is mask, along the said Semiconductor substrate of said groove opening etching, in said Semiconductor substrate, forms shallow trench;
Said shallow trench is repaired annealing;
In said shallow trench, fill cushion oxide layer and insulating oxide successively;
Remove said etching barrier layer and buffering oxide layer, form fleet plough groove isolation structure.
2. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, said reparation is annealed into rapid thermal annealing.
3. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the gas of said reparation annealing is hydrogen, and its range of flow is 10～1000sccm.
4. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the temperature range of said reparation annealing is 800～1200 degrees centigrade.
5. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the pressure limit of said reparation annealing is 10～70 holders.
6. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the time of said reparation annealing is 1～120 second.
7. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the heating rate of said annealing is 5～150 degrees centigrade/second.
8. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the rate of temperature fall of said annealing is-5～-150 degrees centigrade/second.
9. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the material of said buffer oxide layer is a silica, and the material of etching barrier layer is a silicon nitride, and said cushion oxide layer is a silica with the material of buffering oxide layer.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022018A (en) * | 2014-06-19 | 2014-09-03 | 无锡宏纳科技有限公司 | Dry etching plasma damage repair technology |
| CN108022831A (en) * | 2016-11-03 | 2018-05-11 | 无锡华润上华科技有限公司 | Groove preparation method and semiconductor device preparation method |
| CN110379763A (en) * | 2019-07-25 | 2019-10-25 | 德淮半导体有限公司 | The forming method of groove isolation construction and imaging sensor |
| CN110504156A (en) * | 2018-05-17 | 2019-11-26 | 美光科技公司 | Method for reducing silicon consumption, the method for forming semiconductor structure, and the method for forming isolation structure |
| CN111613570A (en) * | 2019-02-25 | 2020-09-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN113113436A (en) * | 2021-03-18 | 2021-07-13 | 华虹半导体(无锡)有限公司 | Manufacturing method of CIS deep trench epitaxial layer |
| CN113725149A (en) * | 2021-08-30 | 2021-11-30 | 长江存储科技有限责任公司 | Material filling method, semiconductor structure and 3D NAND memory |
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| US5895252A (en) * | 1994-05-06 | 1999-04-20 | United Microelectronics Corporation | Field oxidation by implanted oxygen (FIMOX) |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022018A (en) * | 2014-06-19 | 2014-09-03 | 无锡宏纳科技有限公司 | Dry etching plasma damage repair technology |
| CN108022831A (en) * | 2016-11-03 | 2018-05-11 | 无锡华润上华科技有限公司 | Groove preparation method and semiconductor device preparation method |
| CN108022831B (en) * | 2016-11-03 | 2021-06-04 | 无锡华润上华科技有限公司 | Groove preparation method and semiconductor device preparation method |
| CN110504156A (en) * | 2018-05-17 | 2019-11-26 | 美光科技公司 | Method for reducing silicon consumption, the method for forming semiconductor structure, and the method for forming isolation structure |
| CN111613570A (en) * | 2019-02-25 | 2020-09-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111613570B (en) * | 2019-02-25 | 2023-09-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110379763A (en) * | 2019-07-25 | 2019-10-25 | 德淮半导体有限公司 | The forming method of groove isolation construction and imaging sensor |
| CN113113436A (en) * | 2021-03-18 | 2021-07-13 | 华虹半导体(无锡)有限公司 | Manufacturing method of CIS deep trench epitaxial layer |
| CN113725149A (en) * | 2021-08-30 | 2021-11-30 | 长江存储科技有限责任公司 | Material filling method, semiconductor structure and 3D NAND memory |
| CN113725149B (en) * | 2021-08-30 | 2023-10-10 | 长江存储科技有限责任公司 | Material filling method, semiconductor structure and 3D NAND memory |
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