CN102222636A - Manufacturing method of shallow trench isolation - Google Patents
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- CN102222636A CN102222636A CN2010101548034A CN201010154803A CN102222636A CN 102222636 A CN102222636 A CN 102222636A CN 2010101548034 A CN2010101548034 A CN 2010101548034A CN 201010154803 A CN201010154803 A CN 201010154803A CN 102222636 A CN102222636 A CN 102222636A
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- 238000002955 isolation Methods 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 71
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000000137 annealing Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 112
- 238000005516 engineering process Methods 0.000 claims description 33
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 18
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000010276 construction Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical class FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 8
- 230000008901 benefit Effects 0.000 abstract description 4
- 230000000873 masking effect Effects 0.000 abstract 3
- 239000012300 argon atmosphere Substances 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000009931 harmful effect Effects 0.000 description 4
- 238000005498 polishing Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000003595 mist Substances 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 101000911390 Homo sapiens Coagulation factor VIII Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- GWUAFYNDGVNXRS-UHFFFAOYSA-N helium;molecular oxygen Chemical compound [He].O=O GWUAFYNDGVNXRS-UHFFFAOYSA-N 0.000 description 1
- 102000057593 human F8 Human genes 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229940047431 recombinate Drugs 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
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Abstract
The invention provides a manufacturing method of shallow trench isolation, which comprises the steps of: providing a semiconductor substrate with a masking structure covered on a surface, wherein an opening for exposing the semiconductor substrate is formed on the masking structure; etching a trench corresponding to the opening on the semiconductor substrate by taking the masking structure as a mask; forming lining oxidizing layers on sidewalls and the bottom of the trench; annealing under an argon atmosphere; and filling an insulating medium in the trench to form the shallow trench isolation. The manufacturing method provided by the invention can ensure that corners on the top of the trench are smoothened; and in addition, compared with the prior art, the manufacturing method has the advantages of simplifying process steps and lowering process cost.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of manufacturing method for shallow groove.
Background technology
Along with the progress of semiconductor fabrication, shallow trench isolation has replaced conventional semiconductor devices gradually from (STI, Shallow Trench Isolation) method and has made employing as other partition methods such as localized oxidation of silicon methods.Shallow trench isolation method has been compared many advantages with other partition methods, mainly comprises: 1, the STI method can obtain narrower semiconductor device isolation width, thereby improves device density; 2, the STI method can promote surface flatness, thereby can effectively control minimum feature when photoetching.
In existing technical process, find, shallow trench isolation has very strong correlation from the slick and sly degree of the shallow channel corner that is adopted with electric leakage, Yuan Hua corner, the generation of easy more prevention electric leakage, thereby how to make shallow channel corner slick and sly more, improve shallow trench isolation from electric property, thereby further reduce shallow trench isolation from electric leakage, be a major issue in the semiconductor technology.
Publication number is the Chinese patent of CN1404129A, disclose a kind of on-site steam of utilizing and generated technology (In-situ steam generated, ISSG) and technology such as anneal, reoxidize and make the shallow trench isolating side wall oxide layer, make the method for corner, shallow trench top slynessization.Fig. 1 to Fig. 6 is each process schematic diagram of having showed above-mentioned manufacturing method for shallow groove.
As shown in Figure 1, provide Semiconductor substrate 100, form dielectric layer 101, form mask layer 102 on the surface of described dielectric layer 101 on the surface of Semiconductor substrate 100.Described dielectric layer 101 can form by chemical vapour deposition (CVD) or thermal oxidation method for silica; Described mask layer 102 can be silicon nitride, forms by chemical vapour deposition (CVD).
As shown in Figure 2, adopt anisotropic etching, opening 110 of formation mask layer 102 in, described opening 110 exposes dielectric layer 101 surfaces, and defined follow-up making shallow trench isolation from the position.As shown in Figure 3, be mask with mask layer 102, etching dielectric layer 101 and Semiconductor substrate 100 form groove 120 on Semiconductor substrate 100 successively, and the degree of depth of described groove 120 depends on the type of follow-up shallow trench isolation from the components and parts of being isolated.Adopt on-site steam to generate technology ISSG then and form lining oxide layer 201 in the sidewall and the bottom of groove.Adopt on-site steam to generate the uniformity that technology ISSG can improve lining oxide layer 201, avoid lining oxide layer 201 to produce defective to a certain extent, make the corner slynessization at edge (position shown in the bracket among the figure).
As shown in Figure 4, continue to use on-site steam to generate technology ISSG on the surface of lining oxide layer 201, form sacrificial oxide layer 202, described sacrificial oxide layer 202 can weaken the stress in the lining oxide layer 201, avoid of the harmful effect of the internal stress of lining oxide layer 201, thereby make that shallow trench top edge is more slick and sly the corner.
As shown in Figure 5, in shallow trench, fill dielectric, form shallow trench isolation, and carry out chemico-mechanical polishing leveling shallow trench isolation from 203 surface from 203.Described dielectric can be materials such as silica or silicon nitride.
As shown in Figure 6, above-mentioned fleet plough groove isolation structure is carried out thermal oxidation technology once more, further improve the uniformity of above-mentioned each oxide layer, help groove corner slyness, remove mask layer 102 and dielectric layer 101 then.
In the existing shallow trench isolation production method, for slick and sly shallow channel corner, obtain enough slick and sly degree, formed two-layer oxide layer on trenched side-wall and bottom, successively carried out oxidation technology three times, processing step is comparatively complicated.The technology of wherein using on-site steam generation technology ISSG formation lining oxide layer 201 and sacrificial oxide layer 202 is because equipment and raw material limit, and cost is comparatively expensive, and efficiency-cost ratio is not high.Therefore be necessary to develop the shallow trench isolation that makes new advances from manufacture method, simplify processing procedure and also reduce the technology cost.
Summary of the invention
The problem that the present invention solves provide a kind of shallow trench isolation from manufacture method, make corner, shallow trench top slynessization that forms, simplification manufacturing process, and reduction technology cost.
For addressing the above problem, shallow trench isolation provided by the invention from manufacture method, comprising:
The Semiconductor substrate that provides surface coverage that mask structure is arranged is formed with the opening that exposes Semiconductor substrate on the described mask structure;
With the mask structure is mask, etches on Semiconductor substrate and the corresponding groove of described opening;
Lining oxide layer is formed on sidewall and bottom at described groove;
Under argon gas atmosphere, anneal;
In described groove, fill dielectric, form shallow trench isolation from.
Described argon flow amount is 0.5～10slm.Air pressure during described annealing is 1～760torr, and annealing temperature is 800～1150 degrees centigrade, and annealing time is 1～300 minute.
Optionally, described mask structure be silicon nitride mask layer, carborundum mask layer and polycrystalline silicon mask layer single layer structure or combination in any laminated construction.Described mask structure is the laminated construction that dielectric layer, mask layer superpose successively.
Optionally, the method for described etching semiconductor substrate is the anisotropic plasma etching.Described etching comprises the plasma etching that is formed by gases such as hydrogen bromide, helium, oxygen and sulphur hexafluorides for utilizing.
Optionally, described formation lining oxide layer adopts boiler tube thermal oxidation method or on-site steam to generate technology.
Optionally, after forming lining oxide layer, in the groove, before the filling dielectric, also comprise: remove lining oxide layer, form second lining oxide layer.Described removal lining oxide layer adopts the selectivity wet-etching technology.Described formation second lining oxide layer adopts boiler tube thermal oxidation method or on-site steam to generate technology.As alternative dispensing means, form shallow trench isolation from after, also comprise: remove mask structure, form sacrificial oxide layer at semiconductor substrate surface.Described formation sacrificial oxide layer adopts the boiler tube thermal oxidation method.
Compared with prior art, the present invention has the following advantages: mainly by the annealing under the argon gas atmosphere crystal lattice recombination is carried out in corner, groove top, improve the uniformity of described corner surfaces oxide layer, thereby realize the slynessization to corner, groove top.To the formation technology of lining oxide layer and have no special requirements, when conditions permit, can also omit the technology of making sacrificial oxide layer.Further simplify processing step, reduced the technology cost.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will be more clear.Parts same as the prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size in layer and zone.
Fig. 1 to Fig. 6 is the process schematic representation of existing shallow trench isolation production method;
Fig. 7 is the schematic flow sheet of shallow trench isolation production method of the present invention;
Fig. 8 to Figure 15 is the process schematic representation of the method for the invention first embodiment;
Figure 16 to Figure 18 is the process schematic representation of the method for the invention second embodiment.
Embodiment
Shallow trench isolation provided by the invention from manufacture method can be applied in 65nm node and the technology less than the 65nm node, in the size of shallow trench hour, also can form slick and sly shallow trench drift angle, improve shallow trench isolation from the electric property performance, alleviated shallow trench isolation from leaky.Simplify manufacturing process simultaneously, reduced the technology cost.
As shown in Figure 7, shallow trench isolation of the present invention from the manufacture method basic step comprise:
S101, the Semiconductor substrate that provides surface coverage that mask structure is arranged are formed with the opening that exposes Semiconductor substrate on the described mask structure; Wherein, the corresponding follow-up formation shallow trench isolation of the opening of mask structure from the position, mask structure can adopt conventional individual layer or multiple layer combination laminated construction.
S102, be mask, on Semiconductor substrate, etch and the corresponding groove of described opening with the mask structure; Wherein, when carrying out plasma etching, usually therefore opening sidewalls that also can the attenuate mask structure after forming groove, always exposes the corner at groove top.
S103, form lining oxide layer at the sidewall of described groove and bottom; Described lining oxide layer also should coat the corner at groove top.Described lining oxide layer can form by the boiler tube thermal oxidation method of routine to reduce production costs, and also can adopt the on-site steam growth technique to form as required, as booster action, obtains better slyness effect at groove top edge.
S104, under argon gas atmosphere, anneal; Usually annealing steps can be so that corner slynessization of groove, and this step is placed after the formation lining oxide layer, is in order to utilize the restriction of lining oxide layer, controls shape and size after the slynessization of corner, with practical requirement.This step is that the present invention is to the main slyness measure in corner, groove top.
S105, in described groove, fill dielectric, form shallow trench isolation from.Subsequent technique also should comprise the step of removing mask structure.
It is to be noted, in order to reduce the stress influence of lining oxide layer, avoid producing defective at the groove edge, can be after the S104 step, remove original lining oxide layer, and at the flute surfaces of annealed processing one deck lining oxide layer that regrows, the described lining oxide layer that regrows can form by conventional boiler tube thermal oxidation method or on-site steam growth technique.Select as another kind, can also after the S105 step,, can reach the effect that weakens the lining oxide layer stress influence equally removing the semiconductor substrate surface employing boiler tube thermal oxidation method formation sacrificial oxide layer that mask structure exposes.
Below in conjunction with specific embodiment the present invention is done further introduction.
First embodiment
Fig. 8 to Figure 15 is the process schematic representation of the method for the invention first embodiment.In conjunction with Figure of description the present embodiment manufacture method is described in detail.
As shown in Figure 8, at first provide Semiconductor substrate 300, be coated with mask structure 301 on the described Semiconductor substrate 300.Described mask structure 301 can be the individual layer in silicon oxide layer, silicon nitride layer or the polysilicon layer or the laminated construction of combination in any, can also be the laminated construction that dielectric layer, mask layer superpose successively.When wherein said dielectric layer is used for photo etched mask structure 301 formation openings, play the effect of etching stopping protection Semiconductor substrate 300.The thickness of mask structure 301 can be 100nm to 120nm.Semiconductor substrate 300 adopts polysilicon in the present embodiment, and mask structure 301 adopts the individual layer silicon nitride layer, and thickness is selected 110nm for use.Forming this Semiconductor substrate 300 and mask layer structure 301 can be common epitaxial growth of field of semiconductor manufacture or deposition process.
As shown in Figure 9, etch mask structure 301 forms opening 310 until exposing Semiconductor substrate 300 on described mask structure 301.Described opening 310 be corresponding follow-up formation shallow trench isolation from the position.Described etch mask structure 310 forms the lithographic method of opening 310, can be the common lithographic method of field of semiconductor manufacture, for example utilizes photoresist to carry out plasma etching.
As shown in figure 10, be etch mask with the mask structure 301 that has opening 310, on Semiconductor substrate 300, etch groove 320.The degree of depth of described groove 320 depends on the type of device of shallow trench isolation from required isolation, therefore selects according to actual needs.In the present embodiment, the degree of depth of described groove 320 can be between the 390nm to 410nm, concrete example such as 400nm.The lithographic method of described groove 320 can be the plasma etching of the mist of hydrogen bromide, helium, oxygen and carbon hexa fluoride as etching gas, and wherein the flow of hydrogen bromide is 27 to 33sccm, concrete example such as 30sccm; The flow of helium-oxygen gas mixture body is 34 to 40sccm, concrete example such as 37sccm; The flow of sulphur hexafluoride is 5-7sccm, concrete example such as 6sccm.The pressure of etching is 10 to 20mTorr, concrete example such as 15mTorr; The power that adopts during etching is between 1100 to 1300W, concrete example such as 1200W; Etching voltage is 136 to 164V, concrete example such as 150V; The time of etching is 51 to 64 seconds, and concrete example was as 58 seconds.
After etching groove 320 on the Semiconductor substrate 300, can also carry out a step that substrate trenches 320 is revised, be used to optimize the inner surface form of groove 320 sidewalls and bottom, strengthen the slick and sly effect of the corner, groove top of subsequent step formation.Described step is that the mist with hydrogen bromide and oxygen carries out plasma etching as etching gas to groove 320, and the flow of hydrogen bromide is 315 to 385sccm, and concrete example such as 350sccm, the flow of oxygen are 10 to 20sccm, concrete example such as 15sccm.The pressure of etching is 5 to 10mTorr, concrete example such as 7mTorr; The power that adopts during etching is between 900 to 1100W, concrete example such as 1000W; Etching voltage is 300V; The time of etching is 5 to 15 seconds, and concrete example was as 9 seconds.
As shown in figure 11, form lining oxide layer 302 in the sidewall and the bottom of groove 320, the material of described lining oxide layer is a silica, can form by employing on-site steam growth technique same as the prior art, obtains the slynessization effect at groove top edge.In the present embodiment, described slynessization effect can realize that therefore for the simplification technology that reduces production costs, described lining oxide layer 302 only adopts conventional boiler tube thermal oxidation method to form by subsequent anneal technology.The thickness range of described lining oxide layer 302 can be 50nm to 100nm, concrete example such as 50nm.
As shown in figure 12, anneal under argon gas atmosphere, can the recombinate lattice structure of groove top edge of described annealing steps is improved the uniformity of lining oxide layer 302, makes the corner slyness at groove 320 tops.The technological parameter of described annealing is: gas flow is 0.5～10slm, and air pressure is 1～760torr, and annealing temperature is 800～1150 degrees centigrade, and annealing time is 1～300 minute.Usually rapid thermal annealing need adopt higher temperature can accelerate manufacturing process, and the temperature requirements of thermal annealing is lower at a slow speed, and required time is longer, can more accurate control to the corner slyness degree at groove 320 tops.Concrete parameter is selected, and can select according to equipment, the production demand of reality.
Described argon annealed technology is implemented comparatively simple as the manufacture of semiconductor of routine.Above-mentioned argon annealed technology can also form the technology of lining oxide layer 302 with the aforementioned hot oxidation, carries out in same boiler tube, further reduces operation, reduces cost.Therefore pass through on-site steam growth technique ISSG compared to prior art, obtain the method for slick and sly groove corner, the present invention is based on existing processing line and both can realize that need not increased extra equipment, cost is lower, has more outstanding efficiency-cost ratio.
As shown in figure 13, as optional step, present embodiment is removed lining oxide layer 302, and forms second lining oxide layer 303 at the sidewall and the substrate surface of the groove 320 of annealed processing.Because annealed corner, groove 320 top has obtained enough slick and sly degree, therefore new second lining oxide layer 303 that forms is than original lining oxide layer 302, to have better uniformity in corner surfaces, the influence of its internal stress is less than lining oxide layer 302.Can adopt the selectivity wet etching to remove lining oxide layer 302, can adopt boiler tube thermal oxidation method or on-site steam growth technique to form second lining oxide layer 303.Usually in order to reduce cost, present embodiment adopts conventional boiler tube thermal oxidation method, forms second lining oxide layer 303, and the thickness of described second lining oxide layer 303 is 50nm to 100nm, concrete example such as 50nm.
As shown in figure 14, in described groove 320, fill dielectric, form shallow trench isolation from 400.Described dielectric can be a silica, can fill by chemical vapour deposition (CVD) CVD technology.After having filled dielectric, to shallow trench isolation from 400 and mask structure 301 carry out chemico-mechanical polishing, remove the dielectric overflow, the leveling shallow trench isolation is from 400 top surface.
As shown in figure 15, remove mask structure 301.Mask structure described in the present embodiment 301 is the individual layer silicon nitride layer, can adopt optionally wet etching removal, and described wet etching can adopt hot phosphoric acid.
Second embodiment
Adopt groove 320 sidewalls and lower surface to regenerate second lining oxide layer 303 among first embodiment in annealed processing, weaken the effect of described oxide layer internal stress, described stress may cause harmful effect at the edge at groove 320 tops.For further simplifying technology, present embodiment also provides a kind of optional method, after the step of removing mask structure 301, form sacrificial oxide layer at exposed semiconductor substrate surface, improve the uniformity of corner surfaces silica, with the harmful effect of the internal stress that weakens lining oxide layer 302 to described corner.Because the difference of the present embodiment and first embodiment is the formation step of sacrificial oxide layer.Therefore the technology and first embodiment before annealing steps shown in Figure 12 is identical, repeats no more.
As shown in figure 16, after annealing finishes to lining oxide layer 302, directly described groove 320 in, fill dielectric and through leveling surperficial concordant until with mask structure 301, the formation shallow trench isolation is from 400.Described dielectric can be a silica, can fill by chemical vapour deposition (CVD) CVD technology.After having recharged dielectric, to shallow trench isolation from 400 and mask structure 301 carry out chemico-mechanical polishing, remove the dielectric overflow, the leveling shallow trench isolation is from 400 top surface.
As shown in figure 17, remove mask structure 301, expose the Semiconductor substrate 300 of mask structure 301 bottoms.Mask structure described in the present embodiment 301 is the individual layer silicon nitride layer, can adopt optionally wet etching removal, and described wet etching can adopt hot phosphoric acid.
As shown in figure 18, form sacrificial oxide layer 304 on Semiconductor substrate 300 surfaces that expose.Can adopt conventional boiler tube thermal oxidation method, the thickness of described sacrificial oxide layer 304 is 30nm to 120nm, concrete example such as 80nm.Above-mentioned sacrificial oxide layer 304 is adjacent at the top of groove 320 edge with lining oxide layer 301, improves the uniformity of groove corner surfaces silica, can weaken the harmful effect that the internal stress of lining oxide layer 302 produces corner, described top equally.
In the existing shallow trench isolation production method, adopt on-site steam growth technique ISSG to form the mode of oxide layer in flute surfaces, though can improve the uniformity of flute surfaces oxide layer to a certain extent, improve the slick and sly degree of corner, groove top, efficiency-cost ratio is relatively poor.For example adopt and embodiment of the invention same size parameter, form the oxide layer of 80nm thickness equally in flute surfaces, the groove that existing manufacture method forms, the silicon oxide thickness of top sides angle surface is about 52.2nm to 59.1nm, accounts for 64.1% of central average thickness.And adopt manufacture method of the present invention, and corner, described groove top is more slick and sly, and its surperficial silicon oxide thickness is about 66nm to 68.1nm, accounts for 84.6% of central average thickness.Therefore manufacture method of the present invention has well in corner, groove top slynessization effect equally, even also is better than prior art, has also reached the purpose that significantly reduces production costs on the other hand.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (13)
- A shallow trench isolation from manufacture method, it is characterized in that, comprising:The Semiconductor substrate that provides surface coverage that mask structure is arranged is formed with the opening that exposes Semiconductor substrate on the described mask structure;With the mask structure is mask, etches on Semiconductor substrate and the corresponding groove of described opening;Lining oxide layer is formed on sidewall and bottom at described groove;Under argon gas atmosphere, anneal;In described groove, fill dielectric, form shallow trench isolation from.
- 2. shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that described argon flow amount is 0.5～10slm.
- 3. shallow trench isolation as claimed in claim 1 or 2 from manufacture method, it is characterized in that the air pressure in described when annealing is 1～760torr, annealing temperature is 800～1150 degrees centigrade, annealing time is 1～300 minute.
- 4. shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that described mask structure is the single layer structure or the combination in any laminated construction of silicon nitride mask layer, carborundum mask layer and polycrystalline silicon mask layer.
- 5. shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that described mask structure is the laminated construction that dielectric layer, mask layer superpose successively.
- 6. shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that the method for described etching semiconductor substrate is the anisotropic plasma etching.
- 7. shallow trench isolation as claimed in claim 6 from manufacture method, it is characterized in that described etching comprises the plasma etching that is formed by gases such as hydrogen bromide, helium, oxygen and sulphur hexafluorides for utilizing.
- 8. shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that described formation lining oxide layer adopts boiler tube thermal oxidation method or on-site steam to generate technology.
- 9. shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that, after forming lining oxide layer, in the groove, fill dielectric before, also comprise: remove lining oxide layer, form second lining oxide layer.
- 10. the manufacture method of money trench isolations as claimed in claim 9 is characterized in that, described removal lining oxide layer adopts the selectivity wet-etching technology.
- 11. shallow trench isolation as claimed in claim 9 from manufacture method, it is characterized in that described formation second lining oxide layer adopts boiler tube thermal oxidation method or on-site steam to generate technology.
- 12. shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that, form shallow trench isolation from after, also comprise: remove mask structure, form sacrificial oxide layer at semiconductor substrate surface.
- 13. shallow trench isolation as claimed in claim 12 from manufacture method, it is characterized in that described formation sacrificial oxide layer adopts the boiler tube thermal oxidation method.
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| CN104347470A (en) * | 2013-07-29 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of the semiconductor device |
| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
| CN105990127A (en) * | 2015-02-03 | 2016-10-05 | 苏州同冠微电子有限公司 | Etching method for etching semiconductor groove |
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| CN115483092A (en) * | 2021-06-15 | 2022-12-16 | 芯恩（青岛）集成电路有限公司 | Method for rounding top angle of groove in semiconductor structure and semiconductor structure |
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| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
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| CN115020321A (en) * | 2022-05-31 | 2022-09-06 | 上海积塔半导体有限公司 | Method for preparing active region |
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