CN102446480A - Voltage conversion circuit - Google Patents
Voltage conversion circuit Download PDFInfo
- Publication number
- CN102446480A CN102446480A CN2010105091210A CN201010509121A CN102446480A CN 102446480 A CN102446480 A CN 102446480A CN 2010105091210 A CN2010105091210 A CN 2010105091210A CN 201010509121 A CN201010509121 A CN 201010509121A CN 102446480 A CN102446480 A CN 102446480A
- Authority
- CN
- China
- Prior art keywords
- voltage
- switch module
- clock signal
- conversion circuit
- nmos pipe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 94
- 239000003990 capacitor Substances 0.000 claims abstract description 34
- 230000008901 benefit Effects 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000008859 change Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
Images
Landscapes
- Dc-Dc Converters (AREA)
Abstract
The invention provides a voltage conversion circuit, comprising: the charge pump module, the switch module, the level conversion module and the capacitor are arranged in the circuit board; the charge pump module is used for converting the input voltage into a preset voltage, and when the level conversion module controls the switch module to be closed, the preset voltage is output to the output end of the voltage conversion circuit by the switch module; when the level conversion module controls the switch module to be switched off, the capacitor provides output voltage for the voltage conversion circuit. The circuit only adopts a charge pump to convert the input voltage into a preset voltage and then output the preset voltage, and the output voltage can be larger than or smaller than the input voltage. The charge pump correspondingly utilizes a capacitor, so that the size of the voltage conversion circuit can be reduced, and the cost is reduced. The voltage conversion circuit provided by the invention has the advantage of small volume, can be further integrated on the array substrate of the display panel and synchronously completed in the manufacturing process of the array substrate, and can further reduce the cost of the driving chip.
Description
Technical field
The present invention relates to the circuit design technique field, particularly a kind of voltage conversion circuit.
Background technology
Panel display board is when work, and thin film transistor (TFT) array must have the action of scanning, makes video data deposit each display unit in the thin film transistor (TFT) array in regular turn in.In the drive voltage circuit of thin film transistor (TFT) array, must use a voltage level shifter, be used for converting the clock signal of low-voltage to high-tension clock signal.Like this, this high-tension clock signal just has enough abilities to drive late-class circuit, accomplishes the demonstration of panel display board.
At present, the voltage conversion circuit that produces high-tension clock signal comprises two charge pumps, two corresponding two electric capacity of charge pump.
Two charge pumps are alternately controlled the output of voltage conversion circuit, thereby realize the clock signal of voltage conversion circuit output HIGH voltage.But because the volume of electric capacity and charge pump itself is bigger, the area of such two electric capacity and two charge pump corresponding electrical circuits is also bigger.
Summary of the invention
The technical matters that the present invention will solve provides a kind of voltage conversion circuit, can reduce the area of circuit board.
The embodiment of the invention provides a kind of voltage conversion circuit, comprising: charge pump module, switch module, level switch module and a capacitor;
The input signal of charge pump module comprises first clock signal, second clock signal and input voltage; Said first clock signal and second clock signal are the clock signal of a pair of complementation; The output terminal of charge pump module is connected to the input end of switch module, and the switch module output terminal is as the output terminal of voltage conversion circuit, and the output terminal of voltage conversion circuit passes through capacitor grounding;
The control end of switch module connects the output terminal of level switch module; The conducting and the disconnection of said level switch module CS module; The input signal of said level switch module comprises said second clock signal, and the output voltage of voltage conversion circuit is as the power supply of level switch module;
In preceding 1/2 cycle of a work period; The charge pump module is transported to input voltage the output terminal of charge pump module under the control of first clock signal and second clock signal, level switch module breaks off switch module under the control of second clock signal;
In back 1/2 cycle of a work period; The charge pump module changes into predetermined voltage with input voltage under the control of first clock signal and second clock signal; With the switch module conducting, predetermined voltage provides output voltage and voltage that capacitor is charged on the capacitor is predetermined voltage through switch module to the output terminal of voltage conversion circuit to level switch module under the control of second clock signal.
Preferably, perhaps can obtain different predetermined voltages through the amplitude that changes the second clock signal through changing input voltage.
Preferably, said level switch module is used to provide an amplitude to equal the control end that voltage conversion circuit output voltage values, control signal that phase place is opposite with the second clock signal output to switch control module.
Preferably, the output voltage of said voltage conversion circuit equal input voltage and second clock signal amplitude with.
Preferably, all by same supply voltage power supply, the output voltage of voltage conversion circuit is 2 times of input voltage for said first clock signal, second clock signal and input voltage.
Preferably, said charge pump module comprises NMOS pipe, PMOS pipe, the 2nd PMOS pipe and first electric capacity;
The grid of the one NMOS pipe all is connected first clock signal with the grid of PMOS pipe;
The source ground of the one NMOS pipe;
The drain electrode of the one NMOS pipe all is connected the grid that the 2nd PMOS manages with the drain electrode of PMOS pipe;
The source electrode of the one PMOS pipe all is connected the second clock signal through first electric capacity with the drain electrode of the 2nd PMOS pipe; The drain electrode of the source electrode of the one PMOS pipe and the 2nd PMOS pipe links together as the output terminal of charge pump module;
The source electrode of the 2nd PMOS pipe connects input voltage.
Preferably, said switch module comprises the 3rd PMOS pipe;
The source electrode of the 3rd PMOS pipe connects the output terminal of charge pump module as first end of switch module;
The drain electrode of the 3rd PMOS pipe is as second end of switch module;
The grid of the 3rd PMOS pipe connects the output terminal of level switch module as the control end of switch module.
Preferably, said level switch module comprises: the 4th PMOS pipe, the 5th PMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, first phase inverter and second phase inverter;
The source electrode of the 4th PMOS pipe is managed second end that source electrode all is connected switch module with the 5th PMOS;
The grid of the 4th PMOS pipe connects the drain electrode of the 5th PMOS pipe, and the drain electrode of the 4th PMOS pipe connects the grid of the 5th PMOS pipe;
The grid of the 2nd NMOS pipe connects the second clock signal through first phase inverter, and the grid of the 3rd NMOS pipe connects the second clock signal;
The source grounding of the source electrode of the 2nd NMOS pipe and the 3rd NMOS pipe;
The drain electrode of the 2nd NMOS pipe connects the drain electrode of the 4th PMOS pipe, and the drain electrode of the 3rd NMOS pipe connects the drain electrode of the 5th PMOS pipe;
The drain electrode of the 4th PMOS pipe connects the input end of second phase inverter, and the output terminal of second phase inverter connects the control end of switch module as the output terminal of level switch module.
Preferably, the output voltage of said voltage conversion circuit equals input voltage and deducts the poor of second clock signal amplitude.
Preferably, said first clock signal, second clock signal and input voltage are supplied power by same supply voltage, and the output voltage of voltage conversion circuit is-1 times of input voltage.
Preferably, said charge pump module comprises the 6th PMOS pipe, the 5th NMOS pipe, the 4th NMOS pipe and the 3rd electric capacity;
The grid of the 6th PMOS pipe all is connected first clock signal with the grid of the 4th NMOS pipe;
The source electrode of the 6th PMOS pipe connects input voltage;
The drain electrode of the 6th PMOS pipe all is connected the grid that the 5th NMOS manages with the drain electrode of the 4th NMOS pipe;
The grounded drain of the 5th NMOS pipe;
The source electrode of the 4th NMOS pipe all is connected the second clock signal through the 3rd electric capacity with the source electrode of the 5th NMOS pipe;
The source electrode of the source electrode of the 4th NMOS pipe and the 5th NMOS pipe links together as the output terminal of charge pump module.
Preferably, said switch module comprises the 6th NMOS pipe;
The drain electrode of the 6th NMOS pipe connects the output terminal of charge pump module as first end of switch module;
The source electrode of the 6th NMOS pipe is as second end of switch module;
The grid of the 6th NMOS pipe connects the output terminal of level switch module as the control end of switch module.
Preferably, said level switch module comprises: the 7th PMOS pipe, the 8th PMOS pipe, the 7th NMOS pipe, the 8th NMOS pipe, the 3rd phase inverter and the 4th phase inverter;
The 7th PMOS pipe all is connected input voltage with the source electrode of the 8th PMOS pipe;
The second clock signal connects the grid that the 7th PMOS manages through the 3rd phase inverter, and the second clock signal connects the grid of the 8th PMOS pipe;
The drain electrode of the 7th PMOS pipe connects the drain electrode of the 7th NMOS pipe, and the 8th PMOS pipe connects the drain electrode of the 8th NMOS pipe;
The source electrode of the 7th NMOS pipe and the source electrode of the 8th NMOS pipe all are connected second end of switch module;
The grid of the 7th NMOS pipe connects the drain electrode of the 8th NMOS pipe, and the drain electrode of the 7th NMOS pipe connects the grid of the 8th NMOS pipe;
The drain electrode of the 7th NMOS pipe connects the input end of the 4th phase inverter, and the output terminal of the 4th phase inverter connects the control end of switch module as the output terminal of level switch module.
Preferably, said voltage conversion circuit is integrated on the array base palte of display panel.
Compared with prior art, the present invention has the following advantages:
Voltage conversion circuit provided by the invention only adopts a charge pump, converts input voltage into multiplication of voltage voltage, and the amplitude of this multiplication of voltage voltage is the prearranged multiple of input voltage.Such charge pump correspondence has been utilized an electric capacity, thereby can reduce the volume of voltage conversion circuit, reduces cost.Because voltage conversion circuit provided by the invention has the advantage of small size, can also further be integrated on the array base palte of display panel, and in the processing of array base palte, accomplish synchronously, can further reduce the chip for driving cost.
Description of drawings
Fig. 1 is voltage conversion circuit embodiment one structural drawing provided by the invention;
Fig. 2 is voltage conversion circuit one an embodiment circuit diagram provided by the invention;
Fig. 3 is another embodiment circuit diagram of voltage conversion circuit provided by the invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Referring to Fig. 1, this figure is voltage conversion circuit embodiment one structural drawing provided by the invention;
The voltage conversion circuit that present embodiment provides comprises: charge pump module 1, switch module 2, level switch module 3 and capacitor C2;
The input signal of charge pump module 1 comprises the first clock signal C K, second clock signal CKB and input voltage vin; Said first clock signal C K and second clock signal CKB are the clock signal of a pair of complementation, that is, when CK was high level, CKB was a low level; When CK was low level, CKB was a high level;
Charge pump module 1 is used under the control of the first clock signal C K and second clock signal CKB, exports after converting input voltage vin into predetermined voltage; Need to prove that the voltage after 1 conversion of charge pump module is pulse voltage, predetermined voltage is the amplitude voltage of this pulse voltage.This predetermined voltage can be greater than or less than input voltage vin, and its variation receives the control of the first clock signal C K, second clock signal CKB, and its variation range is relevant with the amplitude of input voltage vin and second clock signal CKB.Such as, when the predetermined voltage of the first clock signal C K and second clock signal CKB control output during greater than input voltage vin, the scope of the pulse voltage after the said conversion is (an input voltage vin; The amplitude sum of input voltage vin and second clock signal CKB); Such as input voltage vin is 5V, and the amplitude of second clock signal CKB is 5V, and then the pulsating sphere of pulse voltage is (5; 10), promptly 10 pairs of input voltage vin of charge pump module raise; When the predetermined voltage of the first clock signal C K and second clock signal CKB control output during less than input voltage vin; The scope of the pulse voltage after the said conversion is (input voltage vin, the amplitude of input voltage vin and second clock signal CKB poor), is 0V such as input voltage vin; The amplitude of second clock signal CKB is 5V; Then the pulsating sphere of pulse voltage is (0 ,-5), and promptly 1 pair of input voltage vin of charge pump module reduces.The amplitude of input voltage vin and second clock signal CKB also can be for other be worth in other embodiments, and corresponding just can obtain different scheduled voltages.
The output terminal of charge pump module 1 connects the input end of switch module 2, and the output terminal of switch module 2 is as the output terminal of voltage conversion circuit; The output terminal OUT of voltage conversion circuit is through capacitor C2 ground connection;
The output voltage of voltage conversion circuit output terminal OUT is as the power supply of level switch module 3; The output terminal of level switch module 3 connects the control end of switch module 2;
The input signal of level switch module 3 comprises said second clock signal CKB, and level switch module 3 is used to provide an amplitude to equal the control end that voltage conversion circuit output voltage values, control signal that phase place is opposite with the second clock signal are exported to switch module 2.
When switch module 2 breaks off, to the output end vo ut of voltage conversion circuit the predetermined voltage greater than input voltage is provided by capacitor C2.More than, voltage conversion circuit just can obtain a constant output voltage greater than input voltage.As the principle of work that need reduce input voltage vice versa, no longer specify here, those skilled in the art can release according to the principle of work that input voltage is raise.
Need to prove; The control signal CT of this level switch module 3 outputs mainly is in order to match with predetermined voltage, if for example input voltage vin is 5V, the amplitude of second clock signal CKB is 5V; The predetermined voltage of output is greater than input voltage vin; Its amplitude is 10V, and then the amplitude of control signal CT equals the voltage conversion circuit output voltage values, and main like this is in order to guarantee the closed and disconnected of CS module.
Voltage conversion circuit provided by the invention; Only utilize a charge pump module just can realize the purpose that input voltage is improved or reduces; Such charge pump module correspondence has been utilized a capacitor; Just can change the output voltage of voltage conversion circuit, thereby can reduce the volume of voltage conversion circuit, reduce cost.
Voltage conversion circuit provided by the invention can change output voltage, exports behind the input voltage that promptly can raise, and exports after also can reducing input voltage, raises in the face of voltage conversion circuit down or the change situation that reduces input voltage is introduced respectively.
At first introduce and export after voltage conversion circuit raises to input voltage, promptly the output voltage of voltage conversion circuit is greater than the situation of input voltage.Referring to Fig. 2, this figure is the circuit diagram of voltage conversion circuit one embodiment that provides of the embodiment of the invention.
In this enforcement, voltage conversion circuit comprises charge pump module 10, switch module 20, level switch module 30, the second capacitor C2 and supply voltage VDD.
The grid of the one NMOS pipe MN1 all is connected the first clock signal C K with the grid of PMOS pipe MP1;
The source ground of the one NMOS pipe MN1 is VSS;
The drain electrode of the one NMOS pipe MN1 all is connected the grid that the 2nd PMOS manages MP2 through node N1 with the drain electrode of PMOS pipe MP1;
The source electrode of the one PMOS pipe MP1 all is connected with first capacitor C 1 through node P1 with the drain electrode of the 2nd PMOS pipe MP2, and first capacitor C 1 is connected to second clock signal CKB;
Node P1 is as the output terminal of charge pump module 10;
The source electrode of the 2nd PMOS pipe MP2 connects input voltage VDD.
The source electrode of the 3rd PMOS pipe MP3 connects the output terminal of charge pump module 1O as the input end of switch module 20;
The drain electrode of the 3rd PMOS pipe MP3 exports the output end vo ut of voltage conversion circuit to as the output terminal of switch module 20;
The source electrode of the 4th PMOS pipe MP4 is managed the output terminal that the MP5 source electrode all is connected switch module 20 with the 5th PMOS, promptly connects the drain electrode of the 3rd PMOS pipe MP3;
The grid of the 4th PMOS pipe MP4 connects the drain electrode of the 5th PMOS pipe MP5, and the drain electrode of the 4th PMOS pipe MP4 connects the grid of the 5th PMOS pipe MP5;
The grid of the 2nd NMOS pipe MN2 connects second clock signal CKB through the first phase inverter D1, and the grid of the 3rd NMOS pipe MN3 connects second clock signal CKB;
The source grounding of the source electrode of the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3;
The drain electrode of the 2nd NMOS pipe MN2 connects the drain electrode of the 4th PMOS pipe MP4, and the drain electrode of the 3rd NMOS pipe MN3 connects the drain electrode of the 5th PMOS pipe MP5;
The drain electrode of the 4th PMOS pipe MP4 connects the input end of the second phase inverter D2, and the output terminal of the second phase inverter D2 promptly connects the grid of the 3rd PMOS pipe MP3 as the control end of the output terminal connection switch module 20 of level switch module 30.
The effect of level switch module 30 is to convert the CKB that imports into predetermined clock signal CT to export, and the CT amplitude is two times of CKB amplitude, and the phase place of these two clock signals is opposite.
Introduce the principle of work of present embodiment below in conjunction with Fig. 2.
It is 5V that the input voltage vin of voltage conversion circuit equals supply voltage VDD, and the variation range of first clock signal is 0～5V, and the variation range of second clock signal is 0～5V.
When preceding 1/2 cycle of one-period, the first clock signal C K is 5V, when second clock signal CKB is 0V, and NMOS pipe MN1 conducting, PMOS pipe MP1 breaks off, and therefore, the voltage of node N1 is 0V (because source ground of NMOS pipe MN1).The 2nd PMOS pipe MP2 conducting sends source voltage Vin to node P1.The voltage of first capacitor C, 1 lower end is 0V, and the upper end is 5V.At this moment, the voltage of the output terminal CT of level switch module is 5V, and therefore, the 3rd PMOS pipe MP3 breaks off.
In next 1/2 cycle, the first clock signal C K is 0V, and when second clock signal CKB was 5V, NMOS pipe MN1 broke off, PMOS pipe MP1 conducting, and therefore, the 5V voltage of node P1 sends node N1 to, and this moment, the 2nd PMOS pipe MP2 broke off.Because the source electrode of the 3rd PMOS pipe MP3 and the voltage of drain electrode equate that therefore the 3rd PMOS pipe MP3 also closes.At this moment; Satisfy the principle of charge conservation of electric capacity; Therefore become moment of 5V by 0V as second clock pulse CKB, the upper end of first capacitor C 1 can become 10V from 5V moment, and then the 3rd PMOS pipe MP3 can conducting; The voltage of the output end vo ut output 10V of voltage after the rising through voltage conversion circuit, and second capacitor C 2 charged make the voltage at second capacitor C, 2 two ends reach 10V.
In next again 1/2 cycle, the first clock signal C K becomes 5V, and second clock signal CKB becomes 0V, NMOS pipe MN1 conducting, and PMOS pipe MP1 breaks off, and the voltage of node N1 node is 0V (because source ground of NMOS pipe MN1).The 2nd PMOS pipe MP2 conducting.The voltage at first capacitor C, 1 two ends is got back to before the rising once more, and the voltage of C1 lower end is 0V, and the voltage of upper end is 5V.At this moment, level switch module 30 CS modules 20 are broken off, and the output voltage of this voltage conversion circuit OUT end is provided by second capacitor C 2.
In sum, the output voltage V out that the switch motion more than repeating just can make this voltage conversion circuit exports after promptly input voltage vin being raise greater than input voltage vin.
As preferred embodiment; In the voltage conversion circuit that present embodiment provides; It is 5V that input voltage vin equals supply voltage VDD; The variation range of the first clock signal C K is 0～5V, and the variation range of second clock signal CKB is 0～5V, because in circuit, generally by a power supply voltage is provided; Promptly provide voltage to supply with input voltage vin, the first clock signal C K, second clock signal CKB by supply voltage VDD; So the amplitude of the value of input voltage vin and the first clock signal C K, second clock signal CKB equates that the output voltage of voltage conversion circuit is the value of input voltage vin and the amplitude sum of second clock signal CKB, output voltage is the twice of input voltage.In other embodiments; Input voltage vin can be supplied power through different power supplys with the first clock signal C K, second clock signal CKB; And obtain different output voltage thus; Such as input voltage vin is 5V, and the first clock signal C K, second clock signal CKB change in the scope of 10V at 0V, and the output voltage that then obtains is 15V.
Following embodiment explains less than the situation of input voltage with the output voltage of voltage conversion circuit.Referring to Fig. 3, this figure is the another embodiment circuit diagram of voltage conversion circuit provided by the invention.
The voltage conversion circuit charge pump module 100 that present embodiment provides, switch module 200, level switch module 300 and second capacitor C 2.
The charge pump module 100 that present embodiment provides comprises the 6th PMOS pipe MP6, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5 and the 3rd capacitor C 3;
The grid of the 6th PMOS pipe MP6 all is connected the first clock signal C K with the grid of the 4th NMOS pipe MN4;
The source electrode of the 6th PMOS pipe MP6 connects supply voltage VDD;
The drain electrode of the drain electrode of the 6th PMOS pipe MP6 and the 4th NMOS pipe MN4 all is connected the grid of the 5th NMOS pipe MN5 through node N2;
The source electrode of the 5th NMOS pipe MN5 connects output voltage V in;
The source electrode of the 4th NMOS pipe MN4 all is connected second clock signal CKB through node P2 with the 3rd capacitor C 3 with the drain electrode of the 5th NMOS pipe MN5, and node P3 is as the output terminal of charge pump module 100;
The switch module 200 that present embodiment provides comprises the 6th NMOS pipe MN6;
The source electrode of the 6th NMOS pipe MN6 connects the output terminal of charge pump module 100, i.e. connected node P2 as the input end of switch module 200;
The drain electrode of the 6th NMOS pipe MN6 is as the output terminal of switch module 200;
The grid of the 6th NMOS pipe MN6 connects the output terminal of level switch module 300 as the control end of switch module 200.
The level switch module 300 that present embodiment provides comprises: the 7th PMOS pipe MP7, the 8th PMOS pipe MP8, the 7th NMOS pipe MN7, the 8th NMOS manage MN8, the 3rd phase inverter D3 and the 4th phase inverter D4;
The 7th PMOS pipe MP7 all is connected supply voltage VDD with the source electrode of the 8th PMOS pipe MP8;
The output terminal of second clock signal CKB connects the grid that the 7th PMOS manages MP7 through the 3rd phase inverter D3, and the input end of second clock signal CKB connects the grid of the 8th PMOS pipe MP8;
The drain electrode of the 7th PMOS pipe MP7 connects the drain electrode of the 7th NMOS pipe MN7, and the 8th PMOS pipe MP8 connects the drain electrode of the 8th NMOS pipe MN8;
The source electrode of the 7th NMOS pipe MN7 and the source electrode of the 8th NMOS pipe MN8 all are connected the output terminal of switch module 200, promptly connect the drain electrode of the 6th NMOS pipe MN6;
The grid of the 7th NMOS pipe MN7 connects the drain electrode of the MN8 of the 8th NMOS pipe, and the drain electrode of the 7th NMOS pipe MN7 connects the grid of the 8th NMOS pipe MN8;
The drain electrode of the 7th NMOS pipe MN7 connects the input end of the 4th phase inverter D4, and the output terminal of the 4th phase inverter D4 promptly connects the grid of the 6th NMOS pipe MN6 as the control end of the output terminal connection switch module 200 of level switch module 300.
Introduce the principle of work of present embodiment below in conjunction with Fig. 2.
It is 0V that the defeated eight voltage Vin of voltage conversion circuit equal supply voltage VSS, and the variation range of first clock signal is 0～5V, and the variation range of second clock signal is 0～5V, and supply voltage VDD is 5V.
When preceding 1/2 cycle of one-period, the first clock signal C K is 0V, when second clock signal CKB is 5V, and the 6th PMOS pipe MP6 conducting, the 4th NMOS pipe MN4 breaks off, and therefore, the voltage of node N2 is VDD.The 5th NMOS pipe MN5 conducting is that the 0V voltage of VSS sends node P2 to source voltage Vin.The voltage of the 3rd capacitor C 3 lower ends is 5V, and the upper end is 0V.At this moment, the voltage of the output terminal CT of level switch module 300 is 0V, and therefore, the 6th NMOS pipe MN6 breaks off.
In next 1/2 cycle, the first clock signal C K is 5V, and when second clock signal CKB was 0V, the 6th NMOS pipe MN6 broke off, the 4th PMOS pipe MN4 conducting, and therefore, the 0V voltage of node P2 sends node N2 to, and this moment, the 5th NMOS pipe MN5 broke off.Because the source electrode of the 6th NMOS pipe MN6 and the voltage of drain electrode equate that therefore the 6th NMOS pipe MN6 also closes.At this moment; Satisfy the principle of charge conservation of electric capacity; Therefore become moment of 0V by 5V as second clock pulse CKB, the upper end of the 3rd capacitor C 3 can become-5V from 0V moment, and then the 6th NMOS pipe MN6 can conducting; The voltage of the output end vo ut output-5V of voltage after the change through voltage conversion circuit, and second capacitor C 2 voltage that makes the second electric capacity two ends that charges reached-5V.
In next again 1/2 cycle, the first clock signal C K becomes 0V, and second clock signal CKB becomes 5V, the 6th PMOS pipe MP6 conducting, and the 4th NMOS pipe MN4 breaks off, and the voltage of node N2 is that the VDD value is 5V.The 5th NMOS pipe MN5 conducting.The voltage at the 3rd capacitor C 3 two ends is got back to before the change once more, and the voltage of C3 lower end is 5V, and the voltage of upper end is 0V.At this moment, level switch module 300 CS modules 200 are broken off, and the output voltage of this voltage conversion circuit OUT end is provided by second capacitor C 2.
In sum, the output voltage V out that the switch motion more than repeating just can make this voltage conversion circuit exports after promptly input voltage vin being raise greater than input voltage vin.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (14)
1. a voltage conversion circuit is characterized in that, comprising: charge pump module, switch module, level switch module and a capacitor;
The input signal of charge pump module comprises first clock signal, second clock signal and input voltage; Said first clock signal and second clock signal are the clock signal of a pair of complementation; The output terminal of charge pump module is connected to the input end of switch module, and the switch module output terminal is as the output terminal of voltage conversion circuit, and the output terminal of voltage conversion circuit passes through capacitor grounding;
The control end of switch module connects the output terminal of level switch module; The conducting and the disconnection of said level switch module CS module; The input signal of said level switch module comprises said second clock signal, and the output voltage of voltage conversion circuit is as the power supply of level switch module;
In preceding 1/2 cycle of a work period; The charge pump module is transported to input voltage the output terminal of charge pump module under the control of first clock signal and second clock signal, level switch module breaks off switch module under the control of second clock signal;
In back 1/2 cycle of a work period; The charge pump module changes into predetermined voltage with input voltage under the control of first clock signal and second clock signal; With the switch module conducting, predetermined voltage provides output voltage and voltage that capacitor is charged on the capacitor is predetermined voltage through switch module to the output terminal of voltage conversion circuit to level switch module under the control of second clock signal.
2. voltage conversion circuit according to claim 1 is characterized in that, perhaps can obtain different predetermined voltages through changing input voltage through the amplitude that changes the second clock signal.
3. voltage conversion circuit according to claim 1; It is characterized in that said level switch module is used to provide an amplitude to equal the control end that voltage conversion circuit output voltage values, control signal that phase place is opposite with the second clock signal output to switch control module.
4. voltage conversion circuit according to claim 1 is characterized in that, the output voltage of said voltage conversion circuit equal input voltage and second clock signal amplitude with.
5. voltage conversion circuit according to claim 4 is characterized in that, all by same supply voltage power supply, the output voltage of voltage conversion circuit is 2 times of input voltage for said first clock signal, second clock signal and input voltage.
6. voltage conversion circuit according to claim 4 is characterized in that, said charge pump module comprises NMOS pipe, PMOS pipe, the 2nd PMOS pipe and first electric capacity;
The grid of the one NMOS pipe all is connected first clock signal with the grid of PMOS pipe;
The source ground of the one NMOS pipe;
The drain electrode of the one NMOS pipe all is connected the grid that the 2nd PMOS manages with the drain electrode of PMOS pipe;
The source electrode of the one PMOS pipe all is connected the second clock signal through first electric capacity with the drain electrode of the 2nd PMOS pipe; The drain electrode of the source electrode of the one PMOS pipe and the 2nd PMOS pipe links together as the output terminal of charge pump module;
The source electrode of the 2nd PMOS pipe connects input voltage.
7. voltage conversion circuit according to claim 4 is characterized in that, said switch module comprises the 3rd PMOS pipe;
The source electrode of the 3rd PMOS pipe connects the output terminal of charge pump module as first end of switch module;
The drain electrode of the 3rd PMOS pipe is as second end of switch module;
The grid of the 3rd PMOS pipe connects the output terminal of level switch module as the control end of switch module.
8. voltage conversion circuit according to claim 4 is characterized in that, said level switch module comprises: the 4th PMOS pipe, the 5th PMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, first phase inverter and second phase inverter;
The source electrode of the 4th PMOS pipe is managed second end that source electrode all is connected switch module with the 5th PMOS;
The grid of the 4th PMOS pipe connects the drain electrode of the 5th PMOS pipe, and the drain electrode of the 4th PMOS pipe connects the grid of the 5th PMOS pipe;
The grid of the 2nd NMOS pipe connects the second clock signal through first phase inverter, and the grid of the 3rd NMOS pipe connects the second clock signal;
The source grounding of the source electrode of the 2nd NMOS pipe and the 3rd NMOS pipe;
The drain electrode of the 2nd NMOS pipe connects the drain electrode of the 4th PMOS pipe, and the drain electrode of the 3rd NMOS pipe connects the drain electrode of the 5th PMOS pipe;
The drain electrode of the 4th PMOS pipe connects the input end of second phase inverter, and the output terminal of second phase inverter connects the control end of switch module as the output terminal of level switch module.
9. voltage conversion circuit according to claim 1 is characterized in that, the output voltage of said voltage conversion circuit equals input voltage and deducts the poor of second clock signal amplitude.
10. voltage conversion circuit according to claim 9 is characterized in that, said first clock signal, second clock signal and input voltage are supplied power by same supply voltage, and the output voltage of voltage conversion circuit is-1 times of input voltage.
11. voltage conversion circuit according to claim 9 is characterized in that, said charge pump module comprises the 6th PMOS pipe, the 5th NMOS pipe, the 4th NMOS pipe and the 3rd electric capacity;
The grid of the 6th PMOS pipe all is connected first clock signal with the grid of the 4th NMOS pipe;
The source electrode of the 6th PMOS pipe connects input voltage;
The drain electrode of the 6th PMOS pipe all is connected the grid that the 5th NMOS manages with the drain electrode of the 4th NMOS pipe;
The grounded drain of the 5th NMOS pipe;
The source electrode of the 4th NMOS pipe all is connected the second clock signal through the 3rd electric capacity with the source electrode of the 5th NMOS pipe;
The source electrode of the source electrode of the 4th NMOS pipe and the 5th NMOS pipe links together as the output terminal of charge pump module.
12. voltage conversion circuit according to claim 9 is characterized in that, said switch module comprises the 6th NMOS pipe;
The drain electrode of the 6th NMOS pipe connects the output terminal of charge pump module as first end of switch module;
The source electrode of the 6th NMOS pipe is as second end of switch module;
The grid of the 6th NMOS pipe connects the output terminal of level switch module as the control end of switch module.
13. voltage conversion circuit according to claim 9 is characterized in that, institute reaches level switch module and comprises: the 7th PMOS pipe, the 8th PMOS pipe, the 7th NMOS pipe, the 8th NMOS pipe, the 3rd phase inverter and the 4th phase inverter;
The 7th PMOS pipe all is connected input voltage with the source electrode of the 8th PMOS pipe;
The second clock signal connects the grid that the 7th PMOS manages through the 3rd phase inverter, and the second clock signal connects the grid of the 8th PMOS pipe;
The drain electrode of the 7th PMOS pipe connects the drain electrode of the 7th NMOS pipe, and the 8th PMOS pipe connects the drain electrode of the 8th NMOS pipe;
The source electrode of the 7th NMOS pipe and the source electrode of the 8th NMOS pipe all are connected second end of switch module;
The grid of the 7th NMOS pipe connects the drain electrode of the 8th NMOS pipe, and the drain electrode of the 7th NMOS pipe connects the grid of the 8th NMOS pipe;
The drain electrode of the 7th NMOS pipe connects the input end of the 4th phase inverter, and the output terminal of the 4th phase inverter connects the control end of switch module as the output terminal of level switch module.
14. voltage conversion circuit according to claim 1 is characterized in that, said voltage conversion circuit is integrated on the array base palte of display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010509121.0A CN102446480B (en) | 2010-10-14 | 2010-10-14 | Voltage conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010509121.0A CN102446480B (en) | 2010-10-14 | 2010-10-14 | Voltage conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102446480A true CN102446480A (en) | 2012-05-09 |
| CN102446480B CN102446480B (en) | 2015-04-01 |
Family
ID=46008945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010509121.0A Expired - Fee Related CN102446480B (en) | 2010-10-14 | 2010-10-14 | Voltage conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102446480B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368383A (en) * | 2013-07-24 | 2013-10-23 | 苏州加古尔微电子科技有限公司 | Switch control circuit for DC (direct current)-DC boost converter |
| EP2860865A1 (en) * | 2013-10-11 | 2015-04-15 | Dialog Semiconductor GmbH | High efficiency charge pump circuit |
| CN107404307A (en) * | 2016-05-18 | 2017-11-28 | 英飞凌科技股份有限公司 | Measurement apparatus, level shifter circuit, charge pump stage and charge pump and its method |
| CN107516542A (en) * | 2017-07-03 | 2017-12-26 | 合肥格易集成电路有限公司 | A kind of I/O circuit and memory |
| CN108962119A (en) * | 2018-08-01 | 2018-12-07 | 京东方科技集团股份有限公司 | Level shifter and its driving method, display device |
| US10685802B2 (en) | 2016-05-18 | 2020-06-16 | Infineon Technologies Ag | Circuit architecture for a measuring arrangement, a level converter circuit, a charge pump stage and a charge pump, and method for operating same |
| CN114664269A (en) * | 2022-04-21 | 2022-06-24 | 京东方科技集团股份有限公司 | Working power supply conversion circuit, display drive board and liquid crystal display screen |
| CN118316434A (en) * | 2024-04-26 | 2024-07-09 | 江苏帝奥微电子股份有限公司 | High-voltage high-speed level conversion circuit and conversion method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6483728B1 (en) * | 2000-12-22 | 2002-11-19 | Matrix Semiconductor, Inc. | Charge pump circuit |
| JP2006276457A (en) * | 2005-03-29 | 2006-10-12 | Optrex Corp | Voltage generating circuit in liquid crystal drive circuit |
| TW200933562A (en) * | 2008-01-31 | 2009-08-01 | Tpo Displays Corp | Images display system |
-
2010
- 2010-10-14 CN CN201010509121.0A patent/CN102446480B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6483728B1 (en) * | 2000-12-22 | 2002-11-19 | Matrix Semiconductor, Inc. | Charge pump circuit |
| JP2006276457A (en) * | 2005-03-29 | 2006-10-12 | Optrex Corp | Voltage generating circuit in liquid crystal drive circuit |
| TW200933562A (en) * | 2008-01-31 | 2009-08-01 | Tpo Displays Corp | Images display system |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368383A (en) * | 2013-07-24 | 2013-10-23 | 苏州加古尔微电子科技有限公司 | Switch control circuit for DC (direct current)-DC boost converter |
| CN103368383B (en) * | 2013-07-24 | 2015-09-02 | 苏州加古尔微电子科技有限公司 | For the ON-OFF control circuit of DC-DC boost converter |
| EP2860865A1 (en) * | 2013-10-11 | 2015-04-15 | Dialog Semiconductor GmbH | High efficiency charge pump circuit |
| CN107404307A (en) * | 2016-05-18 | 2017-11-28 | 英飞凌科技股份有限公司 | Measurement apparatus, level shifter circuit, charge pump stage and charge pump and its method |
| US10685802B2 (en) | 2016-05-18 | 2020-06-16 | Infineon Technologies Ag | Circuit architecture for a measuring arrangement, a level converter circuit, a charge pump stage and a charge pump, and method for operating same |
| CN107404307B (en) * | 2016-05-18 | 2021-02-09 | 英飞凌科技股份有限公司 | Measuring device, level converter circuit, charge pump stage and charge pump and method thereof |
| CN107516542A (en) * | 2017-07-03 | 2017-12-26 | 合肥格易集成电路有限公司 | A kind of I/O circuit and memory |
| CN108962119A (en) * | 2018-08-01 | 2018-12-07 | 京东方科技集团股份有限公司 | Level shifter and its driving method, display device |
| CN114664269A (en) * | 2022-04-21 | 2022-06-24 | 京东方科技集团股份有限公司 | Working power supply conversion circuit, display drive board and liquid crystal display screen |
| CN118316434A (en) * | 2024-04-26 | 2024-07-09 | 江苏帝奥微电子股份有限公司 | High-voltage high-speed level conversion circuit and conversion method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102446480B (en) | 2015-04-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102446480A (en) | Voltage conversion circuit | |
| CN104537991B (en) | Forward-reverse scanning gate drive circuit | |
| CN102386898B (en) | Reset circuit | |
| CN103198782B (en) | Shift register, gate driver circuit and restorative procedure thereof and display device | |
| US20150318052A1 (en) | Shift register unit, gate drive circuit and display device | |
| CN104240766A (en) | Shifting register unit and gate driving device | |
| US9437152B2 (en) | Scan driving circuit | |
| CN104867438B (en) | Shift register cell and its driving method, shift register and display device | |
| CN104217763A (en) | A shifting register unit and a driving method thereof, a gate driving circuit, and a display device | |
| CN104299583A (en) | Shifting register, drive method of shifting register, drive circuit and display device | |
| CN104008738B (en) | Display Panel and Gate Driver | |
| CN204102544U (en) | Shift register cell, gate driver circuit and display device | |
| CN103646636A (en) | Shift register, grid drive circuit and display device | |
| CN202838909U (en) | Shifting register, grid driving circuit and display device | |
| CN101131807A (en) | Voltage buffer and source driver thereof | |
| CN106847215B (en) | Display device | |
| CN105427786A (en) | Gate driving circuit unit and gate driving circuit | |
| CN107221299A (en) | A kind of GOA circuits and liquid crystal display | |
| CN105446402A (en) | Controllable voltage source, shift register and unit thereof and display | |
| CN101505094A (en) | Electric power supply module for portable equipment | |
| CN105741740B (en) | GOA unit and its driving method, GOA circuit, display device | |
| CN109616060B (en) | Low-power consumption circuit | |
| CN104123922A (en) | Grid driving circuit and driving system and display device utilizing grid driving circuit | |
| CN106601178A (en) | Shift register unit and driving method thereof, grid driving circuit and display apparatus | |
| CN103680452B (en) | A kind of shift register, gate driver circuit, array base palte and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150401 |