CN204102544U - Shift register cell, gate driver circuit and display device - Google Patents

Abstract

The utility model provides a shift register unit, a grid drive circuit and a display device, which belong to the field of display technology. The shift register unit of the utility model includes: an input module, a pull-up module, a pull-down control module, a pull-down module, and a reset module And the discharge module; the input module, connected to the signal input terminal, the reset module and the pull-up control node; the pull-up module, connected to the pull-up control node, the first clock signal port and the signal output terminal; the pull-down control module, connected to the pull-down control node The control node, the pull-up control node and the second clock signal port; the pull-down module is connected to the pull-down control node and the low-level signal; the discharge module includes a discharge capacitor, and the first end of the discharge capacitor is connected to the pull-up module and the pull-up control node, The second end is connected to the output signal reset input end; the reset module is connected to the reset signal input end and the pull-up control node.

Description

Shift register unit, gate drive circuit and display device

technical field

The utility model belongs to the field of display technology, and in particular relates to a shift register unit, a grid drive circuit and a display device.

Background technique

TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor-Liquid Crystal Display) The basic principle of realizing a frame display is to input a square wave of a certain width to each row of pixels sequentially from top to bottom through the gate drive. strobe, and then through the source (source) to drive the signal required for each row of pixels to be output from top to bottom in turn. At present, the display device with such a structure is usually made of gate drive circuit and source drive circuit on the glass panel by COF (Chip On Film, chip-on-film) or COG (Chip On Glass, chip directly fixed on the glass) process. However, when the resolution is high, the output of the gate drive circuit and the source drive circuit will increase, and the length of the drive circuit will also increase, which will not be conducive to the bonding process of the module drive circuit. .

In order to overcome the above problems, the manufacturing of existing display devices adopts the design of GOA (GateDrive On Array) circuit. Compared with the existing COF or COG process, it not only saves the cost, but also achieves a symmetrical and beautiful design on both sides of the panel. The Bonding area of the gate drive circuit and the peripheral wiring space can also be omitted, thereby realizing the design of a narrow frame of the display device and improving the production capacity and yield rate of the display device. But the design of existing GOA circuit also has certain problems, as shown in Fig. The signal output terminal OUTPUT can be discharged through the fourth transistor M4, so the fourth transistor M4 has a large size and takes up a large space, and the control electrode voltage of the fourth transistor M4 is used as a shift register of a certain stage below the shift register unit. The output of the unit, so the gate voltage value of the fourth transistor M4 is the high level of the output voltage, but because the high level is not high enough, the size of the fourth transistor M4 needs to be relatively large to ensure that the output delay can work normally Within the range, resulting in a larger footprint of the GOA circuit.

Utility model content

The technical problem to be solved by the utility model includes, aiming at the above-mentioned problems existing in the existing shift register unit, providing a shift register, a gate drive circuit and a display device with a simple structure.

The technical solution adopted to solve the technical problem of the utility model is that a shift register includes: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module and a discharge module;

The input module is connected to the signal input terminal, the reset module and the pull-up control node, and is used to control the potential of the pull-up control node according to the signal input from the signal input terminal. The pull-up control node is the connection between the input module and the pull-up control node. the connection point of the pull module;

The pull-up module is connected to the pull-up control node, the first clock signal port, and the signal output terminal, and is used to control the clock signal input from the pull-up control node according to the potential of the pull-up control node and the first clock signal port. The signal output by the signal output terminal is pulled up to a high level;

The pull-down control module is connected to the pull-down control node, the pull-up control node and the second clock signal port, and is used to control the opening of the pull-down module according to the level of the pull-up control node, and the pull-down control node is the pull-down control node. The connection point between the module and the drop-down module;

The pull-down module is connected to a pull-down control node and a low-level signal, and is used to pull down the signal output by the signal output terminal to a low level through the low-level signal when the pull-down module is turned on;

The discharge module includes a discharge capacitor, the first end of the discharge capacitor is connected to the pull-up module and the pull-up control node, and the second end is connected to the output signal reset input end, which is used to reset the signal input by the input end according to the output signal controlling the discharge capacitor to maintain the potential of the pull-up control node, and the signal output terminal is discharged through the pull-up module and the discharge capacitor;

The reset module is connected to the reset signal input terminal and the pull-up control node, and is used to pull down the level of the pull-up control node through the signal input by the pull-up reset signal input terminal.

Because the discharge module of the register unit of the utility model adopts a discharge capacitor, the number of its transistors is less than that of the prior art, so its structure is simple, the power consumption is small, and the problem of delay is alleviated.

Preferably, the input module includes a first transistor;

The first pole of the first transistor is connected to its control pole and the signal input terminal, and the second pole is connected to the pull-up control node and the reset module.

Further preferably, the pull-up module includes a second transistor and a storage capacitor;

The first pole of the second transistor is connected to the first clock signal port, the second pole is connected to the second terminal of the storage capacitor and the signal output terminal, and the control pole is connected to the pull-up control node;

The first end of the storage capacitor is connected to the pull-up control node and the first end of the discharge capacitor.

Still further preferably, the pull-down control module includes a third transistor and a fourth transistor;

The first pole of the third transistor is connected to its control pole and the second pole of the fourth transistor, the second pole is connected to the control pole of the fourth transistor and the pull-down control module, and the control pole is connected to the second clock signal port;

The first pole of the fourth transistor is connected to the pull-down control node.

Still further preferably, the pull-down module includes a fifth transistor and a sixth transistor;

The first pole of the fifth transistor is connected to the second pole of the third transistor and the control pole of the fourth transistor, the second pole is connected to a low level signal, and the control pole is connected to the control pole of the sixth transistor;

The first pole of the sixth transistor is connected to the pull-down control node, the second pole is connected to the low level signal, and the control pole is connected to the pull-up control node.

Still further preferably, the discharge module further includes a seventh transistor;

The seventh transistor is connected to the second pole of the third transistor, the second terminal of the storage capacitor and the signal output terminal, the second pole is connected to a low level signal, and the control pole is connected to the second terminal of the storage capacitor.

Still further preferably, the reset module includes an eighth transistor;

The first pole of the eighth transistor is connected to the pull-up control node, the second pole is connected to the low level signal, and the control pole is connected to the reset signal input terminal.

Preferably, the register unit also includes a noise reduction module;

The noise reduction module is connected to the reset module, the low voltage signal, the pull-up control node and the pull-down control node, and is used to pull down the potential of the pull-up control node through the low-voltage signal according to the potential of the pull-down control node, so as to remove the shift register unit noise.

Further preferably, the noise reduction module includes a ninth transistor and a tenth transistor;

The first pole of the ninth transistor is connected to a pull-up control node, the second pole is connected to a low-level signal, and the control pole is connected to a pull-down control node;

The first pole of the tenth transistor is connected to the signal output terminal, the second pole is connected to the low level signal, and the control pole is connected to the pull-down control node.

The technical solution adopted to solve the technical problem of the utility model is a gate drive circuit, which includes at least four cascaded shift register units described in any one of the above,

Except for the first-stage and second-stage shift register units, the signal output terminals of each other shift register units are connected to the signal input terminals of the lower two-stage shift registers;

Except for the shift register units of the first stage and the second stage, the signal output terminals of each other shift register units are connected to the output signal reset input terminals of the upper two stages of shift register units;

Except for the shift register units of the first stage, the second stage and the third stage, the signal output terminals of each other shift register units are connected to the reset signal input terminals of the upper three stages of shift register units; wherein,

The signal input terminals of the shift registers of the first stage and the second stage are connected to the frame gate signal.

The technical solution adopted to solve the technical problem of the utility model is a display device, which includes the above-mentioned gate driving circuit.

Description of drawings

Fig. 1 is the schematic diagram of existing shift register;

Fig. 2 is a kind of schematic diagram of the shift register of embodiment 1 of the present utility model;

Fig. 3 is another schematic diagram of the shift register of Embodiment 1 of the present utility model;

Fig. 4 is the circuit diagram of the shift register of embodiment 1 of the present utility model;

Fig. 5 is the timing diagram of the shift register work of embodiment 1 of the present utility model;

FIG. 6 is a schematic diagram of the gate driving circuit of Embodiment 1 of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the technical solution of the utility model, the utility model will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

The transistor used in the embodiment of the utility model can be a thin film transistor or a field effect transistor or the same device with other characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between the source and the drain. of. In the embodiment of the present invention, in order to distinguish the source and drain of the transistor, one of them is called the first pole, the other is called the second pole, and the gate is called the control pole. In addition, according to the characteristics of transistors, transistors can be divided into N-type and P-type. In the following embodiments, N-type transistors are used for illustration. The drain of an N-type transistor. It is conceivable that the realization by using P-type transistors can be easily thought of by those skilled in the art without any creative efforts, and therefore also falls within the protection scope of the embodiments of the present invention.

Example 1:

As shown in Figure 2, the present embodiment provides a shift register unit, which includes: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module, and a discharge module; the input module is connected to the signal input terminal INPUT , a reset module and a pull-up control node PU, used to control the potential of the pull-up control node PU according to the signal input by the signal input terminal INPUT, and the pull-up control node PU is the connection point between the input module and the pull-up module The pull-up module is connected to the pull-up control node PU, the first clock signal port CLK and the signal output terminal OUTPUT, and is used to input the pull-up control node PU and the first clock signal port CLK according to the potential of the pull-up control node PU. The control of the clock signal pulls up the signal output by the signal output terminal OUTPUT to a high level; the pull-down control module is connected to the pull-down control node PD, the pull-up control node PU and the second clock signal port CLKR, for according to The level of the pull-up control node PU controls the opening of the pull-down module, and the pull-down control node PD is the connection point between the pull-down control module and the pull-down module; the pull-down module is connected to the pull-down control node PD and a low-level signal, using When the pull-down module is turned on, the signal output from the signal output terminal OUTPUT is pulled down to a low level through the low-level signal; the discharge module at least includes a discharge capacitor, and the first end of the discharge capacitor is connected to The pull-up module and the pull-up control node PU, the second terminal is connected to the output signal reset input terminal RES-OUT, and is used to control the discharge capacitor according to the signal input by the output signal reset input terminal RES-OUT to maintain the potential of the pull-up control node PU , the signal output terminal OUTPUT is discharged through the pull-up module and the discharge capacitor; the reset module is connected to the reset signal input terminal RES-PU and the pull-up control node PU, and is used to input the reset signal input terminal RES-PU through the pull-up The signal of pulls up the level of the control node PU and pulls it down.

In this embodiment, the discharge capacitor is used as the discharge module. Compared with the discharge module composed of transistors in the prior art, the discharge capacitor occupies a smaller area, so that it can discharge the shift register unit well while reducing the The footprint of the shift register unit.

As shown in FIG. 4, preferably, in the shift register unit of this embodiment, the input module includes a first transistor M1, and the first pole of the first transistor M1 is connected to its control pole and the signal input terminal INPUT. The two poles are connected to the pull-up control node PU and the reset module.

In this embodiment, the pull-up control node PU refers to a node that controls the turn-on or turn-off of the pull-up module. The specific time of the function of the input module depends on whether the signal input by the signal input terminal INPUT is high level or low level to determine the state of the shift register unit.

Preferably, the pull-up module includes a second transistor M2 and a storage capacitor C1, the first pole of the second transistor M2 is connected to the first clock signal port CLK, and the second pole is connected to the second end of the storage capacitor C1 and the signal output terminal OUTPUT , the control electrode is connected to the pull-up control node PU; the first end of the storage capacitor C1 is connected to the pull-up control node PU and the first end of the discharge capacitor C2. The pull-down control module includes a third transistor M3 and a fourth transistor M4, the first pole of the third transistor M3 is connected to its control pole and the second pole of the fourth transistor M4, and the second pole is connected to the control pole of the fourth transistor M4. pole and a pull-down control module, the control pole is connected to the second clock signal port CLKR; the first pole of the fourth transistor M4 is connected to the pull-down control node PD. The pull-down module includes a fifth transistor M5 and a sixth transistor M6; the first pole of the fifth transistor M5 is connected to the second pole of the third transistor M3 and the control pole of the fourth transistor M4, and the second pole is connected to a low level signal, the control electrode is connected to the control electrode of the sixth transistor M6; the first electrode of the sixth transistor M6 is connected to the pull-down control node PD, the second electrode is connected to the low level signal, and the control electrode is connected to the pull-up control node PU. The discharge module further includes a seventh transistor M7, the seventh transistor M7 is connected to the second pole of the third transistor M3, the second end of the storage capacitor C1 and the signal output terminal OUTPUT, and the second pole is connected to a low level signal, The control electrode is connected to the second end of the storage capacitor C1. The reset module includes an eighth transistor M8; the first pole of the eighth transistor M8 is connected to the pull-up control node PU, the second pole is connected to a low level signal, and the control pole is connected to the reset signal input terminal RES-PU.

As shown in Figures 3 and 4, the register unit also includes a noise reduction module; the noise reduction module is connected to the reset module, the low voltage signal, the pull-up control node PU and the pull-down control node PD, and is used to control The potential of the PD pulls down the potential of the pull-up control node PU through a low voltage signal, so as to remove noise in the output signal of the shift register unit. Preferably, the noise reduction module includes a ninth transistor M9 and a tenth transistor M10; the first pole of the ninth transistor M9 is connected to the pull-up control node PU, the second pole is connected to a low-level signal, and the control pole is connected to the pull-down control node PU. Node PD; the first pole of the tenth transistor M10 is connected to the signal output terminal OUTPUT, the second pole is connected to a low level signal, and the control pole is connected to the pull-down control node PD.

In this embodiment, due to the existence of the discharge capacitor C2 and the capacitive coupling effect of the discharge capacitor C2, the pull-up control node PU can maintain a constant potential, so the signal output terminal OUTPUT can be well discharged, thereby reducing the size of the second transistor M2 The size of the seventh transistor and the reduction of the size of the seventh transistor can even eliminate the seventh transistor, thereby saving space and reducing power consumption of the shift register.

As shown in Figure 6, the corresponding present embodiment provides a gate drive circuit, including at least four cascaded shift register units mentioned above, except for the shift register units of the first stage and the second stage, each The signal output terminal OUTPUT of a shift register unit is connected to the signal input terminal INPUT of the next two stages of shift registers; except the first and second stage shift register units, the signal output terminal OUTPUT of each other shift register unit It is connected to the output signal reset input terminal RES-OUT of the upper two-stage shift register unit; except for the first-stage, second-stage and third-stage shift register units, the signal output terminal OUTPUT of each other shift register unit is connected to The reset signal input terminals RES-PU of the upper three-stage shift register units are connected; wherein, the signal input terminals INPUT of the first-stage and second-stage shift registers are connected to the frame strobe signal.

4 and 5, in order to understand the gate drive circuit of this embodiment more clearly, the drive method of the gate drive circuit is also provided:

S1. The signal (frame strobe signal STV) input by the signal input terminal INPUT is a high-level signal. At this time, the first transistor M1 is gated, and the pull-up control node PU is charged.

S2. The first clock signal port CLK inputs a high-level signal. Since the pull-up control node PU is charged at S1, it is at a high level. At this time, the second transistor M2 is gated, and the signal output terminal OUTPUT outputs a high level. Signal.

S3. The first clock signal port CLK changes from an input high-level signal to a low-level signal, and at the same time, the signal input by the output signal reset input terminal RES-OUT is the signal output terminal OUTPUT output of the lower two-stage shift register unit Since the signal input by the first clock signal port CLK of the lower two-stage shift register unit is a high-level signal (CLK3), the signal output by the signal output terminal OUTPUT of the lower two-stage shift register unit is It is high level, that is to say, the signal input by the output signal reset input terminal RES-OUT is high level. Due to the existence of the discharge capacitor C2, when the storage capacitor C1 and the discharge capacitor C2 are similar in size, the pull-down control node PD The potential of the signal is basically unchanged, so the signal output terminal OUTPUT can be well discharged through the second transistor M2.

S4. Since the reset signal input terminal RES-PU is connected to the signal output terminal OUTPUT of the lower three-stage shift register unit, since the signal output terminal OUTPUT of the lower three-stage shift register unit outputs a high-level signal at this time, Therefore, the signal input by the reset signal input terminal RES-PU is at a high level, and the eighth transistor M8 is strobed. Since the second pole of the eighth transistor M8 is connected to a low voltage signal, the potential of the pull-up control node PU is pulled down, completing Charging of the gate line connected to the shift register unit and reset of the pull-up control node PU.

During the rest of the working process, in order to further avoid noise in the signal output by the signal output terminal OUTPUT, when the pull-down control node PD is periodically pulled up to a high level by the second clock signal CLKR, the ninth transistor M9 and the tenth transistor M9 The transistor M10 is gated, so the pull-up control node PU and the signal output terminal OUTPUT are pulled low, noise is eliminated, and wrong output is prevented.

As mentioned above, in this embodiment, due to the existence of the discharge capacitor C2, the voltage at the pull-up control node PU remains unchanged in the S3 stage, and the voltage value at this point will be higher than the high level of the output voltage of the signal output terminal OUTPUT Therefore, the control electrode of the second transistor will maintain a very high potential, and the signal output terminal OUTPUT can be well discharged to CLK through the second transistor M2 (because CLK is low potential), so the second transistor M2 The size can be reduced, and the seventh transistor M7 can also be greatly reduced, and even the seventh transistor M7 can be eliminated, so that the power consumption and occupied area of the shift register unit can be reduced.

Correspondingly, this embodiment also provides a display device, which includes the above-mentioned gate driving circuit. The display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

Because the display device of this embodiment can realize a narrow frame design.

Of course, the display device of this embodiment may also include other conventional structures, such as a display driving unit and the like.

It can be understood that, the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present utility model, and these variations and improvements are also regarded as the protection scope of the present utility model.

Claims (11)

1. A shift register unit, characterized in that, comprising: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module and a discharge module; The input module is connected to the signal input terminal, the reset module and the pull-up control node, and is used to control the potential of the pull-up control node according to the signal input from the signal input terminal. The pull-up control node is the connection between the input module and the pull-up control node. the connection point of the pull module; The pull-up module is connected to the pull-up control node, the first clock signal port, and the signal output terminal, and is used to control the clock signal input from the pull-up control node according to the potential of the pull-up control node and the first clock signal port. The signal output by the signal output terminal is pulled up to a high level; The pull-down control module is connected to the pull-down control node, the pull-up control node and the second clock signal port, and is used to control the opening of the pull-down module according to the level of the pull-up control node, and the pull-down control node is the pull-down control node. The connection point between the module and the drop-down module; The pull-down module is connected to a pull-down control node and a low-level signal, and is used to pull down the signal output by the signal output terminal to a low level through the low-level signal when the pull-down module is turned on; The discharge module includes a discharge capacitor, the first end of the discharge capacitor is connected to the pull-up module and the pull-up control node, and the second end is connected to the output signal reset input end, which is used to reset the signal input by the input end according to the output signal controlling the discharge capacitor to maintain the potential of the pull-up control node, and the signal output terminal is discharged through the pull-up module and the discharge capacitor; The reset module is connected to the reset signal input terminal and the pull-up control node, and is used to pull down the level of the pull-up control node through the signal input by the pull-up reset signal input terminal. 2. The shift register unit according to claim 1, wherein the input module comprises a first transistor; The first pole of the first transistor is connected to its control pole and the signal input terminal, and the second pole is connected to the pull-up control node and the reset module. 3. The shift register unit according to claim 2, wherein the pull-up module includes a second transistor and a storage capacitor; The first pole of the second transistor is connected to the first clock signal port, the second pole is connected to the second terminal of the storage capacitor and the signal output terminal, and the control pole is connected to the pull-up control node; The first end of the storage capacitor is connected to the pull-up control node and the first end of the discharge capacitor. 4. The shift register unit according to claim 3, wherein the pull-down control module includes a third transistor and a fourth transistor; The first pole of the third transistor is connected to its control pole and the second pole of the fourth transistor, the second pole is connected to the control pole of the fourth transistor and the pull-down control module, and the control pole is connected to the second clock signal port; The first pole of the fourth transistor is connected to the pull-down control node. 5. The shift register unit according to claim 4, wherein the pull-down module includes a fifth transistor and a sixth transistor; The first pole of the fifth transistor is connected to the second pole of the third transistor and the control pole of the fourth transistor, the second pole is connected to a low level signal, and the control pole is connected to the control pole of the sixth transistor; The first pole of the sixth transistor is connected to the pull-down control node, the second pole is connected to the low level signal, and the control pole is connected to the pull-up control node. 6. The shift register unit according to claim 5, wherein the discharging module further comprises a seventh transistor; The seventh transistor is connected to the second pole of the third transistor, the second terminal of the storage capacitor and the signal output terminal, the second pole is connected to a low level signal, and the control pole is connected to the second terminal of the storage capacitor. 7. The shift register unit according to claim 1, wherein the reset module comprises an eighth transistor; The first pole of the eighth transistor is connected to the pull-up control node, the second pole is connected to the low level signal, and the control pole is connected to the reset signal input terminal. 8. The shift register unit according to any one of claims 1 to 6, wherein the register unit also includes a noise reduction module; The noise reduction module is connected to the reset module, the low voltage signal, the pull-up control node and the pull-down control node, and is used to pull down the potential of the pull-up control node through the low voltage signal according to the potential of the pull-down control node, so as to remove the shift register unit noise. 9. The shift register unit according to claim 8, wherein the noise reduction module comprises a ninth transistor and a tenth transistor; The first pole of the ninth transistor is connected to a pull-up control node, the second pole is connected to a low-level signal, and the control pole is connected to a pull-down control node; The first pole of the tenth transistor is connected to the signal output terminal, the second pole is connected to the low level signal, and the control pole is connected to the pull-down control node. 10. A gate drive circuit, characterized in that the gate drive circuit comprises at least four cascaded shift register units according to any one of claims 1 to 9, Except for the first-stage and second-stage shift register units, the signal output terminals of each other shift register units are connected to the signal input terminals of the lower two-stage shift registers; Except for the shift register units of the first stage and the second stage, the signal output terminals of each other shift register units are connected to the output signal reset input terminals of the upper two stages of shift register units; Except the shift register unit of the first stage, the second stage and the third stage, the signal output end of each other shift register unit is connected to the reset signal input end of the upper three-stage shift register unit; wherein, The signal input terminals of the shift registers of the first stage and the second stage are connected to the frame gate signal. 11. A display device, characterized in that the display device comprises the gate driving circuit according to claim 10.