CN102412811A - Adjustable non-overlapping clock signal generating method and generator - Google Patents

Abstract

The invention discloses an adjustable non-overlapping clock generation method and a generator. The square wave signals generated by an oscillating circuit are respectively input into at least two duty ratio adjustment circuits, and each duty ratio adjustment circuit is controlled at different duty ratios. Under the action of the signal, the duty ratio adjustment of the square wave signal is realized, thereby obtaining at least two output signals with different duty ratios, and these output signals with different duty ratios are non-overlapping clock signals. The invention has the characteristics of adjustable duty cycle and wide frequency output range.

Description

An adjustable non-overlapping clock generation method and generator

technical field

The invention relates to a non-overlapping clock generator, in particular to an adjustable non-overlapping clock generation method and generator.

Background technique

Switched capacitor (SC) technology is a hot spot in CMOS VLSI. Switched capacitor circuits are not only widely used in analog signal processing (such as filters, switched capacitor DC-DC converters, and voltage comparators, etc.), but also penetrate into mixed-signal modules (such as analog-to-digital converters, sigma-delta modulators, and sampling analog structure). The non-overlapping clock generator is used to control the switch of charging and discharging the capacitor, which is one of the core modules of the switched capacitor circuit. Traditional non-overlapping clock generator designs generally use NOR gates and inverter chains to form delay cells. Although researchers in the past have proposed different design methods for non-overlapping clock generators, most of the clock circuit modules are independent of the input signal generator, so they can only be regarded as shaping circuits. In these circuits, parameters defining the properties of the non-overlapping clock pair (clk1, clk2), such as duty cycle, non-overlapping time interval Δτ[clk1, clk2], and rise/fall times depend on the configuration of the delay cells. Once the circuit is integrated, these parameters cannot be changed. Furthermore, within the concept of this conventional design, the basic circuit is limited to medium to high frequency applications due to the limited number of delay elements. Some researchers have proposed a circuit design suitable for low-frequency applications, but the number of transistors required reaches hundreds. Some researchers realized the importance of the integration of oscillator and clock, and proposed to use the digitally controlled oscillator (DCO) structure to realize the whole process from the generation of oscillation signal to the generation of non-overlapping clock. However, in order to control the properties of the non-overlapping clock pair, DCO, level shifter and some other digital circuits are used, which makes the circuit structure very complicated.

Contents of the invention

The technical problem to be solved by the present invention is to provide an adjustable non-overlapping clock generation method and generator, which have the characteristics of adjustable duty cycle and wide frequency output range.

In order to solve the above problems, the present invention is achieved through the following technical solutions:

The present invention provides an adjustable non-overlapping clock generation method. The square wave signals generated by the oscillating circuit are respectively input into at least two duty ratio adjustment circuits, and each duty ratio adjustment circuit is under the action of different duty ratio control signals. The duty ratio adjustment of the square wave signal is realized, thereby obtaining at least two output signals with different duty ratios, and these output signals with different duty ratios are non-overlapping clock signals.

Each of the above-mentioned duty cycle adjustment circuits is composed of two input inverters and control inverters connected in parallel; the square wave signal input from the input inverter input is at the duty cycle Under the adjustment of the ratio control signal, change the inversion point of the input inverter to realize the duty ratio adjustment of the input square wave signal.

The above clock method also includes the step of connecting two intermediate inverters and output inverters connected in series to the output terminal of the input inverter to improve the output signal waveform of the duty ratio adjustment circuit.

The above-mentioned oscillating circuit is mainly composed of an input control circuit and N-level end-to-end delay units, wherein each one-level delay unit includes transmission gates and oscillating inverters that are connected in series with each other, and the above-mentioned N is an odd number equal to or greater than 3; the external The input voltage signal is adjusted by the input control circuit to form a complementary voltage signal, and the voltage of the complementary voltage signal is the difference between the voltage of the power supply and the voltage of the input voltage signal. The above-mentioned input voltage signal and complementary voltage signal are respectively sent to the two control terminals of the transmission gates of each delay unit, so that all the transmission gates are switched between on and off states, and prompt the delay unit to generate Square wave signal for tuning range.

The invention provides an adjustable non-overlapping clock generator, which includes a clock generator body. The main body of the clock generator is mainly composed of an oscillation circuit and at least 2 circuits with adjustable duty ratio; among them, 2 or more circuits with adjustable duty ratio are connected in parallel with each other, and the input of each circuit with adjustable duty ratio Both terminals are connected to the output terminal of the oscillation circuit; each duty cycle adjustable circuit has a duty cycle adjustment terminal, and different duty cycle control signals enter the clock generator body from different duty cycle adjustable circuits Middle; the output end of the duty ratio adjustment circuit forms the output end of the clock generator body.

In the above scheme, each duty cycle adjustment circuit is composed of two input inverters and control inverters connected in parallel with each other; the input end of the input inverter forms the input end of the oscillation circuit, and the control inverter The input end of the circuit forms a duty ratio adjustment end, and the input inverter is connected with the output end of the control inverter to form an output end of the duty ratio adjustment circuit.

In order to improve the waveform of the output signal, each of the above-mentioned duty cycle adjustment circuits also includes two intermediate inverters and output inverters that are connected in series; wherein the input terminals of the intermediate inverters are connected between the input inverter and the output inverter. control the output terminal of the inverter, and at this time, the output terminal of the output inverter forms the output terminal of the duty ratio adjustment circuit.

In order to obtain a complementary signal, an output terminal of a complementary signal is also led out from the output terminal of the above-mentioned intermediate inverter.

In order to obtain wide-frequency tuning capability, the above-mentioned oscillation circuit is mainly composed of an input control circuit and N-level end-to-end delay units, wherein each one-level delay unit includes a transmission gate circuit and an oscillation inverter that are connected in series with each other, and the above-mentioned N It is an odd number equal to or greater than 3; the input voltage signal of the external input is divided into two channels immediately after entering the clock generator body, one of which is directly connected to one control terminal of the transmission gate of each delay unit, and the other is passed through After the input control circuit is connected to the other control terminal of the transmission gate of each delay unit; the output terminal of the oscillation inverter of the last delay unit is divided into 2 routes, and 1 route is connected to the first stage as a feedback terminal The input end of the delay unit, and the other one forms the output end of the oscillator circuit.

In order to ensure that the sum of the grid voltages of the transmission gate remains unchanged, the above-mentioned input control circuit is composed of two identical field effect transistors; wherein the source of the first field effect transistor is connected to the positive pole of the power supply, and the second field effect transistor The drain and grid of the first field effect transistor are connected to the negative pole of the power supply; the drain of the first field effect transistor is connected to the source of the second field effect transistor, and the gate of the first field effect transistor forms the input terminal of the input control circuit.

Compared with prior art, the present invention has following characteristics:

1) By connecting at least two duty ratio adjustment circuits in parallel behind the oscillating circuit to generate non-overlapping clock signals, the present invention can integrate oscillation signal generation and non-overlapping clock generation, thus breaking the traditional non-overlapping clock circuit structure , making the circuit a real clock generator;

2) Since the duty cycle control signal of the duty cycle adjustment circuit can be taken out of the clock generator, this can not only flexibly adjust the time interval of the clock signal output by the clock generator, but also generate complementary signals on the premise of simplifying the circuit. Multiple pairs of non-overlapping clocks, non-overlapping high-level regions and/or non-overlapping low-level regions;

3) The oscillating circuit adopts a voltage-controlled oscillator based on the transmission gate. Because the transmission gate can have a wide resistance range as an adjustable equivalent resistance, that is, the oscillating circuit can obtain a wide frequency range, so the present invention can have a wide frequency range of multiple orders of magnitude. It can be widely used in low-frequency fields (such as biomedical signal processing) and high-frequency fields (such as wireless sensor network nodes detecting and processing a certain signal).

Description of drawings

Fig. 1 is a functional block diagram of an adjustable non-overlapping clock generator;

Fig. 2 is the circuit diagram of oscillating circuit;

Fig. 3 is a circuit diagram of a duty ratio adjustment circuit;

Fig. 4 is the equivalent resistance model of Fig. 3;

Fig. 5 is the simulation result of a kind of adjustable non-overlapping clock generator;

FIG. 6 is an enlarged view of the details of FIG. 5 .

Detailed ways

Referring to Fig. 1, a method for generating an adjustable non-overlapping clock of the present invention includes a square wave signal generation step and a square wave signal duty ratio adjustment step, and the square wave signal generated by its oscillator circuit is input to at least two duty ratio adjustment channels respectively. In the circuit, each duty ratio adjustment circuit realizes the duty ratio adjustment of the square wave signal under the action of different duty ratio control signals, thereby obtaining at least two output signals with different duty ratios, which have different duty ratios. The output signal of the duty cycle is the non-overlapping clock signal.

Each of the above-mentioned duty cycle adjustment circuits is composed of two input inverters and control inverters connected in parallel; the square wave signal input from the input inverter input is at the duty cycle Under the adjustment of the ratio control signal, change the inversion point of the input inverter to realize the duty ratio adjustment of the input square wave signal. In order to make the waveform of the final signal better, each duty cycle adjustment circuit also includes two intermediate inverters and output inverters connected in series with each other, and the intermediate inverter and output inverter are connected in series to the above-mentioned input inverters. The flip point of the phase device is used to improve the waveform of the output signal of the duty cycle adjustment circuit.

The above-mentioned oscillating circuit is mainly composed of an input control circuit and N-level end-to-end delay units, wherein each one-level delay unit includes transmission gates and oscillating inverters that are connected in series with each other, and the above-mentioned N is an odd number equal to or greater than 3; the external The input voltage signal is adjusted by the input control circuit to form a complementary voltage signal. The voltage of the complementary voltage signal is the difference between the voltage of the power supply and the voltage of the input voltage signal; the above input voltage signal and complementary voltage signal are respectively sent to each stage The two control terminals of the transmission gates of the delay unit make all the transmission gates switch between on and off states, and prompt the delay unit to generate a square wave signal with a wide frequency tunable range.

This circuit design is based on the transmission gate structure voltage-controlled oscillator (TG-VCO) with adjustable duty cycle. The input signal forms two signals through the input control circuit, and controls and adjusts the transmission gate in the delay unit at the same time. This adjustment is mainly to obtain a wide frequency tuning range for the output signal of the oscillating circuit. After passing through N stages of delay units composed of transmission gates and inverters, the oscillator circuit outputs a square wave signal. In consideration of voltage control of this output signal, its duty cycle can be changed. Following this idea, in order to obtain two-phase non-overlapping clock signals, we propose a parallel voltage control design scheme, using two control voltages to adjust the output signal of the TG-VCO with different duty ratios through the duty ratio adjustment circuit. Therefore, the VCO directly outputs the two-phase non-overlapping clock, and realizes the integration of the generation of the oscillation signal and the generation of the two-phase non-overlapping clock signal.

An adjustable non-overlapping clock generator designed according to the above method, as shown in Figure 1, is mainly composed of an oscillating circuit and at least 2 circuits with adjustable duty ratios; The adjustable circuits are connected in parallel, and the input end of each duty cycle adjustable circuit is connected to the output end of the oscillation circuit; each duty cycle adjustable circuit has a duty cycle adjustment end, different duty cycle Duty ratio control signals enter the clock generator body from different duty ratio adjustable circuits; the output end of the duty ratio adjustment circuit forms the output end of the clock generator body.

In order to obtain wide frequency tuning capability, in the present invention, the oscillation circuit adopts a voltage-controlled oscillator (TG-VCO) based on a transmission gate structure. That is, the oscillating circuit is mainly composed of an input control circuit and N stages of end-to-end delay units, wherein each stage of delay units includes a transmission gate circuit and an oscillating inverter that are connected in series with each other. The above-mentioned N is an odd number equal to or greater than 3, such as N=3, 7, 9, 11 . . . In this embodiment, a three-stage delay unit is used. The input voltage signal input from the outside is divided into two channels immediately after entering the clock generator body, one of which is directly connected to a control terminal of the transmission gate of each level of delay unit, and the other is connected to each of the transmission gates after passing through the input control circuit. The other control terminal of the transmission gate of the first-stage delay unit; the output terminal of the oscillation inverter of the last-stage delay unit is divided into two routes, and one route is connected to the input terminal of the first-stage delay unit as a feedback terminal, The other one forms the output end of the oscillator circuit. Since the transmission gate is composed of an N-channel field effect transistor and a P-channel field effect transistor connected in parallel, and the sum of the voltages used to control the grid of the N-channel field effect transistor and the gate of the P-channel field effect transistor is Vdd. Therefore, in order to ensure that the sum of the grid voltage Vdd remains unchanged, in the present invention, two identical field effect transistors can be used to form the input control circuit. Wherein the source of the first FET is connected to the positive pole of the power supply, the drain and the grid of the second FET are connected to the negative pole of the power supply; the drain of the first FET is connected to the source of the second FET The poles are connected, and the grid of the first field effect transistor forms the input terminal of the input control circuit. See Figure 2.

By adjusting the input voltage control signal of the transmission gate circuit to change the working area of the transistor, so that the transmission gate is switched between the on state and the off state, the equivalent resistance of the transmission gate, and the delay unit composed of the inverter and the transmission gate are simultaneously changes, so that the frequency of the output signal of the oscillation circuit can be controlled by the voltage, and the relationship between the frequency and the equivalent resistance of the transmission gate is shown in the following formula:

$f_{\mathrm{osc}}=\frac{1}{2\·N\·\mathrm{\τ}}=\frac{1}{2\·N\·(\frac{1}{G_m}+R_{\mathrm{tg}})\&Center\; Dot;C_g}$ ①

In the above formula, N is the number of delay units, τ is the delay of each unit, Gm is the transconductance of the inverter, Rtg is the equivalent resistance of the transmission gate, and Cg is the parasitic capacitance. Because Gm and Cg are device parameters and are generally considered constants, the oscillation frequency is mainly affected by Rtg.

Considering the voltage control of the output signal of the oscillation circuit, its duty cycle can be changed. Following this idea, in order to obtain two-phase non-overlapping clocks, the present invention proposes a parallel voltage control design scheme, using two control voltages to adjust different duty ratios of the output signal of the TG-VCO, so that the VCO directly outputs The two phases do not overlap the clock. To change the duty cycle of the output signal of the oscillator circuit, it is actually necessary to change the ratio of the high level to the low level within a signal cycle. When both the PMOS transistor and the NMOS transistor constituting the inverter are saturated, its voltage transfer characteristic curve is approximately a vertical line segment, and the ideal gain in this region is infinite. The flip point, also known as the flip threshold, is defined as the point at which the input and output voltages of the inverter are equal. When the two transistors of the inverter are in the saturation region, the transition between high and low levels can be realized by changing the flip point of the inverter, thereby changing the duty cycle of the output signal. The duty ratio adjustment circuit used to control the TG-VCO output signal is shown in Figure 3, that is, each duty ratio adjustment circuit is composed of two input inverters and control inverters that are connected in parallel with each other. The input inverter is composed of transistor M15 and transistor M16, the input terminal of the input inverter forms the input terminal of the oscillation circuit, and the square wave signal Vin output by TG-VCO is input from it; the control inverter is composed of transistor M17 and transistor M18 structure, the input end of the control inverter forms a duty ratio adjustment end, and the duty ratio control signal Vduty is input from it; the input inverter is connected with the output end of the control inverter to form the duty ratio adjustment circuit. Inversion point: In order to make the waveform of the final signal better, two inverters are connected in series after the inversion point of the above-mentioned duty ratio adjustment circuit. That is to say, each duty cycle adjustment circuit includes two intermediate inverters and output inverters connected in series; the intermediate inverter is composed of a transistor M19 and a transistor M20, and the input terminal of the intermediate inverter is connected to On the output terminals of the input inverter and the control inverter, the output terminal of the intermediate inverter is a complementary signal output terminal, and the complementary output signal Vout' is output from this; the output inverter is composed of a transistor M21 and a transistor M22, the The input terminal of the output inverter is connected to the output terminal of the middle inverter, and the output terminal of the output inverter forms the output terminal of the duty cycle adjusting circuit, and the output signal Vout is outputted therefrom.

Assuming that all the tubes work in the saturation region, the equivalent resistance model of the input inverter and the control inverter is shown in Figure 4, and the node voltage Vb can be calculated by the following formula:

$\mathrm{Vb}=\frac{R16\left|\right|R18}{R15\left|\right|R17+R16\left|\right|R18}\&Center\; Dot;\mathrm{Vdd}$ ②

R is the on-resistance of the FET, and R17 and R18 can be regarded as variable resistors. Adjust Vduty to control the resistance of R17 and R18, and the value of Vb will also change accordingly. Therefore, the inversion point of the input inverter composed of M15 and M16 can be controlled by Vduty, thereby adjusting the duty cycle of the output signal of the oscillator circuit.

In this embodiment, the non-overlapping clock generator shown in the functional block diagram of FIG. 1 can be realized by connecting the input Vin of the two duty ratio adjustment circuits in parallel to the output of the oscillator circuit in FIG. 2 . Vduty1 and Vduty2 are the control voltages of the two duty ratio adjustment circuits respectively. By setting these two control voltages, output signals with different duty ratios are obtained, thereby generating non-overlapping clock pairs. Since the intermediate inverter and the output inverter can output mutually inverse signals, a complementary signal output terminal can be added after the intermediate inverter, then the signal nclk1 output by the complementary signal output terminal will be the same as that originally set at the output The signal clk1 output from the signal output end after the inverter is a pair of clock signals that are inverse and complementary to each other. According to the solution, if each duty cycle circuit can output a pair of anti-complementary clock signals, then different non-overlapping clock signals can be obtained. Take the parallel connection of two duty cycle circuits in Figure 4 as an example, then a total of 4 signals can be output, namely clk1, nclk1, clk2, nclk2, and the waveforms of these 4 signals are shown in Figure 5 and Figure 6. which has:

2 sets of complementary non-overlapping clock signals: clk1 and nclk1, clk2 and nclk2. Their characteristic is that when clk is high, nclk is low, and the high and low levels never overlap.

1 set of high-level non-overlapping clock signals: clk1 and clk2. Their low-level parts can overlap.

1 set of low-level non-overlapping clock signals: nclk1 and nclk2. Their high level parts can overlap.

It can be seen that how many pairs of complementary non-overlapping clock signals, that is, clk and nclk, can be output as many circuits with adjustable duty ratios are connected in parallel.

When the output terminal of the oscillating circuit is connected with only one duty cycle adjustable circuit, only one set of complementary non-overlapping clock signals is output.

When the output terminal of the oscillator circuit is connected in parallel with 2 duty cycle adjustable circuits, 2 sets of complementary signals can be output, 1 set of high level non-overlapping signals, and 1 set of low level non-overlapping signals.

When the output terminal of the oscillation circuit is connected in parallel with 3 duty cycle adjustable circuits, 3 groups of complementary signals can be output, 3 groups of high level parts do not overlap signals, and 3 groups of low level parts do not overlap signals. For example, by adjusting the different signal duty ratios of the 3-way duty ratio adjustment circuit, 6 signals are output: clk1 (44% of the high level part), nclk1 (56%), clk2 (80%), nclk2 (20%) %), clk3 (60%), nclk3 (40%). which has:

3 sets of complementary non-overlapping signal pairs: clk1 and nclk1, clk2 and nclk2, clk3 and nclk3.

3 groups of high-level non-overlapping signal pairs: clk1 and nclk2, clk1 and nclk3, clk3 and nclk2.

3 groups of non-overlapping signal pairs of low level parts: clk2 and nclk1, clk2 and nclk3, clk3 and nclk1.

Therefore, the present invention can obtain multiple pairs of non-overlapping clock signals through parallel connection of multiple duty ratio adjustment circuits, including complementary non-overlapping signal pairs, high-level non-overlapping signal pairs and low-level non-overlapping signal pairs.

Claims (10)

1. An adjustable non-overlapping clock generation method, characterized in that: the square wave signal generated by the oscillating circuit is respectively input into at least 2 road duty ratio adjustment circuits, and every 1 road duty ratio adjustment circuit is controlled at different duty ratios Under the action of the signal, the duty ratio adjustment of the square wave signal is realized, thereby obtaining at least two output signals with different duty ratios, and these output signals with different duty ratios are non-overlapping clock signals. 2. A kind of adjustable non-overlapping clock generation method according to claim 1, is characterized in that: every 1 road duty cycle adjusting circuit is all made of 2 input inverters and control inverters that form parallel connection with each other; The square wave signal input from the input terminal of the input inverter is adjusted by the duty cycle control signal input from the control inverter, and the inversion point of the input inverter is changed to realize the duty cycle adjustment of the input square wave signal. 3. A kind of adjustable non-overlapping clock generation method according to claim 2, is characterized in that: also comprise on the output end of input inverter, connect in series 2 mutually form the middle inverter of series connection and output inverter The step of improving the output signal waveform of the duty ratio adjustment circuit by means of the device. 4. A method for generating an adjustable non-overlapping clock according to any one of claims 1 to 3, wherein the oscillating circuit is mainly composed of an input control circuit and N-level end-to-end delay units, wherein each 1 The first-stage delay unit includes a transmission gate and an oscillating inverter that are connected in series with each other, and the above-mentioned N is an odd number equal to or greater than 3; the input voltage signal input from the outside is adjusted by the input control circuit to form a complementary voltage signal, and the voltage of the complementary voltage signal The size is the difference between the voltage of the power supply and the voltage of the input voltage signal; the above-mentioned input voltage signal and complementary voltage signal are respectively sent to the two control terminals of the transmission gate of each 1-stage delay unit, so that all transmission gates are turned on and off Switch between states and cause the delay unit to generate a square wave signal with a wide frequency tunable range. 5. An adjustable non-overlapping clock generator, including a clock generator body, characterized in that: the clock generator body is mainly composed of an oscillation circuit and at least 2 circuits with adjustable duty ratio; wherein 2 or more than 2 circuits The adjustable duty cycle circuits are connected in parallel, and the input end of each adjustable duty cycle circuit is connected to the output end of the oscillation circuit; each adjustable duty cycle circuit has a duty cycle adjustment end, Different duty ratio control signals enter the clock generator body from different duty ratio adjustable circuits; the output end of the duty ratio adjustment circuit forms the output end of the clock generator body. 6. A kind of adjustable non-overlapping clock generator according to claim 5, characterized in that: every 1-way duty ratio adjustment circuit is composed of 2 input inverters and control inverters that are connected in parallel with each other; The input terminal of the input inverter forms the input terminal of the oscillating circuit, the input terminal of the control inverter forms the duty ratio adjustment terminal, and the input inverter is connected with the output terminal of the control inverter to form the duty ratio adjustment circuit. output terminal. 7. A kind of adjustable non-overlapping clock generator according to claim 6, characterized in that: each duty ratio adjustment circuit of 1 path also includes 2 intermediate inverters and output inverters connected in series with each other; The input terminal of the intermediate inverter is connected to the output terminals of the input inverter and the control inverter, and at this time, the output terminal of the output inverter forms the output terminal of the duty ratio adjustment circuit. 8. An adjustable non-overlapping clock generator according to claim 7, characterized in that: the output terminal of the intermediate inverter also leads to a complementary signal output terminal. 9. An adjustable non-overlapping clock generator according to any one of claims 5-8, characterized in that: the oscillation circuit is mainly composed of an input control circuit and N stages of delay units connected in series, wherein each The first-level delay unit includes a transmission gate circuit and an oscillation inverter that form a series connection with each other, and the above-mentioned N is an odd number equal to or greater than 3; the input voltage signal input from the outside is divided into 2 paths immediately after entering the clock generator body, of which 1 One way is directly connected to one control terminal of the transmission gate of each level of delay unit, and the other way is connected to the other control terminal of each level of delay unit transmission gate after passing through the input control circuit; the oscillation of the last level of delay unit The output terminal of the inverter is divided into two channels, one channel is used as a feedback terminal and connected to the input terminal of the first-stage delay unit, and the other channel is used as an output terminal of the oscillation circuit. 10. An adjustable non-overlapping clock generator according to claim 9, characterized in that: the input control circuit is composed of two identical field effect transistors; wherein the source of the first field effect transistor is connected to the power supply The positive pole of the power supply is connected, the drain and grid of the second field effect transistor are connected with the negative pole of the power supply; the drain of the first field effect transistor is connected with the source of the second field effect transistor, and the gate of the first field effect transistor Form the input terminal of the input control circuit.

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