CN102412806B - The Farrow wave filters and its implementation of logic-based circuit - Google Patents
The Farrow wave filters and its implementation of logic-based circuit Download PDFInfo
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Abstract
The invention discloses a kind of Farrow wave filters of logic-based circuit and its implementation, the wave filter includes：Gating switch, for the input data sampling rate according to configuration and the proportionate relationship of output data sampling rate, controls the mode of operation of Farrow wave filters；Filtering interpolation device, under the control of gating switch, filtering interpolation to be carried out to input data, and during filtering interpolation, carries out cut position operation to intermediate data according to the first setting bit wide, obtains first kind fixed-point data；Decimation filtering apparatus, under the control of gating switch, filtering extraction to be carried out to input data, and during filtering extraction, carries out cut position operation to intermediate data according to the second setting bit wide, obtains Equations of The Second Kind fixed-point data.The present invention solves existing Farrow filter hardwares framework underaction, the problem of Configuration Online speed is not supported, and reduces the resource occupation of hardware by the cut position operation to intermediate data.
Description
Technical Field
The invention relates to the field of communication, in particular to a Farrow filter based on a logic circuit and an implementation method thereof.
Background
The Farrow filter has the greatest characteristic of being capable of realizing conversion of an arbitrary sampling rate of a signal by using a set of fixed coefficients. Its theoretical basis is based on a continuous-time model, as shown in fig. 1.
The Farrow filter functions to implement the process of fig. 1 entirely in the digital domain: 1) using an ideal DAC and an analog filter ha(t) recovering the digital signal x (k) to a quasi-original signal ya(t); 2) for ya(t) resampling to obtain a rate-converted digital signal y (l). Filter haThe performance of (t) determines the time and frequency domain quality of the output signal.
The digitization of the simulation process can be completely deduced and proved by mathematical theory, and mathematical models of the Farrow filter under two conditions of interpolation and extraction can be obtained respectively. The most abstract logical hardware implementation model can be obtained from the mathematical model.
1. Under the condition of interpolation
Time coefficient mulTo representThe time interval between the current output sample and the most recent previous input sample, and the input sampling period TinNormalized as shown in fig. 2.
The interpolation structure of the Farrow filter is shown in fig. 3. Each output sample y (l) is calculated for a set of input samples, which is passed through M +1 sub-filters Ci(z) filtering, v of the outputm(nl) Are respectively linked with (2 mu)l-1)mAnd multiplying and accumulating to obtain the resampled output sample. The sub-filters all operating at the input sampling rate, vm(nl) And (2 mu)l-1)mThe multiplication operation of (a) operates at the output sample rate.
2. In the case of extraction
Time coefficient mukRepresenting the time interval between the current input sample and the most recent previous output sample, and the output sampling period ToutAnd (6) normalizing. The decimation structure of the Farrow filter is shown in fig. 4. The calculation of each output sample y (l) corresponds to a set of input samples, each sample corresponding to a respective (2 μm)k-1)mAfter multiplication, the data is accumulated in segments by using the upper and lower limits of the index, that is, in each output sampling period, the accumulator sends a group of calculated data (i.e. input samples) to the sub-filter Ci(z), adding the output results of the sub-filters to obtain the extracted output sample y (l). In this configuration, the sample and (2 μ) are inputk-1)mThe multiplication and accumulator operations of (a) operate at the input sampling rate and the sub-filters all operate at the output sampling rate.
When the Farrow filter is used for fractional delay, the sampling rate of the signal is not changed, and the mathematical model and logic implementation block diagram of the Farrow filter can be regarded as a special case in the interpolation case.
The foregoing background describes a mathematical model of a Farrow filter and corresponding software implementation flow, which has been studied and analyzed on a number of published technical data. Much of the current research on Farrow filters is focused on finding how to find betterFilter bank Ci(z) to better meet the performance requirements for time and frequency domains in a certain signal processing application scenario or scenarios.
Farrow filters are generally divided into software and logic hardware implementations. The software implementation is that a software program is used in a Processor chip such as a Digital Signal Processor (DSP) to perform floating point calculation and implementation, which is suitable for non-real-time calculation or real-time calculation when the data sampling rate is very low. The software implementation can be carried out by full floating point, and the calculation can be carried out by fully using a mathematical model of a Farrow filter.
The real-time Farrow filter processing of the intermediate frequency signals is suitable for being realized by using a fixed-point logic circuit, and at the moment, the data sampling rate is high, so that the DSP processor is difficult to bear the large calculation amount. But there is currently no fixed-point logic implementation for Farrow filters.
Aiming at the problems that the hardware architecture of the existing Farrow filter in the related art is not flexible enough and does not support the online configuration rate, an effective solution is not provided at present.
Disclosure of Invention
Aiming at the problem that the hardware architecture of the conventional Farrow filter is not flexible enough and does not support on-line configuration rate, the invention provides a Farrow filter based on a logic circuit and an implementation method thereof, so as to at least solve the problem.
According to an aspect of the present invention, there is provided a logic circuit based Farrow filter, comprising: the gating switch is used for controlling the working mode of the Farrow filter according to the proportion relation between the configured input data sampling rate and the configured output data sampling rate; the interpolation filtering device is used for performing interpolation filtering on input data under the control of the gating switch, and performing bit cutting operation on intermediate data according to a first set bit width in the interpolation filtering process to obtain first type fixed point data; and the extraction filtering device is used for extracting and filtering the input data under the control of the gating switch, and performing bit cutting operation on the intermediate data according to a second set bit width in the process of extracting and filtering to obtain second-class fixed point data.
Preferably, the interpolation filtering means and the decimation filtering means share a set of sub-filters, which support the function of coefficient on-line configuration.
Preferably, the interpolation filtering means comprises a set of sub-filters, a set of multipliers and a set of adders; each multiplier of a group of multipliers is connected with a multiplication truncator, and the multiplication truncator is used for truncating the output result of the multiplier according to a first set bit width to obtain first type fixed point data.
Preferably, each multiplier receives a time coefficient uiv 2 ui-I, where ui μi*I，μiMod (D × l, I)/I, I being a set difference multiple, D being a set decimation multiple; l is the data index of the output clock domain; mod () is the remainder computation.
Preferably, the coefficient c of each sub-filter of the set of sub-filters is a coefficient of a sub-filter of the set of sub-filtersm' (n) is determined using the following formula:where M is the quantization bit width of the set of sub-filter coefficients, cm(n) is the normalized floating point coefficient of the mth sub-filter; n is the sequence number, N-0, 1.... cndot.n-1; n is the sequence length; m is an integer of 0 or more; round () is a round calculation; NI is the first set bit width,an addition truncator is arranged between the group of adders and the data output end and is used for truncating lower M bits of a result operated by the group of adders.
Preferably, the Farrow filter further comprises a first logic hardware system, and the first logic hardware system comprises: the first restorer is used for resetting the first logic hardware system and resetting uiv, rd _ flag and temporary variable t as initial values, wherein rd _ flag is a clock domain conversion read address identifier; the first variable processor is used for setting t to t + D when each output clock arrives, judging whether t is larger than I or not, if so, setting t to t-I, adding 1 to rd _ flag, and if not, keeping t and rd _ flag unchanged; and the first time coefficient generator is used for setting the time coefficient uiv-2 t-I corresponding to each output clock.
Preferably, the decimation filtering means comprises a set of sub-filters, a set of multipliers, a set of accumulators and a set of adders; each multiplier of the group of multipliers is connected with a multiplication truncator, the multiplication truncator is used for truncating the output result of the multiplier according to a second set bit width and inputting truncated data into a corresponding accumulator; and an accumulation truncator is arranged between each accumulator and the sub-filter and is used for truncating the result output by the accumulator to obtain second type fixed point data.
Preferably, the time coefficient received by each multiplier is udv-2 ud-D, where ud- μd*D，μdMod (I × k, D)/D, I being a set difference multiple and D being a set decimation multiple; k is the data index of the output clock domain; mod () is the remainder computation.
Preferably, the coefficient c of each sub-filter of a set of sub-filtersm' (n) is determined using the following formula:where M is the quantization bit width of the set of sub-filter coefficients, cm(n) is the normalized floating point coefficient of the mth sub-filter; m is an integer of 0 or more; round () is a round calculation; ND is a second set bit width,NP being cumulative cutoffThe bit-truncating bit of the bit slicer is wide,an addition truncator is arranged between the group of adders and the data output end and is used for truncating lower M bits of a result operated by the group of adders.
Preferably, the Farrow filter further comprises a second logic hardware system, and the second logic hardware system comprises: the second restorer is used for restoring the second logic hardware system and restoring the udv, the clr _ flag and the temporary variable t into initial values, wherein the clr _ flag is a clear identifier of the feedback input end of the accumulator and an effective identifier of output data; the second variable processor is used for setting t to t + I when each output clock arrives, judging whether t is larger than D or not, if so, setting t to t-D, setting clr _ flag to 1, and if not, keeping t and rd _ flag unchanged; and the second time coefficient generator is used for setting the time coefficient udv-2 t-D corresponding to each output clock.
According to another aspect of the present invention, there is provided a method for implementing a Farrow filter based on a logic circuit, including: determining the working mode of the Farrow filter according to the proportion relation between the configured input data sampling rate and the configured output data sampling rate; when the working mode is interpolation filtering, in the process of interpolation filtering, bit cutting operation is carried out on the intermediate data according to a first set bit width to obtain first type fixed point data; and when the working mode is the extraction filtering, in the process of extracting the filtering, performing bit cutting operation on the intermediate data according to the second set bit width to obtain second type fixed point data.
By adopting the method and the device, the interception operation is carried out on the intermediate data in the filtering process, the hardware resource occupation is reduced, so the Farrow filter can be applied to the processing of various signals (including real-time signals and non-real-time signals), and meanwhile, the signal processing gain of the framework is controllable, thereby solving the problems that the Farrow filter in the related technology is not flexible enough in hardware framework and does not support the on-line configuration rate. By arranging the gating switch, the interpolation and extraction functions of the Farrow filter can be integrated, so that the function of the Farrow filter is not single any more, and the market competitiveness of the Farrow filter is enhanced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a raw theoretical model of a Farrow filter according to the related art;
FIG. 2 is a time domain schematic of Farrow filter input and output sample points and time coefficients according to the related art;
FIG. 3 is a mathematical theory implementation model of a Farrow filter in interpolation mode according to the related art;
FIG. 4 is a mathematical theory implementation model of a Farrow filter in decimation mode according to the related art;
FIG. 5 is a block diagram of a Farrow filter based on logic circuitry according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an interpolation filtering apparatus according to an embodiment of the present invention;
FIG. 7 is a detailed schematic diagram of an interpolation filtering apparatus according to an embodiment of the invention;
FIG. 8 is a schematic diagram of a method for generating time coefficients input by an interpolation filter according to an embodiment of the present invention;
FIG. 9 is a block diagram of a logical hardware system for generating interpolated time coefficients according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a decimation filtering apparatus according to an embodiment of the present invention;
fig. 11 is a detailed schematic diagram of a decimation filtering apparatus according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a method for generating time coefficients input by a decimation filtering apparatus according to an embodiment of the present invention;
FIG. 13 is a block diagram of a logical hardware system for generating decimation time coefficients according to an embodiment of the present invention;
FIG. 14 is a flow chart of a method for implementing a Farrow filter based on logic circuitry according to an embodiment of the present invention;
fig. 15 is a schematic diagram of a specific structure of a Farrow filter based on a logic circuit according to an embodiment of the present invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The embodiment of the invention provides a Farrow filter based on a logic circuit and an implementation method thereof.
When implementing the Farrow filter using the logic circuit, at least the following problems need to be considered:
1. time coefficient mulAnd mukThe two time coefficients are floating point data which are determined by input and output sampling rates and change in real time, and the time coefficients need to be subjected to fixed-point processing and real-time online calculation;
2. and (4) truncating the time coefficient and the data multiplication. From the mathematical model, it can be seen that the different powers of the time coefficient have the multiplied calculation with the input or output data of the sub-filter, which brings the multiplied increase of the calculation bit width in the process of fixed-point, and the full-precision calculation is basically impossible and needs a reasonable bit-cutting operation.
In view of the foregoing problems, the present embodiment provides a Farrow filter based on a logic circuit, and as shown in fig. 5, the Farrow filter based on a logic circuit according to an embodiment of the present invention includes: a gating switch 52, an interpolation filter 54, and a decimation filter 56. Wherein,
a gating switch 52, configured to control a working mode of the Farrow filter according to a proportional relationship between the configured input data sampling rate and the configured output data sampling rate;
the interpolation filtering device 54 is connected with the gating switch 52 and used for performing interpolation filtering on input data under the control of the gating switch 52 and performing bit cutting operation on intermediate data according to a first set bit width in the interpolation filtering process to obtain first type fixed point data;
and the decimation filtering device 56 is connected to the gating switch 52, and is configured to perform decimation filtering on the input data under the control of the gating switch 52, and perform a bit truncation operation on the intermediate data according to a second set bit width in the decimation filtering process to obtain second type fixed point data.
In the embodiment, the hardware resource occupation is reduced by performing the bit-cutting operation on the intermediate data in the filtering process, so that the Farrow filter can be applied to processing various signals (including real-time signals and non-real-time signals), and meanwhile, the signal processing gain of the architecture is controllable, thereby solving the problems that the Farrow filter in the related art is not flexible enough in hardware architecture and does not support the on-line configuration rate. By arranging the gating switch, the interpolation and extraction functions of the Farrow filter can be integrated, so that the function of the Farrow filter is not single any more, and the market competitiveness of the Farrow filter is enhanced.
The operating mode of the Farrow filter in the embodiment of the present invention may be an interpolation operating modeThe interpolation mode may include a specific example, fractional delay mode. FIG. 6 is a schematic diagram of an interpolation filtering apparatus according to an embodiment of the present invention, as shown in FIG. 6, the apparatus includes a set of sub-filters Ci(z), a set of multipliers (used in the figure)Shown) and a set of adders (shown asThat is, in the above-mentioned publication), wherein,
each multiplier in the group of multipliers is connected with a multiplication truncator, and the multiplication truncator is used for truncating the output result of the multiplier according to a first set bit width to obtain first type fixed point data.
The time coefficient 2 mu received at each multiplier in fig. 6 is embodied in a logic circuitiWhen the time coefficient is-1, the time coefficient received by each multiplier is uiv-2 ui-I, wherein ui-mui*I，I is a set difference multiple, and D is a set extraction multiple; l is the data index of the output clock domain; mod () is the remainder computation. The value l is a continuously variable integer from 0 to N-1, and it is assumed that Tout is the output data sampling period, 0 corresponds to time 0, 1 corresponds to time 1 × Tout, and 2 corresponds to time 2 × Tout.
The common fixed-point implementation filter processing requires that the gain of a signal in a pass band is guaranteed to be 0dB or a certain fixed gain required by a user, and the floating-point calculation generally does not have the problem. In view of this problem, the embodiment of the present invention employs the filter bank C described aboveiAnd (z) quantizing the time coefficient, performing multiplication truncation on the time coefficient, performing truncation on an accumulator and the like, and finishing comprehensive trade-off and compensation on floating point data. Based on this, as shown in fig. 7, a specific example of an interpolation filter device according to an embodiment of the present inventionIt is intended that the arrangement is modified on the basis of fig. 6 in that an addition truncator is arranged between the set of adders and the data output, and that, on the basis of fig. 7, the sub-filter C is arrangediCoefficient of (z) cm' (n) is determined using the following formula:where M is the quantization bit width of a set of sub-filter coefficients, cm(n) is the normalized floating point coefficient of the mth sub-filter; n is the sequence number, N-0, 1.... cndot.n-1; n is the sequence length; m is an integer of 0 or more; round () is a round calculation; NI is the first set bit width,the addition truncator is used for truncating lower M bits of a result operated by a group of adders. This approach ensures that the gain of the signal within the passband is 0dB or some fixed gain required by the user.
In order to obtain the time coefficient received by each multiplier in the interpolation filter device, a logical hardware system is set in a Farrow filter in the embodiment, see a schematic diagram of a method for generating the time coefficient input by the interpolation filter device shown in fig. 8, during initialization, uiv, rd _ flag, and a temporary variable t are reset to initial values, where the initial values of the quantities in the embodiment are all 0, and rd _ flag is a clock domain conversion read address identifier; when each output clock comes, setting t to t + D, judging whether t is larger than I, if so, setting t to t-I, adding 1 to rd _ flag, and if not, keeping t and rd _ flag unchanged; and setting the time coefficient uiv-2 t-I corresponding to each output clock.
Based on the time coefficient generation method in fig. 8, in this embodiment, a logical hardware system is adopted to implement the method, and as shown in a structural block diagram of the logical hardware system in fig. 9, the logical hardware system includes: a resetter 92, configured to reset the logic hardware system, and reset uiv, rd _ flag, and a temporary variable t to initial values, where rd _ flag is a clock domain conversion read address identifier; a variable processor 94, connected to the resetter 92, for setting t to t + D when each output clock arrives, and determining whether t is greater than I, if yes, setting t to t-I, and adding 1 to rd _ flag, if no, t and rd _ flag are unchanged; and a time coefficient generator 96, connected to the variable processor 94, for setting the time coefficient uiv-2 × t-I corresponding to each output clock.
FIG. 10 is a schematic diagram of a decimation filtering apparatus according to an embodiment of the present invention, as shown in FIG. 10, the apparatus includes a set of sub-filters, a set of multipliers, and a set of adders; wherein a group of sub-filters Ci(z), a set of multipliers (used in the figure)Shown), a set of accumulators (shown as ∑) and a set of adders (shown as ∑)And the multiplier of the group of multipliers is connected with a multiplication truncator, and the multiplication truncator is used for truncating the output result of the multiplier according to a second set bit width and inputting the truncated data into a corresponding accumulator; and an accumulation truncator is arranged between each accumulator and the sub-filter and is used for truncating the result output by the accumulator to obtain second type fixed point data.
Fig. 11 is a specific schematic diagram of a decimation filtering apparatus according to an embodiment of the present invention, which is improved on the basis of fig. 10, that is, an addition truncator is arranged between the group of adders and the data output terminal, and each multiplier receives a time coefficient of 2 μ based on fig. 11dAt time-1, the time coefficient received by each multiplier is udv-2 ud-D, where ud μd*D，μdMod (I × k, D)/D, I being a set difference multiple and D being a set decimation multiple; k is the data index of the output clock domain; mod () is the remainder computation.
Of each sub-filter of the above-mentioned group of sub-filtersCoefficient cm' (n) is determined using the following formula:where M is the quantization bit width of a set of sub-filter coefficients, cm(n) is the normalized floating point coefficient of the mth sub-filter; m is an integer of 0 or more; round () is a round calculation; ND is a second set bit width,NP is the bit width of the accumulated truncator,the addition truncator is used for truncating lower M bits of a result operated by a group of adders. This approach ensures that the gain of the signal within the passband is 0dB or some fixed gain required by the user.
In order to obtain the time coefficient received by each multiplier in the decimation filter device, a logical hardware system is set in the Farrow filter in the embodiment, see the schematic diagram of the generation method of the time coefficient input by the decimation filter device shown in fig. 12, during initialization, udv, clr _ flag and temporary variable t are reset to initial values, the initial values of the quantities in the embodiment are all 0, wherein clr _ flag is a clear identifier at the feedback input end of the accumulator and an effective identifier of output data; when each output clock arrives, setting t to t + I, judging whether t is larger than D, if so, setting t to t-D, setting clr _ flag to 1, and if not, keeping t and rd _ flag unchanged; and setting the time coefficient udv-2 t-D corresponding to each output clock.
Based on the time coefficient generation method in fig. 12, this embodiment adopts a logic hardware system to implement the method, and as shown in a structural block diagram of the logic hardware system in fig. 13, the logic hardware system includes: the resetter 132 is configured to reset the logic hardware system, and reset the udv, the clr _ flag, and the temporary variable t to initial values, where the clr _ flag is a clear flag at a feedback input end of the accumulator and an effective flag of output data; a variable processor 134, connected to the resetter 132, configured to set t to t + I when each output clock arrives, and determine whether t is greater than D, if yes, set t to t-D, and set clr _ flag to 1, and if no, t and rd _ flag are unchanged; and a time coefficient generator 136, connected to the variable processor 134, for setting the time coefficient udv-2 × t-D corresponding to each output clock.
The decimation factor D, the interpolation factor I and the filter bank Ci(z) is configurable online.
The interpolation filtering device 54 and the decimation filtering device 56 may share a set of sub-filters that support the function of coefficient on-line configuration. This way, hardware can be saved and cost can be reduced.
Corresponding to the Farrow filter, the embodiment also provides a method for implementing the Farrow filter based on the logic circuit. Taking the Farrow filter shown in fig. 5 as an example, referring to a flowchart of an implementation method of the Farrow filter based on the logic circuit shown in fig. 14, the method includes the following steps:
step S142, determining the working mode of the Farrow filter according to the proportion relation between the configured input data sampling rate and the configured output data sampling rate;
step S144, when the working mode is interpolation filtering, in the process of interpolation filtering, bit cutting operation is carried out on the intermediate data according to a first set bit width to obtain first type fixed point data;
and step S146, when the working mode is the extraction filtering, in the process of the extraction filtering, bit cutting operation is carried out on the intermediate data according to the second set bit width to obtain second type fixed point data.
In the embodiment, the hardware resource occupation is reduced by performing the bit-cutting operation on the intermediate data in the filtering process, so that the Farrow filter can be applied to processing various signals (including real-time signals and non-real-time signals), and meanwhile, the signal processing gain of the architecture is controllable, thereby solving the problems that the Farrow filter in the related art is not flexible enough in hardware architecture and does not support the on-line configuration rate. The working mode of the Farrow filter is determined according to the proportion relation between the configured input data sampling rate and the configured output data sampling rate, the interpolation and extraction functions of the Farrow filter can be fused together, the function of the Farrow filter is not single any more, and the market competitiveness of the Farrow filter is enhanced.
The following description is made in conjunction with a preferred embodiment which combines the above embodiments and preferred embodiments. This embodiment provides a Farrow filter based on a logic circuit, and as shown in fig. 15, a specific structural diagram of the Farrow filter based on the logic circuit includes a decimation multiple D, an interpolation multiple I, and a filter bank C in the Farrow filter based on the logic circuiti(z) is reconfigurable online, and the present embodiment is compatible with both interpolation and decimation modes of operation by adding three gate switch controllers K1, K2, and K3, wherein the switches are set to operate in the decimation mode as shown by the dashed lines and to operate in the interpolation mode as shown by the solid lines. The present embodiment adds configurable truncations after the accumulator and multiplier, which can be used to accommodate the limited data bit width requirements of fixed point computation on the one hand and to meet the control requirements of processing gain on the other hand.
K2 bypasses multiplication and ND truncation, K3 bypasses accumulator and NP truncation, and K1 corresponds to an interpolation scenario where D is less than or equal to I when multiplication and NI truncation are enabled. K2 enables multiplication and ND truncate, K3 enables accumulator and NP truncate, and K1 corresponds to the decimation scenario of D > I when the multiplication and NI truncate are bypassed.
The Farrow filter is used for decimal sampling delay and has the same structure as an interpolation working mode, and only the calculation and configuration of time coefficients and the calculation method of the NI truncation bit width are different.
The interpolation factor I and the decimation factor D can be used to represent the proportional relationship of the input and output data sampling rates, so the time coefficients in both cases of interpolation and decimation can be expressed as the following equations (1) and (2), respectively.
μi＝mod(D*l，I)/I (1)
μd＝mod(I*k，D)/D (2)
mod represents the remainder calculation. Both of these time coefficients are floating point decimals, which cannot be directly computed by logic hardware. The amplification of the I times and the D times becomes fixed-point remainder calculation, which can be calculated in logic hardware. As shown in the following equations (3) and (4), the time coefficients to be calculated become ui and ud of fixed point integers. Corresponding to 2 μ which will already correspond to the mathematical model in fig. 15i-1 and 2. mu.d-1 magnifies I times and D times to 2 ui-I and 2 ud-D, respectively.
ui＝μi*I＝mod(D*l，I) (3)
ud＝μd*D＝mod(I*k，D) (4)
Because the time coefficient is respectively enlarged by I times and D times, the data processing must restore the benefits of I times and D times, and the I and D are divided into two parts of 2, namely, the integer power part and the decimal part, wherein the 2 integer power part is directly truncated, and the truncated bit width is shown in formulas (5) and (6).
In FIG. 15, 2^ NI and 2^ ND are configurable rounding truncation operations, which truncate the low NI and low ND bits of the previous stage to cancel the integer power gain of 2. The remaining fractional part of the gain is processed in the quantization of the filter coefficients.
M is the quantization bit width of the sub-filter coefficients, and the interpolation filter coefficient quantization formula is shown in (7).
Round in equation (7) is a rounding calculation,which is used to counteract the effect of the fractional part of the time coefficient amplified by I times, except for the integer power of 2. The right side of the formula is a normalized floating point coefficient, the left side of the formula is a fixed point coefficient, the coefficient is a data vector sequence, N is a sequence number, generally from 0 to N-1, and N is a sequence length.
The difference between the extraction structure and the interpolation structure is that the extraction structure has an accumulator circuit, the accumulator circuit can bring a gain of D/I times, the processing idea of the gain of the time coefficient is the same, and the gain of the integer power of 2 is also split into two parts of integer power and decimal, wherein the gain of the integer power of 2 is controlled by truncation, and the bit width of the truncation is shown in a formula (8).
In FIG. 15, 2^ NP is a configurable rounding truncation operation, which truncates the low NP bits added by the accumulation calculation to offset the integer power of 2 gain brought by the accumulator. The fractional part of the gain of the accumulator is also processed in the filter coefficient quantization, so that the quantization of the decimation filter coefficients is as shown in equation (9).
In formula (9)Is used for offsetting the influence of decimal gain except the integral power of 2 after the extraction time coefficient is amplified by D times,to cancel the fractional gain effect of the accumulator circuit except for an integer power of 2.
The final output truncation of the filter by the low M bits cancels the effect of the filter quantization, as shown by the 2M truncation of FIG. 15.
So far, the gain of the whole fixed point processing is processed by truncation control and quantization of sub-filter coefficients, and the gain of the filter to the in-band signal can be theoretically guaranteed to be 0dB or other fixed gains.
The equations (5), (6), (7), (8) and (9) are all fixed point constants determined by the interpolation multiple I and the decimation multiple D and the floating point coefficient of the filter bank, that is, constants determined by different application scenarios, and these values can be calculated by the support control software or the host computer software on the single board and are configured on line to the Farrow filter fixed point logic implementation apparatus defined in fig. 5.
The time coefficients in both the interpolation and decimation cases, as defined by equations (3) and (4), are constants that vary in real time with respect to the output or input sampling clock sequence and need to be calculated and updated in real time in logic hardware.
Under the condition of interpolation, the sampling rate of input data is lower than that of output data, the sub-filter works in an input sampling clock domain, and the sub-filter needs to be converted into an output clock domain through buffering, multiplied by a time coefficient and summed to obtain output data. The clock domain conversion buffer writes in the input clock domain in the order of the input clock, but the sampling clock rate on the read side is high, and outputs the v of the sampling clock domainm(nl) In the time sampling dimension and time coefficient mulClosely related, all vary periodically as with mod (D × l, I).
Under the condition of interpolation with D less than or equal to I, the interpolation time coefficient is calculated in real time by using a logic circuit according to the method shown in the figure 8, and the data reading of the clock domain conversion buffer is controlled. Uiv-2 ui-I in fig. 8 is the required input for the calculation in fig. 15, and rd _ flag is the clock domain switching read address flag. When the logic hardware system is reset, uiv, rd _ flag and temporary variable t are all reset to initial values, when each output clock arrives, t is assigned to t + D, and the sizes of t and I are judged: if t is not less than I, t is t-I, and the read address identified by rd _ flag is added with 1; if t is less than I, then the read addresses identified by t and rd _ flag are not changed. Each output clock is calculated according to uiv-2 t-I to obtain the uiv value, and the uiv value is sent to fig. 15 for calculation.
Under the condition of extraction, the input data sampling rate is lower than the output sampling rate, the sub-filter works in an output sampling clock domain, the input data of the accumulator circuit needs to be accumulated in segments and an output result needs to be controlled, namely the accumulation input of the accumulator needs to have a control signal of zero clearing and resetting to segment the input data of the accumulator and convert the output result into the output sampling clock domain.
In the case of D > I decimation, the decimation time factor is calculated in real time using a logic circuit, and the clearing and holding operations are performed on the accumulation input and accumulation output of the accumulator circuit, in accordance with the method shown in fig. 12 described above. In fig. 12, udv-2 ud-D is a calculation input required in fig. 15, clr _ flag is a clear flag at the feedback accumulation input end of the accumulator circuit, and clr _ flag is an effective flag of accumulated output data at the same time, and at this time, the accumulated result is sampled and converted into an output clock domain. When the logic hardware system is reset, resetting udv, clr _ flag and a temporary variable t as initial values, assigning t to t + I and judging the magnitudes of t and D when each output clock arrives: if t is not less than D, t-D and clr _ flag is set to 1; if t is less than D, then neither the t nor clr _ flag flags are changed. Each output clock is calculated according to udv 2 × t-D to obtain udv value, and the udv value is sent to fig. 15 for calculation.
When I is equal to D, namely the input and output rate is not changed in a decimal time delay application scene, the physical meaning of the time constant is the normalization of the time difference between the delayed sampling point and the previous input sampling point to the sampling period, and the time coefficient is a constant at the moment, so that the real-time online calculation is not needed. The Farrow logic implementation structure under the decimal time delay scene is consistent with the interpolation mode, only the time coefficient is a quantized constant which does not need on-line calculation, the quantization process of the time constant is amplification calculation according to the integral power of 2, the amplified power is related to the time resolution of decimal time delay, meanwhile, the bit width of the truncation of NI is equal to the quantization bit width of the time coefficient, and the gain of multiplication of the time coefficient is ensured to be unchanged.
The data in the Farrow filter described above may implement conversion and processing control in two different sampling clock domains. In both the extraction and interpolation cases, the data is related to the conversion and control from the input sampling clock domain to the output sampling clock domain, and the processing is not simple clock domain conversion, so that a data buffering mechanism can be adopted, that is, when the Farrow filter operates in the interpolation mode, a buffering device can be arranged at the data output end of each sub-filter in fig. 15 for buffering the data output by the corresponding sub-filter; when the Farrow filter operates in the decimation mode, a buffer device may be provided at the output of each accumulator in fig. 15 for buffering the data output by the corresponding accumulator. Wherein, the read-write control of the data buffer is related to the rate conversion multiple.
The Farrow filter can reconfigure parameters on line, can realize fixed-point processing on floating-point numbers, and can be directly applied to the development and design of ASICs and FPGAs. The Farrow filter does not need to determine the interpolation multiple I and the extraction multiple D and the coefficient value of the sub-filter bank before implementation, and the parameters can be determined and configured by a user according to the practical application scene so that the device of the invention can work normally as required.
Designing and implementing the Farrow filter needs to determine the processing data bit width, the dimension and order of the sub-filter group, the representing bit width of the fixed-point coefficients of the I, D, M, NI, ND, NP and the sub-filters, and determine the processing bit width of the multiplier, the accumulator and the sub-filters according to the bit width.
The data processing bit width is currently generally 16 bits or 18 bits. The dimension and the order of the sub-filter group are required to be obtained by algorithm analysis and simulation evaluation under certain design requirements. Each sub-filter is a symmetric or anti-symmetric general FIR filter in logic design. I. The quantization bit widths for D and M are typically 16 bits or 18 bits. NI, ND and NP are truncated bit width parameters, and generally do not exceed 5 bits, because 5 bits can represent a truncation range of 0-31 bits.
The Farrow filter logic circuit module shown in fig. 15 can be obtained according to the determined parameters and the basic calculation and control unit. The selection of the interpolation or decimation modes of K1, K2, and K3 may be fixedly designed to support only a certain mode in practical applications.
The calculation of the interpolation time coefficient and the read control of the clock domain conversion buffer are designed according to the flow of fig. 8, and the extraction time coefficient and the accumulator control are designed according to the flow of fig. 12.
Based on the Farrow filter designed in the above manner, the system and the single board control software in the Farrow filter configure I, D and M according to the application scenario requirements, and calculate and configure the coefficients of NI, ND, NP and the sub-filters to be proper values according to the above correlation formula, so that the Farrow filter can operate and work normally. As can be seen from the above description, the above embodiments are directed to providing Farrow filter fixed-point calculation technology, in which implementations of decimation factor D, interpolation factor I, and filter bank ci (z) that can be reconfigured online are disclosed, for example, a truncating device is set at a specified position; meanwhile, in the design, two working modes of interpolation and extraction can be compatible; the above equations (5), (6), (7), (8) and (9) describe the localization method of Farrow filter related parameters including several truncation parameters in fig. 15, which theoretically ensure that the processing gain of the Farrow filter can be completely controlled by the user; the fixed-point real-time calculation method of the interpolation time coefficient given by the above formula (1) and fig. 8, and the read-out control method of the clock domain conversion control data buffer; the fixed-point real-time calculation method of the decimation time coefficient and the real-time control method of the accumulator circuit in the decimation mode given by the above formula (2) and fig. 12 can complete the Farrow filter design based on the implementation modes of the formulas. The Farrow filter is a commonly used decimal time delay and decimal sampling rate conversion filter, has wide application in the field of signal processing, and particularly has important application value in intermediate frequency digital signal processing in the field of communication.
The above embodiment implements a general Farrow filter implementation architecture through a series of fixed-point and controllable truncation, the whole processing gain is controllable, and the intermediate processing bit width is reduced, thereby reducing the hardware resource occupation, and meanwhile, the architecture is suitable for various multi-rate sampling signal processing.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a memory device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A logic circuit based Farrow filter comprising:
the gating switch is used for controlling the working mode of the Farrow filter according to the proportion relation between the configured input data sampling rate and the configured output data sampling rate;
the interpolation filtering device is used for performing interpolation filtering on input data under the control of the gating switch, and performing bit cutting operation on intermediate data according to a first set bit width in the interpolation filtering process to obtain first type fixed point data;
and the extraction filtering device is used for extracting and filtering the input data under the control of the gating switch, and performing bit cutting operation on the intermediate data according to a second set bit width in the process of extracting and filtering to obtain second type fixed point data.
2. The Farrow filter of claim 1, wherein the interpolation filtering means and the decimation filtering means share a set of sub-filters that support a coefficient on-line configuration function.
3. The Farrow filter of claim 1, wherein the interpolation filtering means comprises a set of sub-filters, a set of multipliers, and a set of adders; wherein,
each multiplier of the group of multipliers is connected with a multiplication truncator, and the multiplication truncator is used for truncating the output result of the multiplier according to a first set bit width to obtain first type fixed point data.
4. A Farrow filter according to claim 3,
the time coefficient received by each multiplier is uiv-2 ui-I, wherein ui-mui*I，μiMod (D × l, I)/I, I being a set difference multiple, D being a set decimation multiple; l is the data index of the output clock domain; mod () is the remainder computation.
5. A Farrow filter according to claim 4,
the coefficient cm' (n) of each sub-filter of the set of sub-filters is determined using the following formula: < mrow > < msub > < mi > < M > < mo > < mi > < mo > < mi > < mu > < mo > < mi > (</mo > < msub > < M > < mo > < M > < M > M < M > M < M > M < M < mfrac > < msup > < mn >2</mn > < mi > NI </mi > </msup > < mi > I </mi > </mfrac > </mo > </mrow > < mi > M </mi > </msup > </mo > < mo >, </mo > </mrow > where M is the quantization bit width of the set of sub-filter coefficients, and cm (n) is the normalized floating point coefficient of the mth sub-filter; n is the sequence number, N-0, 1.... cndot.n-1; n is the sequence length; m is an integer of 0 or more; round () is a round calculation; NI is the first set bit width,
and an addition truncator is arranged between the group of adders and the data output end and is used for truncating the lower M bits of the result operated by the group of adders.
6. The Farrow filter of claim 4, further comprising a first logical hardware system comprising:
the first restorer is used for resetting the first logic hardware system and resetting uiv, rd _ flag and a temporary variable t as initial values, wherein the rd _ flag is a clock domain conversion read address identifier;
the first variable processor is used for setting t to t + D when each output clock arrives, judging whether t is larger than I or not, if so, setting t to t-I, adding 1 to rd _ flag, and if not, keeping t and rd _ flag unchanged;
and the first time coefficient generator is used for setting the time coefficient uiv-2 t-I corresponding to each output clock.
7. The Farrow filter of claim 1, wherein the decimation filtering means comprises a set of sub-filters, a set of multipliers, a set of accumulators, and a set of adders; wherein,
each multiplier of the group of multipliers is connected with a multiplication truncator, and the multiplication truncator is used for truncating the output result of the multiplier according to a second set bit width and inputting truncated data into a corresponding accumulator;
and an accumulation truncator is arranged between each accumulator and the sub-filter and is used for truncating the result output by the accumulator to obtain second type fixed point data.
8. A Farrow filter according to claim 7,
the time coefficient received by each multiplier is udv-2 × ud-D, wherein ud- μd*D，μdMod (I × k, D)/D, I being a set difference multiple and D being a set decimation multiple; k is the data index of the output clock domain; mod () is the remainder computation.
9. A Farrow filter according to claim 8,
the coefficient cm' (n) of each sub-filter of the set of sub-filters is determined using the following formula: < mrow > < msub > < mi > < M > < mo > < mi > < mo > < mi > < mu > < mo > < mi > (</mo > < msub > < M > < mo > < M > < M > M < M > M < M > M < M [ mfrac > < msup > < mn >2</mn > < mi > </msup > < mi > </mo > </mrow > m </mi > </msup > < mo > (</mo > < mac > < msup > < mn >2</mn > < mi NP > </msup > < mo/mo < mi > < I > </mo < mo > </mo > D </mi > </m > m </mo > </m < m >, m is the quantization bit width of the set of sub-filter coefficients, cm (n) is the normalized floating point coefficient of the mth sub-filter; m is an integer of 0 or more; round () is a round calculation; ND is the second set bit width, NP is the bit-cutting bit width of the accumulation bit-cutter,
and an addition truncator is arranged between the group of adders and the data output end and is used for truncating the lower M bits of the result operated by the group of adders.
10. The Farrow filter of claim 8, further comprising a second logical hardware system, the second logical hardware system comprising:
the second restorer is used for restoring the second logic hardware system and restoring the udv, the clr _ flag and the temporary variable t into initial values, wherein the clr _ flag is a clear identifier of the feedback input end of the accumulator and an effective identifier of output data;
the second variable processor is used for setting t to t + I when each output clock arrives, judging whether t is larger than D or not, if so, setting t to t-D, setting clr _ flag to 1, and if not, keeping t and rd _ flag unchanged;
a second time coefficient generator for setting the time coefficient udv-2 × t-D corresponding to each output clock.
11. A method for implementing a Farrow filter based on a logic circuit is characterized by comprising the following steps:
determining the working mode of the Farrow filter according to the proportion relation between the configured input data sampling rate and the configured output data sampling rate;
when the working mode is interpolation filtering, in the process of interpolation filtering, bit cutting operation is carried out on intermediate data according to a first set bit width to obtain first type fixed point data;
and when the working mode is the extraction filtering, in the process of the extraction filtering, bit cutting operation is carried out on the intermediate data according to a second set bit width to obtain second type fixed point data.
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| CN102412806B (en) * | 2011-10-24 | 2017-08-25 | 南京中兴新软件有限责任公司 | The Farrow wave filters and its implementation of logic-based circuit |
| CN104391674B (en) * | 2014-10-22 | 2017-09-05 | 积成电子股份有限公司 | Sampled value linear interpolation arithmetic device and operation method based on FPGA |
| CN104485933A (en) * | 2014-11-19 | 2015-04-01 | 中国科学院微电子研究所 | Digital pulse width modulation device for switch power supply digital controller |
| US9966977B1 (en) * | 2016-10-25 | 2018-05-08 | Samsung Electronics Co., Ltd | Efficient polyphase architecture for interpolator and decimator |
| CN106849904A (en) * | 2017-01-17 | 2017-06-13 | 广州致远电子股份有限公司 | Digital filtering equipment |
| CN109361377B (en) * | 2018-10-17 | 2020-11-17 | 深圳锐越微技术有限公司 | Filtering method and device of filter, filter and storage medium |
| CN109905100B (en) * | 2019-02-19 | 2023-06-20 | 深圳市极致汇仪科技有限公司 | FPGA implementation method and system of FARROW type filter |
| CN112118063B (en) | 2019-06-21 | 2022-05-24 | 华为技术有限公司 | Clock synchronization device, optical transmitter, optical receiver and method |
| CN114584108A (en) * | 2020-11-30 | 2022-06-03 | 深圳市中兴微电子技术有限公司 | Filter unit and filter array |
| CN115223578B (en) * | 2022-09-21 | 2023-07-14 | 浙江地芯引力科技有限公司 | Audio signal synchronization method, device, equipment and storage medium |
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