CN102412208A - Chip size package and method for making the same - Google Patents

Abstract

The invention discloses a chip size package and a manufacturing method thereof, wherein the chip size package comprises: the package structure comprises a package colloid with a first surface and a second surface which are opposite, conductive bumps which are arranged in the package colloid and are exposed out of the first surface and the second surface of the package colloid, a chip which is embedded in the package colloid and is exposed out of the first surface of the package colloid, a dielectric layer which is arranged on the first surface of the package colloid, the conductive bumps and the chip, a circuit layer which is arranged on the dielectric layer, conductive blind holes which are arranged in the dielectric layer and are electrically connected with the circuit layer, electrode pads and the conductive bumps, and a solder mask layer which is arranged on the dielectric layer and the circuit layer. Therefore, the conductive bump can be directly externally connected with other electronic devices to form a stacked structure, and the manufacturing process is effectively simplified.

Description

Chip size package and method for making the same

technical field

The present invention relates to a package and its manufacturing method, in particular to a chip size package and its manufacturing method.

Background technique

With the evolution of semiconductor technology, semiconductor products have developed different packaging product types, and in order to pursue the lightness, thinness and shortness of semiconductor packages, a chip scale package (CSP) has been developed, which is characterized in that Chip-scale packages are only equal to or slightly larger than the chip size.

U.S. Patent Nos. 5,892,179, 6,103,552, 6,287,893, 6,350,668, and 6,433,427 disclose a traditional CSP structure, which directly forms build-up layers on the chip without using chip carriers such as substrates or lead frames, and utilizes redistribution layers. , RDL) technology to reconfigure the electrode pads on the chip to the desired position.

However, the disadvantage of the above-mentioned CSP structure is that the application of rewiring technology or the conductive traces laid on the chip is often limited by the size of the chip or the area of its active surface, especially when the integration level of the chip is improved and the chip size is shrinking day by day. Under the circumstances, the chip cannot even provide enough surface to place a larger number of solder balls to electrically connect with the outside world.

In view of this, U.S. Patent No. 6,271,469 discloses a manufacturing method of Wafer Level Chip Scale Package WLCSP (Wafer Level CSP), which is a build-up package formed on a chip, which can provide a relatively sufficient surface area to carry more input/output terminals or solder balls.

As shown in FIG. 1A, prepare an adhesive film 11, and paste a plurality of chips 12 on the adhesive film 11 with an active surface 121. The adhesive film 11 is, for example, a heat-sensitive adhesive film; as shown in FIG. 1B, perform encapsulation and molding process, utilize an encapsulant 13 such as epoxy resin to cover the non-active surface 122 and the side of the chip 12, and then heat and remove the adhesive film 11 to expose the active surface 121 of the chip; as shown in Figure 1C, then use Redistribution (RDL) technology, laying a dielectric layer 14 on the active surface 121 of the chip 12 and the surface of the encapsulant 13, and opening a plurality of openings through the dielectric layer 14 to expose the electrode pads 120 on the chip, and then A wiring layer 15 is formed on the dielectric layer 14, and the wiring layer 15 is electrically connected to the electrode pad 120, and then a solder repelling layer 16 is laid on the wiring layer 15 and a solder ball 17 is planted at a predetermined position of the wiring layer 15, and then cutting is performed. Operation.

Through the aforementioned process, since the surface of the encapsulant 13 covering the chip 12 has a larger surface area than the active surface 121 of the chip 12 , more solder balls 17 can be placed to effectively achieve electrical connection with the outside.

However, the disadvantage of the above-mentioned manufacturing process is that the chip 12 is fixed by pasting its active surface 121 on the adhesive film 11, often due to the expansion and contraction of the adhesive film 11 when it is heated in the manufacturing process, causing the chip 12 to stick to the adhesive film 11. The position of the chip 12 on the adhesive film 11 is shifted, and even the chip 12 is displaced due to the thermal softening of the adhesive film 11 during packaging and molding, so that the circuit layer 15 cannot be connected to the chip 12 during the subsequent rewiring process. electrode pad 120, thus causing electrical failure.

Please refer to FIG. 2. In another package molding process, since the adhesive film 11' is softened by heat, the encapsulant 13 is likely to overflow the glue 130 to the active surface 121 of the chip 12, or even pollute the electrode pad 120, resulting in subsequent rewiring. The circuit layer of the process has poor contact with the electrode pad of the chip, which leads to the problem of scrap.

Please refer to FIG. 3A, the above-mentioned encapsulation molding process only supports a plurality of chips 12 through the adhesive film 11, and the adhesive film 11 and the encapsulation compound 13 are prone to serious warping (warpage) 110 problems, especially when the thickness of the encapsulation compound 13 is very large. When it is thinner, the problem of warpage will be more serious, which will lead to the problem of uneven thickness when coating the dielectric layer 14 on the chip 12 during the subsequent rewiring process; thus, an additional hard carrier needs to be provided 18 (as shown in FIG. 3B ), so that the encapsulant 13 is fixed on the hard carrier 18 by an adhesive 19 for leveling, but when the rewiring process is completed and the carrier 18 is removed, it is easy to The adhesive 190 remains on the encapsulant 13 (as shown in FIG. 3C ). Other relevant prior art publications include US Patent Nos. 6,498,387, 6,586,822, 7,019,406 and 7,238,602.

Furthermore, as shown in FIG. 3D, if the packages are to be stacked, the encapsulant 13 needs to be penetrated first, and then the encapsulant 13 through hole process (TMV, Through Mold Via) is performed to form a plurality of through holes. , and then made by electroplating or chemical plating to fill the conductive material 100 in the through hole, thereby forming a plurality of conductive through holes 10, and then form solder balls 17' on the conductive through holes 10, for connecting devices such as another An electronic device 1 in a package. However, the manufacturing process through the encapsulant 13 is difficult, and the conductive material 100 needs to be filled when forming the conductive via 10 , so that the manufacturing time is increased and the cost is increased.

Therefore, how to provide a chip size package and its manufacturing method can avoid the above-mentioned defects of the prior art, thereby ensuring the quality of the electrical connection between the circuit layer and the electrode pad, improving the reliability of the product, and reducing the manufacturing cost. An important subject.

Contents of the invention

The purpose of the present invention is to ensure the quality of the electrical connection between the circuit layer and the electrode pad, improve the reliability of the product, and reduce the manufacturing cost.

In order to achieve the above object, the present invention provides a chip size package, comprising: an encapsulant having opposite first and second surfaces; a conductive bump disposed in the encapsulant and exposed on the first surface of the encapsulant On the surface and the second surface; the chip is embedded in the packaging colloid, the chip has an opposite active surface and a non-active surface, the active surface has a plurality of electrode pads, and the active surface is exposed to the packaging colloid The first surface; the dielectric layer is arranged on the first surface of the encapsulant, the conductive bump and the active surface of the chip; the circuit layer is arranged on the dielectric layer; the conductive blind hole is arranged on the dielectric layer, so that the circuit layer is electrically connected to the electrode pad and the conductive bump through the conductive blind hole; and a solder repelling layer is arranged on the dielectric layer and the circuit layer, and the solder repelling layer has a first and opening a hole so that part of the circuit layer is exposed in the first opening.

In the aforementioned package, the material forming the conductive bump is copper.

In the aforementioned package, the conductive bump has a metal layer, so that the metal layer is exposed on the second surface of the encapsulant, so that the conductive element is disposed on the exposed metal layer.

In the aforementioned package, the non-active surface of the chip is exposed on the second surface of the encapsulant.

In the aforementioned package, the conductive bump is flush with the second surface of the encapsulant, or the second surface of the encapsulant has a second opening corresponding to expose the conductive bump, so that the conductive element is disposed on the second surface of the encapsulant. exposed conductive bumps.

The aforementioned package may further include a conductive element disposed on the circuit layer in the first opening.

The aforementioned package may further include a build-up structure disposed on the dielectric layer and the circuit layer, and the solder repelling layer is disposed on the outermost layer of the build-up structure.

The present invention also provides a method for manufacturing a chip size package, comprising: providing a carrier board, and having adjacent conductive bumps and a die placement area on the carrier board; disposing a chip on the die placement region of the carrier board , the chip has an opposite active surface and a non-active surface, and the active surface has a plurality of electrode pads, and the active surface is connected to the carrier board; forming a packaging compound on the carrier board, conductive bumps and chips , to cover the chip, and the encapsulant has a first surface bonded to the carrier plate and an exposed second surface; the carrier plate is removed to expose the first surface of the encapsulant, the conductive bump and The active surface of the chip; form a dielectric layer on the first surface of the encapsulant, the conductive bump and the active surface of the chip; form a circuit layer on the dielectric layer, and form a conductive layer in the dielectric layer blind hole, so that the circuit layer is electrically connected to the electrode pad and the conductive bump through the conductive blind hole; a solder repelling layer is formed on the dielectric layer and the circuit layer, and the solder repelling layer has a first opening , so that part of the circuit layer is exposed in the first opening; and the conductive bump is exposed on the second surface of the encapsulant.

In the aforementioned manufacturing method, the material for forming the carrier plate is copper.

In the aforementioned manufacturing method, the manufacturing process of forming the carrier plate includes: providing a substrate; forming a resistance layer on the substrate, and the resistance layer has a plurality of openings exposing part of the surface of the substrate; removing the part in the opening substrate material, so that the conductive bump is formed under the resistance layer; and the resistance layer is removed, so that the remaining substrate material is used as the carrier board.

In the aforementioned manufacturing method, a metal layer is formed on the conductive bump, so that the metal layer is exposed on the second surface of the encapsulant.

According to the above-mentioned manufacturing process, the manufacturing process of forming the carrier plate includes: providing a substrate; forming a resistance layer on the substrate, and the resistance layer has a plurality of openings exposing part of the surface of the substrate; forming the metal layer in the openings on the substrate; and removing the resistance layer and part of the substrate material under it, so that the conductive bump is formed under the metal layer, and the remaining substrate material is used as the carrier plate.

The aforementioned manufacturing method also includes coating an adhesive layer on the active surface of the chip so that the chip is positioned on the die placement area of the carrier plate, and when the carrier plate is removed, the adhesive layer is also removed

In the aforementioned manufacturing method, the non-active surface of the chip is exposed to the encapsulant.

The aforementioned manufacturing method further includes removing the encapsulant on the conductive bump, making the conductive bump flush with the second surface of the encapsulant, or forming a corresponding exposed conductive bump on the second surface of the encapsulant. The second opening of the block.

The aforementioned manufacturing method may further include forming a build-up structure on the dielectric layer and the wiring layer, and the solder repelling layer is disposed on the outermost layer of the build-up structure.

As can be seen from the above, the chip size package and the manufacturing method of the present invention mainly place the chip on the carrier board with the conductive bumps first, then coat the chip and the conductive bumps with the encapsulant, and then remove the carrier board to carry out Rewiring process, so as to avoid the problem of heat softening of the film, overflow of packaging colloid, chip offset and pollution caused by the existing technology of directly bonding the chip on the film, or even poor contact between the circuit layer and the electrode pad in the subsequent rewiring process , leading to the problem of waste products.

Furthermore, the support force is increased by the conductive bumps, so the problem of warping caused by using the adhesive film as the supporting member in the existing manufacturing process can be avoided, and the problem of adhesive residue on the encapsulant can be avoided.

In addition, through the design of the conductive bumps, other electronic devices can be directly connected externally when stacking is desired, and there is no need to form conductive via holes through the encapsulant in the prior art, so the present invention effectively simplifies the manufacturing process, and because no filling is required Conductive materials, while effectively reducing manufacturing time and reducing costs.

Description of drawings

1A to 1C are schematic diagrams of the manufacturing method of the wafer-level chip size package disclosed in US Pat. No. 6,271,469;

FIG. 2 is a schematic diagram of the glue overflow problem of the wafer-level chip size package disclosed in US Pat. No. 6,271,469;

3A to 3D are schematic diagrams of problems such as warping of the packaging colloid, additional carriers, residual adhesive on the surface of the packaging colloid, and difficulty in stacking of the wafer-level chip size package disclosed in US Pat. No. 6,271,469;

4A to 4H are schematic diagrams of the chip-scale package and its manufacturing method of the present invention, wherein, FIG. 4A' is another embodiment of FIG. 4A, FIG. 4F' is a schematic diagram of a manufacturing method for forming a build-up structure, and FIG. 4G' and Fig. 4G" are different implementations of Fig. 4G respectively, and Fig. 4H' and Fig. 4H " are respectively different implementations of Fig. 4H;

5A to 5C are schematic diagrams of the manufacturing process of the conductive bump of the chip size package of the present invention, wherein, FIGS. 5A' to 5C' are another embodiment of FIGS. 5A to 5C .

Description of main component symbols:

1.29 Electronic devices

10 Conductive vias

100 Conductive material

11, 11' film

110 warping

12, 22 chips

120, 220 electrode pads

121, 22a Action surface

122, 22b non-active surface

13 Encapsulation colloid

130 overflow glue

14, 24 dielectric layer

15, 25 line layer

16, 26 Solder repellent layer

17, 17' solder ball

18 Vehicles

19 viscose

190 residual glue

20 load board

20a metal layer

200, 200' conductive bumps

21 Adhesive layer

23, 23' encapsulation colloid

23a First surface

23b, 23b' second surface

230 Second opening

240 blind hole

25’ build-up structure

250 Conductive blind vias

260 The first opening

27, 28 Conductive elements

30 Substrate

31 barrier layer

310 opening

A crystal setting area

h distance

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. Limiting conditions, so there is no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of the present invention, should still fall within the scope of the present invention. The disclosed technical content must be within the scope covered. At the same time, terms such as "upper", "top" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the present invention. Changes in their relative relationships or Adjustment, without substantive changes in technical content, should also be regarded as the scope of implementation of the present invention.

Please refer to FIG. 4A to FIG. 4H , which illustrate a manufacturing method of a chip-scale package provided by the present invention.

As shown in FIG. 4A , a carrier board 20 is provided, and there are a plurality of adjacent conductive bumps 200 and a die placement area A on the carrier board 20 , and the carrier board 20 is formed of a material that may be copper.

As shown in FIG. 4A', a metal layer 20a can also be formed on the top surface of the conductive bump 200, and the material for forming the metal layer 20a is one of the group consisting of nickel, palladium, and gold or a stacked structure.

As shown in FIG. 4B , a chip 22 is arranged on the crystal placement area A of the carrier plate 20, the chip 22 has an opposite active surface 22a and a non-active surface 22b, and the active surface 22a has a plurality of electrode pads 220, And connect to the bearing plate 20 with the action surface 22a. In this embodiment, the adhesive layer 21 is coated on the active surface 22 a to achieve the purpose of bonding and fixing the chip 22 on the carrier board 20 , but the method is not limited thereto.

As shown in FIG. 4C , an encapsulant 23 is formed on the carrier plate 20 , the conductive bump 200 and the chip 22 to cover the chip 22 , and the encapsulant 23 has a first bonded to the carrier plate 20 . The surface 23a and the exposed second surface 23b. In this embodiment, the encapsulant 23 covers the non-active surface 22b of the chip 22, and the distance h between the conductive bump 200 and the second surface 20b of the encapsulant 23 is 10 to 50 μm, but not limited to this range.

As shown in FIG. 4D , the carrier board 20 is removed by etching to expose the first surface 23 a of the encapsulant 23 and the conductive bump 200 , and then the adhesive layer 21 is removed with a chemical solution to expose the chip 22 . Active surface 22a.

In the present invention, when the carrier board 20 is removed, no metal or glue remains on the first surface 23 a of the encapsulant 23 .

As shown in FIG. 4E , to perform a redistribution (RDL) process, firstly at least one dielectric layer 24 is formed on the first surface 23 a of the encapsulant 23 , the conductive bump 200 and the active surface 22 a of the chip 22 . Then, a plurality of blind holes 240 are formed in the dielectric layer 24 to expose the conductive bumps 200 and the electrode pads 220 . A patterning step is then performed to form a conductive blind hole 250 in the blind hole 240, and a wiring layer 25 is formed on the conductive blind hole 250 and on the dielectric layer 24, so that the wiring layer 25 passes through the conductive blind hole 250 The electrode pad 220 and the conductive bump 200 are electrically connected.

As shown in FIG. 4F, a solder repelling layer 26 is formed on the dielectric layer 24 and the circuit layer 25, and the solder repelling layer 26 has a plurality of first openings 260, so that part of the circuit layer 25 is exposed on the first circuit layer. An opening 260 is used to form conductive elements 27 such as solder balls on the circuit layer 25 in the first opening 260 in subsequent processes to connect other electronic devices, such as circuit boards and semiconductor chips.

As shown in FIG. 4F', the build-up structure 25' can also be formed on the dielectric layer 24 and the circuit layer 25 first, and then the solder repellent layer 26 is arranged on the outermost layer of the build-up structure 25', so as to Part of the outermost circuit of the build-up structure 25 ′ is exposed to the first opening 260 , so as to form a conductive element 27 on the circuit in the first opening 260 . Furthermore, the build-up structure 25' has at least one dielectric layer, a circuit on the dielectric layer, and a conductive blind hole provided in the dielectric layer and electrically connecting the circuit layer 25 and the circuit.

As shown in FIG. 4G , a second opening 230 is formed on the second surface 23b of the encapsulant 23 by laser drilling, so that the conductive bump 200 is exposed on the second surface 23b of the encapsulant 23 . In other embodiments, another build-up structure may also be formed on the second surface 23 b of the encapsulant 23 (not shown).

As shown in FIG. 4H , conductive elements 28 such as solder balls are formed on the conductive bumps 200 in the second openings 230 for external connection to other electronic devices 29 , such as a circuit board or another package.

Through the design of the conductive bump 200 in the present invention, when stacking is desired, other electronic devices 29 can be directly externally connected to other electronic devices 29 through solder balls, and there is no need to penetrate the encapsulant to form conductive vias as in the prior art, so the present invention can simplify The manufacturing process does not need to be filled with conductive materials, which effectively reduces the manufacturing time and costs.

In one embodiment, as shown in FIG. 4G' and FIG. 4H', if the structure shown in FIG. 4A' is followed by the above manufacturing process, the metal layer 20a will be exposed on the second surface 23b of the encapsulant 23. , so as to form the conductive element 28 on the metal layer 20 a in the second opening 230 , so as to externally connect the electronic device 29 .

In another embodiment, as shown in FIG. 4G'' and FIG. 4H'', the conductive bump 200' and the encapsulant 23 on the non-active surface 22b of the chip 22 are removed, so that the remaining encapsulant 23' forms The new second surface 23b', so that the conductive bump 200' and the non-active surface 22b of the chip 22 are exposed to the new second surface 23b' of the encapsulant 23', so that the non-active surface 22b of the chip 22 can be For heat dissipation, the conductive bump 200' is flush with the new second surface 23b' of the encapsulant 23'. Therefore, how the conductive bump or the non-active surface of the chip is exposed to the encapsulant can be adjusted according to requirements, and there is no special limitation.

In the present invention, the chip 22 is firstly placed on the carrier board 20, and then the chip 22 is covered with the encapsulant 23, and then the carrier board 20 is removed, so that the present invention avoids the need for the existing adhesive film. Problems such as packaging colloid overflow and chip contamination occur in some technologies.

Furthermore, the present invention arranges the chip 22 on the carrier plate 20 with the active surface 22a, which does not cause stretching problems due to heat of the adhesive film in the prior art, so the chip 22 does not shift, and During packaging and molding, the carrier board 20 will not be softened by heat, so the chip 22 will not be displaced. Therefore, during the rewiring process, the circuit layer 25 and the electrode pad 220 of the chip 22 will not have poor contact, effectively avoiding the problem of waste products.

In addition, the present invention forms the conductive bump 200 on the carrier board 20 to increase the supporting force, so that the overall structure will not warp, effectively avoiding the warpage that occurs when the adhesive film is used as the supporting part in the existing manufacturing process. The problem of curvature, so the chip 22 will not be offset. Therefore, during the rewiring process, the circuit layer 25 and the electrode pad 220 will not have poor contact, effectively avoiding the problem of waste products.

The present invention also provides a chip size package, comprising: an encapsulant 23 having opposite first surfaces 23 a and second surfaces 23 b, first and second encapsulants disposed in the encapsulant 23 and exposed to the encapsulant 23 . The conductive bump 200 on the surface 23a, 23b, the chip 22 disposed in the encapsulant 23 and exposed on the first surface 23a of the encapsulant 23a, the first surface 23a of the encapsulant 23, the conductive bump 200 And the dielectric layer 24 on the chip 22, the circuit layer 25 disposed on the dielectric layer 24, the conductive blind hole 250 disposed in the dielectric layer 24, and the dielectric layer 24 and the circuit layer Solder repellent layer 26 on 25.

The conductive bump 200 is made of copper, and the second surface 23b of the encapsulant 23 has a second opening 230 so that the conductive bump 200 is exposed on the second surface 23b of the encapsulant 23 . Alternatively, the conductive bump 200' is flush with the second surface 23b' of the encapsulant 23', so that the conductive bump 200' is exposed on the second surface 23b' of the encapsulant 23'.

The chip 22 has an opposite active surface 22 a and a non-active surface 22 b, the active surface 22 a has electrode pads 220 , and the active surface 22 a is combined with the dielectric layer 24 . In addition, the non-active surface 22b of the chip 22 can be exposed on the second surface 23b' of the encapsulant 23' according to requirements.

The circuit layer 25 is electrically connected to the electrode pad 220 and the conductive bump 200 through the conductive blind hole 250 .

The solder repellent layer 26 has a first opening 260, so that part of the circuit layer 25 is exposed in the first opening 260, so that conductive elements 27 such as solder balls are provided in the first opening 260. on the line layer 25.

In one embodiment, the conductive bump 200 is provided with a metal layer 20 a such that the metal layer 20 a is exposed on the second surface 23 b of the encapsulant 23 .

The package further includes a conductive element 28 disposed on the exposed conductive bumps 200, 200' or on the exposed metal layer 20a.

In addition, the package further includes a build-up structure 25' disposed on the dielectric layer 24 and the circuit layer 25, and the solder resist layer 26 is disposed on the outermost layer of the build-up structure 25'.

Referring to FIGS. 5A to 5C , a manufacturing process for forming the carrier plate 20 shown in FIG. 4A is provided.

As shown in FIG. 5A , a substrate 30 is provided first, and then a resist layer 31 is formed on the substrate 30 , and the resist layer 31 has a plurality of openings 310 to expose part of the surface of the substrate 30 .

As shown in FIG. 5B , part of the material of the substrate 30 in the opening 310 is removed by etching, so that the conductive bump 200 is formed under the resistance layer 31 .

As shown in FIG. 5C , the resist layer 31 is removed, and the remaining material of the substrate 30 is used as the carrier plate 20 .

Referring to FIGS. 5A' to 5C', a manufacturing process for forming the carrier plate 20 as shown in FIG. 4A' is provided.

As shown in FIG. 5A', a substrate 30 is provided, and a resist layer 31 is formed on the substrate 30, and the resist layer 31 has a plurality of openings 310 to expose part of the surface of the substrate 30.

As shown in FIG. 5B', the metal layer 20a is formed on the substrate 30 in the opening 310. Referring to FIG.

As shown in FIG. 5C', the resist layer 31 and part of the substrate 30 material thereunder are removed, so that the conductive bump 200 is formed under the metal layer 20a, and the remaining substrate 30 material is used as the carrier plate 20.

To sum up, the chip size package and its manufacturing method of the present invention are based on the design of the conductive bumps. When stacking is desired, other electronic devices can be directly connected externally through the solder balls, which effectively simplifies the manufacturing process, reduces the manufacturing time and cut costs. Furthermore, the present invention uses a carrier board to replace the existing adhesive film, effectively avoiding problems such as overflow of packaging colloid and contamination of chips.

In addition, the chip is placed on the carrier board, and the supporting force of the overall structure is increased through the conductive bumps to prevent the structure from warping, so the chip will not be offset. Therefore, during the rewiring process, the circuit layer and the electrode pad of the chip There will be no poor contact, effectively avoiding the problem of waste products. In addition, when the carrier board is removed, no metal material or glue remains on the encapsulant.

The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope of the claims.

Claims (20)

1. A chip size package, characterized in that, comprising: The encapsulant has opposite first and second surfaces; a conductive bump disposed in the encapsulant and exposed on the first surface and the second surface of the encapsulant; A chip embedded in the encapsulant, the chip has an opposite active surface and a non-active surface, the active surface has a plurality of electrode pads, and the active surface is exposed on the first surface of the encapsulant; a dielectric layer disposed on the first surface of the encapsulant, the conductive bump and the active surface of the chip; a circuit layer disposed on the dielectric layer; a conductive blind hole is provided in the dielectric layer, so that the circuit layer is electrically connected to the electrode pad and the conductive bump through the conductive blind hole; and The solder repelling layer is arranged on the dielectric layer and the circuit layer, and the solder repelling layer has a first opening, so that part of the circuit layer is exposed in the first opening. 2 . The chip scale package according to claim 1 , wherein the material forming the conductive bump is copper. 3 . 3 . The chip scale package according to claim 1 , wherein the conductive bump has a metal layer, so that the metal layer is exposed on the second surface of the encapsulant. 4 . 4. The chip scale package according to claim 3, further comprising a conductive element disposed on the exposed metal layer. 5. The chip scale package according to claim 1, wherein the non-active surface of the chip is exposed on the second surface of the encapsulant. 6 . The chip scale package according to claim 1 , wherein the conductive bump is flush with the second surface of the encapsulant. 7 . The chip scale package according to claim 1 , wherein the second surface of the encapsulant has a second opening corresponding to exposing the conductive bump. 8 . 8. The chip scale package according to claim 6 or 7, further comprising a conductive element disposed on the exposed conductive bump. 9. The chip scale package according to claim 1, further comprising a conductive element disposed on the circuit layer in the first opening. 10. The chip-scale package according to claim 1, further comprising a build-up structure disposed on the dielectric layer and the circuit layer, and the solder rejection layer is disposed on the outermost layer of the build-up structure layer. 11. A method for manufacturing a chip size package, comprising: providing a carrier board with adjacent conductive bumps and die placement regions on the carrier board; Setting a chip on the crystal placement area of the carrier plate, the chip has an opposite active surface and a non-active surface, and the active surface has a plurality of electrode pads, and is placed on the carrier plate with the active surface; Forming an encapsulant on the carrier board, the conductive bump and the chip to cover the chip, and the encapsulant has a first surface bonded to the carrier board and an exposed second surface; removing the carrier board to expose the first surface of the encapsulant, the conductive bump and the active surface of the chip; forming a dielectric layer on the first surface of the encapsulant, the conductive bump and the active surface of the chip; forming a circuit layer on the dielectric layer, and forming a conductive blind hole in the dielectric layer, so that the circuit layer is electrically connected to the electrode pad and the conductive bump through the conductive blind hole; forming a solder repellent layer on the dielectric layer and the circuit layer, and the solder repellent layer has a first opening, so that part of the circuit layer is exposed through the first opening; and The conductive bump is exposed on the second surface of the encapsulant. 12 . The method for manufacturing a chip scale package according to claim 11 , wherein the carrier plate is made of copper. 13 . 13. The method for manufacturing a chip-scale package according to claim 11, wherein the process of forming the carrier plate comprises: providing a substrate; forming a resistance layer on the substrate, and the resistance layer has a plurality of openings exposing part of the surface of the substrate; removing part of the substrate material in the opening to form the conductive bump under the resistance layer; and The resist layer is removed, and the remaining substrate material is used as the carrier board. 14 . The method for manufacturing a chip scale package according to claim 11 , wherein a metal layer is formed on the conductive bump so that the metal layer is exposed on the second surface of the encapsulant. 15 . 15. The method for manufacturing a chip-scale package according to claim 14, wherein the process of forming the carrier plate comprises: providing a substrate; forming a resistance layer on the substrate, and the resistance layer has a plurality of openings exposing part of the surface of the substrate; forming the metal layer on the substrate in the opening; and The resistance layer and part of the substrate material under it are removed, so that the conductive bump is formed under the metal layer, and the remaining substrate material is used as the carrying plate. 16. The method for manufacturing a chip scale package according to claim 11, wherein the non-active surface of the chip is exposed to the encapsulant. 17. The method for manufacturing a chip-scale package according to claim 11, further comprising coating an adhesive layer on the active surface of the chip, so that the chip is positioned on the die placement area of the carrier plate, And after removing the bearing plate, the adhesive layer is also removed. 18 . The method for manufacturing a chip scale package according to claim 11 , further comprising removing the encapsulant on the conductive bump so that the conductive bump is flush with the second surface of the encapsulant. 19 . The method for manufacturing a chip scale package according to claim 11 , further comprising forming a second opening corresponding to expose the conductive bump on the second surface of the encapsulant. 20. The method for manufacturing a chip-scale package according to claim 11, further comprising forming a build-up structure on the dielectric layer and the circuit layer, and the solder rejection layer is arranged on the build-up structure on the outermost layer.

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