CN102356474A - High quality tco-silicon interface contact structure for high efficiency thin film silicon solar cells - Google Patents

Abstract

A method and apparatus for forming solar cells is provided. In one embodiment, a photovoltaic device includes a first TCO layer disposed on a substrate, a second TCO layer disposed on the first TCO layer, and a p-type silicon containing layer formed on the second TCO layer. In another embodiment, a method of forming a photovoltaic device includes forming a first TCO layer on a substrate, forming a second TCO layer on the first TCO layer, and forming a first p-i-n junction on the second TCO layer.

Description

High-quality transparent conductive oxide-silicon interfacial contact structures for high-efficiency thin-film silicon solar cells

technical field

Embodiments of the invention generally relate to solar cells and methods of forming the same. More particularly, embodiments of the present invention relate to interfacial layers formed in thin film and crystalline silicon solar cells.

Background technique

Crystalline silicon solar cells and thin film solar cells are two types of solar cells. Crystalline silicon solar cells typically use a single crystalline silicon substrate (ie, a single crystalline pure silicon substrate) or multiple crystalline silicon substrates (ie, polycrystalline silicon or polycrystalline silicon substrates). Additional layers are deposited onto the silicon substrate to improve light-harvesting properties, form circuits, and protect the device. Thin film solar cells use thin layers of material deposited on a suitable substrate to form one or more p-n junctions. Suitable substrates include glass, metal and polymer substrates.

In order to expand the economic utilization of solar cells, the efficiency must be improved. Solar cell efficiency is related to the proportion of incident radiation that is converted into useful electrical energy. To be useful in more applications, solar cell efficiency must be improved beyond about 15% of the current best performance. With energy costs rising, there is a need for improved thin film solar cells, and methods and apparatus for forming the improved thin film solar cells in a factory environment.

Contents of the invention

Embodiments of the invention provide methods of forming solar cells. Some embodiments provide a method of forming an interfacial layer between a transparent conductive oxide (TCO) layer and a solar cell junction. In one embodiment, a photovoltaic device comprises: a first TCO layer disposed on a substrate; a second TCO layer disposed on the first TCO layer; and p- type silicon-containing layer, the p-type silicon-containing layer is formed on the second TCO layer.

In another embodiment, a photovoltaic device comprises: a TCO layer disposed on a substrate; an interfacial layer disposed on the TCO layer, wherein the interfacial layer is a carbon-containing p-type a silicon-containing layer; and a p-type silicon-containing layer disposed on the interface layer.

In yet another embodiment, a method of forming a photovoltaic device comprises the steps of: forming a first TCO layer on a substrate; forming a second TCO layer on the first TCO layer; and forming a first p-i-n junction on the substrate on the second TCO layer.

Description of drawings

The features of the invention, briefly summarized above, may be understood in detail by reference to the embodiments of the invention, which are illustrated in the accompanying drawings.

FIG. 1 is a cross-sectional view of a tandem junction thin film solar cell according to an embodiment of the present invention.

2 is a cross-sectional view of a tandem junction thin film solar cell according to an embodiment of the present invention, wherein the tandem junction thin film solar cell has an interface layer disposed between the TCO layer and the cell junction.

3-10 illustrate cross-sectional views of a tandem junction thin film solar cell according to an embodiment of the present invention, wherein the tandem junction thin film solar cell has an interfacial layer disposed between the TCO layer and the cell junction.

Fig. 11 shows a cross-sectional view of an apparatus according to an embodiment of the present invention.

Figure 12 is a plan view of an apparatus according to another embodiment of the present invention.

Figure 13 is a plan view of a portion of a production line incorporating the apparatus of Figures 11 and 12 in accordance with an embodiment of the invention.

To facilitate understanding, identical reference numerals have been used, where possible, to denote identical elements that are common to the figures. It is to be understood that elements and features of one embodiment may be beneficially incorporated in other embodiments without specific recitation.

It is to be understood, however, that the appended drawings depict only exemplary embodiments of the invention and are therefore not limiting of its scope, for the invention admits to other equally effective embodiments.

Detailed ways

Thin film solar cells are typically formed from many types of films or layers put together in many different ways. Most films used in such devices contain semiconductor elements including silicon, germanium, carbon, boron, phosphorus, nitrogen, oxygen, hydrogen, and the like. Properties of different films include crystallinity, doping type, doping concentration, film refractive index, film extinction coefficient, film transmittance, film absorbance, and conductivity. Most of these films can be formed using chemical vapor deposition processes, which can include some degree of ionization or plasma formation.

During a photovoltaic process, charge generation is generally provided by a bulk semiconductor layer, such as a silicon-containing layer. The bulk layer is sometimes called the intrinsic layer to distinguish it from the various doped layers present in the solar cell. The intrinsic layer may have any desired degree of crystallinity which will affect the light absorption properties of the intrinsic layer. For example, an amorphous intrinsic layer such as amorphous silicon absorbs substantially different wavelengths of light than an intrinsic layer having a different degree of crystallinity such as microcrystalline or nanocrystalline silicon. For this reason, it is advantageous to use both types of layers to produce the broadest absorbable characteristics.

Silicon and other semiconductors can be formed as solids with various degrees of crystallinity. A solid with substantially no crystallization is amorphous, and silicon with negligible crystallization is called amorphous silicon. Fully crystalline silicon is known as crystalline, polycrystalline, or monocrystalline silicon. Polycrystalline silicon is crystalline silicon comprising many crystalline grains separated by grain boundaries. Monocrystalline silicon is a single crystal of silicon. Solids that are partially crystalline (i.e., between about 5% and about 95% crystalline) are known as nanocrystals or microcrystals, which roughly refer to crystals suspended in an amorphous phase. particle size. Solids with larger crystalline particles are called microcrystalline, while solids with smaller crystalline particles are called nanocrystalline. It should be understood that the term "crystalline silicon" may refer to any form of silicon having a crystalline phase, including microcrystalline and nanocrystalline silicon.

FIG. 1 is a schematic diagram of an embodiment of a multi-junction solar cell 100 oriented toward light or solar radiation 101 . The solar cell 100 includes a substrate 102 . A first transparent conductive oxide (TCO) layer 104 is formed over the substrate 102 , and a first p-i-n junction 122 is formed over the first TCO layer 104 . A second p-i-n junction 124 is formed over the first p-i-n junction 122 , a second TCO layer 118 is formed over the second p-i-n junction 124 , and a metal back layer 120 is formed over the second TCO layer 118 . The substrate 102 may be a glass substrate, a polymer substrate, a metal substrate, or other suitable substrates on which multilayer films are formed.

The first TCO layer 104 and the second TCO layer 118 may each comprise tin oxide, zinc oxide, indium tin oxide, cadmium stannate, combinations thereof, or other suitable materials. It is understood that TCO materials may additionally include dopants and compositions as well. For example, zinc oxide may further include dopants such as, for example, tin, aluminum, gallium, boron, and other suitable dopants. In one embodiment, the zinc oxide contains 5 atomic % or less doping, and more preferably contains 2.5 atomic % or less aluminum. In a particular example, the substrate 102 may be provided by a glass manufacturer with the first TCO layer 104 already deposited on the substrate 102 .

To improve light absorption by increasing light trapping, the substrate 102 and/or one or more thin films formed on the substrate may optionally be textured by wet, plasma, ionic, and/or other mechanical treatments. For example, in the embodiment of FIG. 1 , the first TCO layer 104 is textured sufficiently that the surface topography is substantially transferred to thin films subsequently deposited on the first TCO layer.

之间的p-型非晶硅层。在特定实施例中，本征型含硅层108是厚度介于约与约

之间的本征型非晶硅层。在特定实施例中，n-型含硅层110是可以形成为厚度介于约

与约

之间的n-型微晶硅层。The first pin junction 122 may include a p-type silicon-containing layer 106, an intrinsic type silicon-containing layer 108 formed over the p-type silicon-containing layer 106, and an n-type silicon-containing layer formed over the intrinsic type silicon-containing layer 108. type silicon-containing layer 110 . In a particular embodiment, the p-type silicon-containing layer 106 is between about make an appointment

between p-type amorphous silicon layers. In a particular embodiment, the intrinsic silicon-containing layer 108 is between about make an appointment

Intrinsic type amorphous silicon layer between. In a specific embodiment, the n-type silicon-containing layer 110 may be formed to have a thickness between about

make an appointment

between n-type microcrystalline silicon layers.

与约之间的p-型微晶硅层。在特定实施例中，本征型含硅层114是厚度介于约

与约之间的本征型微晶硅层。在特定实施例中，n-型含硅层116是厚度介于约与约

之间的非晶硅层。The second pin junction 124 may include a p-type silicon-containing layer 112, an intrinsic type silicon-containing layer 114 formed over the p-type silicon-containing layer 112, and an n-type silicon-containing layer formed over the intrinsic type silicon-containing layer 114. type silicon-containing layer 116 . In a particular embodiment, the p-type silicon-containing layer 112 is between about

make an appointment between p-type microcrystalline silicon layers. In a particular embodiment, the intrinsic silicon-containing layer 114 is between about

make an appointment Intrinsic microcrystalline silicon layer between. In a particular embodiment, n-type silicon-containing layer 116 is between about make an appointment

between the amorphous silicon layers.

The metal back layer 120 may include, but is not limited to, materials selected from the group consisting of Al, Ag, Ti, Cr, Au, Cu, Pt, alloys thereof, and combinations thereof. Other processes may be performed to form solar cell 100, such as a laser scribing process. Other films, materials, substrates, and/or encapsulation may be provided over the metal back layer 120 to complete the solar cell device. The formed solar cells can be connected to each other to form a module, which in turn can be connected to form an array.

The solar radiation 101 is mainly absorbed by the intrinsic layers 108, 114 of the p-i-n junctions 122, 124 and converted into electron-hole pairs. An electric field established between the p-type layer 106, 112 and the n-type layer 110, 116 and extending across the intrinsic layer 108, 114 causes electrons to flow towards the n-type layer 110, 116 and holes towards the p-type The layers 106, 112 flow, thereby generating an electrical current. The first p-i-n junction 122 may comprise an intrinsic type amorphous silicon layer 108, and the second p-i-n junction 124 may comprise an intrinsic type microcrystalline silicon layer 114, to utilize the solar radiation 101 which can be absorbed by amorphous silicon and microcrystalline silicon at different wavelengths nature. Thus, the resulting solar cell 100 is more efficient because the solar cell captures a greater portion of the solar radiation spectrum. The intrinsic layers 108, 114 of amorphous silicon and the intrinsic layer of microcrystalline silicon are stacked in such a way that the solar radiation 101 hits the intrinsic type amorphous silicon layer 108 first, and then hits the intrinsic type microcrystalline silicon layer 114, which This is because amorphous silicon has a larger energy band gap than microcrystalline silicon. Solar radiation not absorbed by the first p-i-n junction 122 is transmitted to the second p-i-n junction 124 .

或更大。在一示范性实施例中，本征型非晶硅层108是以体积流速比为约12.5∶1的氢对硅烷来沉积。In an embodiment where the intrinsic silicon-containing layer 108 is an intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer 108 may be deposited by providing a gas mixture of hydrogen and silane gas, wherein the volumetric flow rate ratio of hydrogen to silane is about 20:1 or less. Silane gas may be provided at a flow rate between about 0.5 sccm/L and about 7 sccm/L. Hydrogen may be provided at a flow rate between about 5 sccm/L and about 60 sccm/L. An RF power of between 15 mW/cm ² and about 250 mW/cm ² may be provided to the showerhead. The pressure of the chamber may be maintained between about 0.1 Torr and 20 Torr, such as between about 0.5 Torr and about 5 Torr. The deposition rate of the intrinsic type amorphous silicon layer 108 will be about

or larger. In an exemplary embodiment, the intrinsic type amorphous silicon layer 108 is deposited with a volumetric flow rate ratio of hydrogen to silane of about 12.5:1.

或更大、诸如约

的速率大致上沉积结晶率为介于约20％与约80％之间、诸如介于约55％与约75％之间的本征型微晶硅层。在一些实施例中，在沉积期间，将所施加的RF功率从第一功率密度增加到第二功率密度是有利的。In an embodiment where the intrinsic silicon-containing layer 114 is an intrinsic microcrystalline silicon layer, the intrinsic microcrystalline silicon layer 114 may be deposited by providing a gas mixture of hydrogen and silane gas, wherein the volumetric flow rate ratio of hydrogen to silane is between Between about 20:1 and about 200:1. Silane gas may be provided at a flow rate between about 0.5 sccm/L and about 5 sccm/L. Hydrogen may be provided at a flow rate between about 40 sccm/L and about 400 sccm/L. in a particular embodiment. In certain embodiments, the silane flow rate may be increased from a first flow rate to a second flow rate during deposition. In certain embodiments, the hydrogen flow rate may be decreased from a first flow rate to a second flow rate during deposition. At a chamber pressure between about 1 Torr and about 100 Torr, such as between about 3 Torr and about 20 Torr, or between about 4 Torr and about 12 Torr, apply about 300 mW/cm2 or greater, such as 600 mW/cm cm ² or greater RF power, will

or larger, such as approx.

The rate generally deposits an intrinsic type microcrystalline silicon layer with a crystallinity of between about 20% and about 80%, such as between about 55% and about 75%. In some embodiments, during deposition, it may be advantageous to increase the applied RF power from a first power density to a second power density.

或更大、诸如

的速率来沉积本征型微晶硅。In another embodiment, the intrinsic microcrystalline silicon layer 114 may be deposited using multiple steps, wherein portions of the layer deposited during each step have different hydrogen dilution ratios, wherein the different hydrogen dilution ratios provide the desired Different crystallization rates of deposited films. For example, in one embodiment, the volumetric flow rate ratio of hydrogen to silane can be reduced from 100:1 to 95:1, to 90:1, and to 85:1 in four steps. In one embodiment, silane gas may be provided at a flow rate between about 0.1 sccm/L and about 5 sccm/L, such as about 0.97 sccm/L. Hydrogen may be provided at a flow rate between about 10 sccm/L and about 200 sccm/L, such as between about 80 sccm/L and about 105 sccm/L. In an exemplary embodiment where the deposition process has multiple steps (eg, four steps), the hydrogen flow may start at about 97 sccm/L during the first step and may be gradually reduced to about 92 sccm in subsequent process steps, respectively /L, 88sccm/L, and 83sccm/L. Apply about 300 mW/cm or ^more at a chamber pressure of between about 1 Torr and about 100 Torr, such as between about 3 Torr and about 20 Torr, such as between about 4 Torr and about 12 Torr, such as about 9 Torr A large RF power, such as about 490mW/cm ² , will result in a

or larger, such as

The rate to deposit intrinsic type microcrystalline silicon.

Charge collection is generally provided by doped semiconductor layers such as silicon layers doped with p-type or n-type dopants. The p-type dopant is usually a group III element such as boron or aluminum. The n-type dopant is usually a group V element such as phosphorus, arsenic, or antimony. In most embodiments, boron is used as p-type dopant and phosphorus is used as n-type dopant. These dopants can be added to the aforementioned p-type and n-type layers 106, 110, 112, 116 by including boron- or phosphorus-containing compounds in the reaction mixture. Suitable boron and phosphorus compounds generally include substituted and unsubstituted subborane and phosphine oligomers. Some _{suitable boron compounds include trimethylboron (B(CH3)3 or TMB), diborane (B2H6), boron trifluoride (BF3 ) , and triethylboron} (B( _C2 H ₅ ) ₃ or TEB). Phosphine is the most common phosphorus compound. Doping is typically provided with a carrier gas such as hydrogen, helium, argon, or other suitable gas. If hydrogen is used as a carrier gas, it will increase the total hydrogen in the reaction mixture. Therefore, the aforementioned hydrogen ratio will include the hydrogen portion contributed by the carrier gas used to transport the dopant.

Doping is generally provided as a diluent in the inert or carrier gas. For example, doping may be provided at a molar or volume concentration of about 0.5% in the carrier gas. If a dopant with a volume concentration of 0.5% is provided in a carrier gas with a flow rate of 1.0 sccm/L, the final dopant flow rate will be 0.005 sccm/L. Depending on the desired level of doping, the doping may be provided to the reaction chamber at a flow rate between about 0.0002 sccm/L and about 0.1 sccm/L. Generally, the doping concentration is maintained between about 10 ¹⁸ atoms/cm ³ and about 10 ²⁰ atoms/cm ³ .

或更大、诸如约

或更大的速率沉积结晶率为介于约20％与约80％之间、诸如介于约50％与约70％之间的p-型微晶硅层。In an embodiment where the p-type silicon-containing layer 112 is a p-type microcrystalline silicon layer, the p-type microcrystalline silicon layer 112 can be deposited by providing a gas mixture of hydrogen and silane gas, wherein the volume flow rate of hydrogen to silane The ratio is about 200:1 or greater, such as 1000:1 or less, such as between about 250:1 and about 800:1, and in a further example about 601:1 or about 401:1. Silane gas may be provided at a flow rate between about 0.1 sccm/L and about 0.8 sccm/L, such as between about 0.2 sccm/L and about 0.38 sccm/L. Hydrogen may be provided at a flow rate between about 60 sccm/L and about 500 sccm/L, such as about 143 sccm/L. TMB may be provided at a flow rate between about 0.0002 sccm/L and about 0.0016 sccm/L, such as about 0.00115 sccm/L. If TMB is provided in a carrier gas at a molar or volume concentration of 0.5%, the dopant/carrier gas mixture may be provided at a flow rate between about 0.04 sccm/L and about 0.32 sccm/L, such as about 0.23 sccm/L . Between about 50 mW is applied at a chamber pressure of between about 1 Torr and about 100 Torr, such as between about 3 Torr and about 20 Torr, between about 4 Torr and about 12 Torr, or about 7 Torr, or about 9 Torr /cm ² and about 700mW/cm ² , such as between about 290mW/cm ² and about 440mW/cm ² RF power, will be about

or larger, such as approx.

A p-type microcrystalline silicon layer with a crystallization rate of between about 20% and about 80%, such as between about 50% and about 70%, is deposited at a rate of or greater.

或更大的速率沉积p-型非晶硅层。甲烷或其他含碳化合物(诸如CH₄、C₃H₈、C₄H₁₀、或C₂H₂)的添加可以用来形成含碳的p-型非晶硅层106，所述含碳的p-型非晶硅层比其他含硅材料吸收更少的光。换言之，在形成的p-型非晶硅层106含有合金元素(诸如碳)的组态中，所形成的层将具有改善的光穿透性质或窗性质(例如以降低太阳能辐射的吸收)。透射通过p-型非晶硅层106的太阳能辐射量的增加可以被本征层吸收，因而改善了太阳能电池的效能。在三甲基硼用来在p-型非晶硅层106中提供硼掺杂的实施例中，硼掺杂浓度被维持在介于约1×10¹⁸atoms/cm²与约1×10²⁰atoms/cm²之间。在甲烷气体被添加且被用来形成含碳的p-型非晶硅层的实施例中，含碳p-型非晶硅层中的碳浓度被控制在介于约10原子％与约20原子％之间。在一实施例中，p-型非晶硅层106的厚度介于约

与约之间，例如介于约与约

之间。In an embodiment where the p-type silicon-containing layer 106 is a p-type amorphous silicon layer, the p-type amorphous silicon layer 106 can be deposited by providing a gas mixture of hydrogen and silane gas, wherein the flow rate ratio of hydrogen to silane is is about 20:1 or less. Silane gas may be provided at a flow rate between about 1 sccm/L and about 10 sccm/L. Hydrogen may be provided at a flow rate between about 5 sccm/L and 60 sccm/L. Trimethylboron may be provided at a flow rate between about 0.005 sccm/L and about 0.05 sccm/L. If trimethylboron is provided in a carrier gas at a molar or volume concentration of 0.5 percent, the dopant/carrier gas mixture may be provided at a flow rate between about 1 sccm/L and about 10 sccm/L. Applying an RF power of between about 15 mW/cm ² and about 200 mW/cm ² at a chamber pressure of between about 0.1 Torr and 20 Torr, such as between about 1 Torr and about 4 Torr, will generate a power of about

or greater rates to deposit a p-type amorphous silicon layer. The addition of methane or other carbon-containing compounds such as CH ₄ , C ₃ H ₈ , C ₄ H ₁₀ , or C ₂ H ₂ can be used to form a carbon-containing p-type amorphous silicon layer 106 that A p-type amorphous silicon layer absorbs less light than other silicon-containing materials. In other words, in configurations where the p-type amorphous silicon layer 106 is formed to contain alloying elements such as carbon, the formed layer will have improved light transmission or window properties (eg, to reduce absorption of solar radiation). The increased amount of solar radiation transmitted through the p-type amorphous silicon layer 106 can be absorbed by the intrinsic layer, thereby improving the performance of the solar cell. In an embodiment where trimethylboron is used to provide boron doping in the p-type amorphous silicon layer 106, the boron doping concentration is maintained between about 1×10 ¹⁸ atoms/cm ² and about 1×10 ²⁰ between atoms/ ^cm2 . In embodiments where methane gas is added and used to form the carbon-containing p-type amorphous silicon layer, the carbon concentration in the carbon-containing p-type amorphous silicon layer is controlled between about 10 atomic percent and about 20 atomic % between. In one embodiment, the thickness of the p-type amorphous silicon layer 106 is between about

make an appointment between, e.g. about make an appointment

between.

或更大、诸如约

或更大的速率沉积结晶率介于约20％与约80％之间、诸如介于约50％与约70％的n-型微晶硅层。In an embodiment where the n-type silicon-containing layer 110 is an n-type microcrystalline silicon layer, the n-type microcrystalline silicon layer 110 may be deposited by providing a gas mixture of hydrogen and silane gas, wherein the volume flow rate of hydrogen to silane The ratio is about 100:1 or greater, eg about 500:1 or less, such as between about 150:1 and about 400:1, such as about 304:1 or about 203:1. Silane gas may be provided at a flow rate between about 0.1 sccm/L and about 0.8 sccm/L, such as between about 0.32 sccm/L and about 0.45 sccm/L, such as about 0.35 sccm/L. Hydrogen may be provided at a flow rate between about 30 sccm/L and about 250 sccm/L, such as between about 68 sccm/L and about 143 sccm/L, such as about 71.43 sccm/L. The phosphine may be provided at a flow rate between about 0.0005 sccm/L and about 0.006 sccm/L, for example between about 0.0025 sccm/L and about 0.015 sccm/L, such as about 0.005 sccm/L. In other words, if a molar or volume concentration of 0.5% phosphine is provided in the carrier gas, it may be between about 0.1 sccm/L and about 5 sccm/L, such as between about 0.5 sccm/L and about 3 sccm/L. The dopant/carrier gas mixture is provided at a flow rate between, such as between about 0.9 sccm/L and about 1.088 sccm/L. At a chamber pressure between about 1 Torr and about 100 Torr, such as between about 3 Torr and about 20 Torr, more preferably between about 4 Torr and about 12 Torr, such as about 6 Torr or about 9 Torr, apply a pressure of between An RF power of between about 100 mW/cm ² and about 900 mW/cm ² , such as about 370 mW/cm ² , will

or larger, such as approx.

An n-type microcrystalline silicon layer having a crystallization rate between about 20% and about 80%, such as between about 50% and about 70%, is deposited at a rate of or greater.

或更大、例如约

或更大，诸如约

或约

的速率沉积n-型非晶硅层。In an embodiment where the n-type silicon-containing layer 116 is an n-type amorphous silicon layer, the n-type amorphous silicon layer 116 can be deposited by providing a gas mixture of hydrogen and silane gas, wherein the volume flow rate of hydrogen to silane The ratio is about 20:1 or less, such as about 5.5:1 or 7.8:1. Can be between about 0.1 sccm/L and about 10 sccm/L, such as between about 1 sccm/L and about 10 sccm/L, between about 0.1 sccm/L and 5 sccm/L, or between about Silane gas is provided at a flow rate between 0.5 sccm/L and about 3 sccm/L, such as about 1.42 sccm/L or 5.5 sccm/L. May be between about 1 sccm/L and about 40 sccm/L, such as between about 4 sccm/L and about 40 sccm/L, or between about 1 sccm/L and about 10 sccm/L, such as about 6.42 sccm /L or 27sccm/L flow rate to provide hydrogen. Can be between about 0.0005 sccm/L and about 0.075 sccm/L, such as between about 0.0005 sccm/L and about 0.0015 sccm/L, or between about 0.015 sccm/L and about 0.03 sccm/L Between, a flow rate such as about 0.0095 sccm/L or 0.023 sccm/L provides the phosphine. If the phosphine is provided at a molar or volume concentration of 0.5% in the carrier gas, it may be between about 0.1 sccm/L and about 15 sccm/L, such as between about 0.1 sccm/L and about 3 sccm/L, A flow rate of between about 2 sccm/L and about 15 sccm/L, or between about 3 sccm/L and about 6 sccm/L, such as about 1.9 sccm/L or about 4.71 sccm/L provides the dopant/carrier gas mixture . Between about 25 mW/cm and about 250 mW/ ^cm are applied at a chamber pressure of between ^about 0.1 Torr and about 20 Torr, such as between about 0.5 Torr and about 4 Torr, or about 1.5 Torr , such as about 60mW/cm ² or about 80mW/cm ² of RF power, will

or larger, such as approx.

or larger, such as approx.

or about

The rate of deposition of n-type amorphous silicon layer.

In some embodiments, alloys of silicon and other elements such as oxygen, carbon, nitrogen, hydrogen, and germanium are useful. By supplementing the reactant gas mixture with a source of each other element, these other elements can be added to the silicon film. Silicon alloys can be used for any type of silicon layer, including interfacial layers, p-type, n-type, PIB, wavelength selective reflector (WSR) layers, or intrinsic type silicon layers. For example, carbon can be added to the silicon film by adding a carbon source such as methane ( _CH4 ) to the gas mixture. Generally, most C ₁ -C ₄ hydrocarbons can be used as carbon sources. Alternatively, organosilicon compounds such as organosilanes, organosiloxanes, organosilanols, and the like can be used as silicon and carbon sources. Germanium compounds, such as germane and organogermanes, and compounds containing silicon and germanium, such as silylgermane or germansilane, can be used as sources of germanium. Oxygen (O ₂ ) can be used as an oxygen source. Other sources of oxygen include, but are not limited to, oxides of nitrogen (nitrogen monoxide (N ₂ O), nitrogen monoxide (NO), nitrogen trioxide (N ₂ O ₃ ), nitrogen dioxide (NO ₂ ), Dinitrogen oxide (N ₂ O ₄ ), nitrogen pentoxide (N ₂ O ₅ ), and nitrogen trioxide (NO ₃ )), hydrogen peroxide (H ₂ O ₂ ), carbon monoxide or carbon dioxide (CO or CO ₂ ) , ozone (O ₃ ), oxygen atoms, oxygen groups, and alcohols (ROH, wherein R is any organic or heteroorganic group). Nitrogen sources may include nitrogen (N ₂ ), ammonia (NH ₃ ), hydrazine (N ₂ H ₂ ), amines (R _x NR' _3-x , where x is 0 to 3, and each R and R' is independently Any organic or heteroorganic group), amide ((RCO) _x NR' _3-x , where x is 0 to 3, and each R and R' is independently any organic or heteroorganic group), acyl Imine (RCONCOR', wherein each R and R' is independently any organic or heteroorganic group), enamine (R ₁ R ₂ C=C ₃ NR ₄ R ₅ , wherein each R ₁ -R ₅ is independently any organic or heteroorganic group), and nitrogen atoms and groups.

In order to improve the conversion efficiency and reduce the contact resistance, an interfacial layer may be formed at the interface between the TCO layer 104 and the p-type silicon-containing layer 106 . FIG. 2 illustrates an interfacial layer 202 disposed between the TCO layer 104 and the p-type silicon-containing layer 106 . The interface layer 202 provides a good interface that can improve the adhesion between the film layer formed on the interface and the TCO substrate. In some embodiments, the interfacial layer 202 may be a heavily doped or degenerately doped silicon-containing layer that is passed through at a high rate (such as previously The rate in the upper half of the ratio described in the text) supplies impurities to form. It is believed that degenerate doping can provide low resistance contact junctions and improve charge collection. It is also believed that degenerate doping can improve the conductivity of some layers, such as amorphous layers.

诸如

的膜。在一实施例中，重掺杂非晶硅层202的III族元素掺杂浓度为介于约10²⁰atoms/cm³与约10²¹atoms/cm³之间。In one embodiment, the interfacial layer 202 is a degenerately doped p-type amorphous silicon layer (heavily doped p-type amorphous silicon (p++) layer). The degenerate (eg heavily) doped p++-type amorphous silicon layer 202 has a higher doping concentration of Group III elements than the p-type silicon-containing layer 106 . The degenerate (eg, heavily) doped p++-type amorphous silicon layer 202 has a doping concentration equal to a layer at a pressure between about 2 Torr and about 2.5 Torr using a mixture volume flow rate ratio of about 2 :1 and about 6:1 between TMP and silane, wherein the TMB precursor contains TMB at a molar or volume concentration of 0.5%. The degenerate (eg, heavily) doped p++-type amorphous silicon layer 202 is formed at a plasma power between about 45 mW/cm ² (2400 Watts) and about 91 mW/cm ² (4800 Watts). In one example, the degenerately doped p++-type amorphous silicon layer 202 can be formed by a temperature between about 2.1 sccm/L (such as 6000 sccm) and about 3.1 sccm/L (such as 9000 sccm). Silane is provided at a flow rate, hydrogen is provided at a flow rate that results in a hydrogen to silane gas mixture ratio of about 6.0, and a flow rate that results in a 6:1 volumetric flow rate ratio of TMB gas (e.g., 0.5% molar or volume concentration TMB) to silane gas mixture Doping precursors are provided while the substrate support temperature is maintained at about 200° C., the plasma power is controlled at between about 57 mW/cm ² (3287 Watts), and the chamber pressure is maintained at about 2.5 Torr for up to about 2 -10 seconds to form approx.

such as

membrane. In one embodiment, the group III element doping concentration of the heavily doped amorphous silicon layer 202 is between about 10 ²⁰ atoms/cm ³ and about 10 ²¹ atoms/cm ³ .

与约之间，例如介于约与约

之间，诸如介于约

与约

之间。In one embodiment, the interfacial layer 202 may be a degenerately doped p-type amorphous silicon carbide layer (heavily doped p-type amorphous silicon carbide (p++) layer). Carbon may be provided by supplying a carbon-containing gas into the gas mixture when forming the heavily doped p-type amorphous silicon carbide layer 202 . In one embodiment, the addition of methane or other carbon-containing compounds (such as CH ₄ , C ₃ H ₈ , C ₄ H ₁₀ , or C ₂ H ₂ ) can be used to form the heavily doped p-type amorphous silicon carbide layer 202 , the heavily doped p-type amorphous silicon carbide layer can absorb less light from other silicon-containing material layers. It is believed that the addition of carbon atoms to the interface layer 202 can improve the light transmittance of the interface layer 202, so that less light will be absorbed or consumed when light passes through the layers, thus improving the conversion efficiency of the solar cell. In one embodiment, the carbon concentration in the heavily doped p-type amorphous silicon carbide layer 202 is controlled to a concentration between about 1 atomic % and about 50 atomic %. In one embodiment, the thickness of the interfacial p-type amorphous silicon carbide layer 202 is between about

make an appointment between, e.g. about make an appointment

between, such as about

make an appointment

between.

In the specific embodiment shown in FIG. 2, when the interface layer 202 is configured as a heavily doped p-type amorphous silicon layer or a heavily doped p-type amorphous silicon carbide layer, the p-type silicon-containing layer 106 may be It is configured as a p-type amorphous silicon layer or a p-type amorphous silicon carbide layer (amorphous silicon alloy layer) to meet different process requirements. In one embodiment, the interface layer 202 is a heavily doped p-type amorphous silicon layer, and the p-type silicon-containing layer 106 is a p-type amorphous silicon layer or a p-type amorphous silicon carbide layer. In another embodiment, the interface layer 202 is a heavily doped p-type amorphous silicon carbide layer, and the p-type silicon-containing layer 106 is a p-type amorphous silicon carbide layer.

In addition, a wavelength selective reflector (WSR) layer 206 can be disposed between the first pin junction 212 and the second pin junction 214 . The WSR layer 206 is configured to have film properties that improve light scattering and current generation in the formed solar cell 100 . Again, the WSR layer 206 also provides a good pn tunnel junction, the good pn tunnel junction has high conductivity and regulated energy bandgap range, and the high conductivity and regulated energy bandgap range can affect the The transmissive and reflective properties of the pn tunnel junction to improve the light conversion efficiency of the formed solar cells. The WSR layer 206 actively acts as an intermediate reflector having a desired refractive index or range of refractive indices to reflect light received from the light incident side of the solar cell 100 . The WSR layer 206 also acts as a junction layer that facilitates the absorption of short to medium wavelength light (eg, 280nm to 800nm) in the first pin junction 212 and improves short circuit current, thus improving quantum and conversion performance. The WSR layer 206 further has a high film transmittance for medium to long wavelength light (eg, 500 nm to 1100 nm) to facilitate light transmission to the layers formed at the second junction 214 . Furthermore, when light of a desired wavelength (eg, shorter wavelength) is reflected back to the layer in the first pin junction 212 and light of the desired wavelength (eg, longer wavelength) is transmitted to the layer in the second pin junction 214 , it is generally desired that the WSR layer 206 absorb as little light as possible. In addition, the WSR layer 206 can have a desired energy bandgap and high film conductivity, thereby efficiently conducting the generated current and allowing electrons to flow from the first pin junction 212 to the second pin junction 214, and avoiding the generation of blocking current. In one embodiment, the WSR layer 206 may be a microcrystalline silicon layer with n-type or p-type doping disposed therein. In an exemplary embodiment, the WSR layer 206 is an n-type crystalline silicon alloy with n-type doping disposed therein. Different doping within the WSR layer 206 also affects the optical and electrical properties of the WSR layer film, such as energy bandgap, crystallinity, electrical conductivity, light transmittance, film refractive index, extinction coefficient, and the like. In some examples, one or more impurities may be doped into various regions of the WSR layer 206 to efficiently control and tune the bandgap, work function, conductivity, light transmittance, etc. of the film. In one embodiment, the WSR layer 206 is controlled to have a refractive index between about 1.4 and about 4, an energy bandgap of at least about 2 eV, and a conductivity greater than about 10 ⁻⁶ S/cm.

In one embodiment, the WSR layer 206 may include an n-type doped silicon alloy layer, such as silicon oxide (SiO _x , SiO ₂ ), silicon carbide (SiC), silicon oxynitride (SiON), silicon nitride (SiN) , silicon nitride carbide (SiCN), silicon oxycarbide (SiOC), silicon oxycarbide nitrogen (SiOCN), or the like. In an exemplary embodiment, WSR layer 206 is an n-type SiON or SiC layer.

或更大。Also, a pi-buffer type intrinsic amorphous silicon (PIB) layer 208 may be selectively formed between the p-type silicon-containing layer 112 and the intrinsic type silicon-containing layer 114 in the second pin junction 214 . It is believed that the PIB layer 208 can efficiently provide transitional film properties between the film layers, thereby improving the overall conversion performance. In one embodiment, the PIB layer 208 may be deposited by providing a gas mixture of hydrogen and silane, wherein the volumetric flow rate ratio of hydrogen to silane is about 50:1 or less, such as less than about 30:1, such as between about Between 20:1 and about 30:1, such as about 25:1. Silane gas may be provided at a flow rate between about 0.5 sccm/L and about 5 sccm/L, such as about 2.3 sccm/L. Hydrogen may be provided at a flow rate between about 5 sccm/L and about 80 sccm/L, such as between about 20 sccm/L and about 65 sccm/L, such as about 57 sccm/L. An RF power of between about 15 mW/cm ² and about 250 mW/cm ² , for example about 30 mW/cm ² may be provided to the showerhead. The chamber pressure may be maintained between about 0.1 Torr and about 20 Torr, such as between about 0.5 Torr and about 5 Torr, or about 3 Torr. The deposition rate of the PIB layer 206 can be about

or larger.

Also, the degenerately doped n-type amorphous silicon layer 210 may be mainly formed as a heavily doped n-type amorphous silicon layer to provide improved ohmic contact with the second TCO layer 118 . In one embodiment, the heavily doped n-type amorphous silicon layer 210 has a doping concentration between about 10 ²⁰ atoms/cm ³ and about 10 ²¹ atoms/cm ³ .

FIG. 3 is an enlarged schematic diagram of another embodiment of the interfacial layer disposed between the TCO layer 104 and the p-type silicon-containing layer 106 . In addition to the aforementioned interface layer 202 of FIG. 2 , a second interface layer 304 may be disposed between the first interface layer 202 and the p-type silicon-containing layer 106 . The second interface layer 304 may have different film properties than the first interface layer 202 , thereby compensating for some electrical properties not fully provided by the first interface layer 202 . For example, films with higher conductivity typically have relatively low film transmittance, which can disadvantageously absorb or reduce the amount of light passing through the film to the solar cell junction, and vice versa. By using this bilayer structure, a greater amount of light with different wavelengths will be allowed to pass through the film to the first junction 212 and further to the second junction 214 while maintaining the desired film conductivity, thus resulting in a greater current flow.

与约之间的重掺杂非晶碳化硅层，并且第二界面层304为厚度介于约

与约

之间的p-型非晶碳化硅层。p-型含硅层106为p-型非晶硅层。In one embodiment, the second interfacial layer 304 is a p-type amorphous silicon layer, and the p-type amorphous silicon layer has a group III element doping concentration similar to that of the p-type silicon-containing layer 106, but has a different The film type (eg, dopant or alloying element) of the p-type silicon-containing layer 106 . For example, when the p-type silicon-containing layer 106 is configured as a p-type amorphous silicon layer, the second interface layer 304 may be configured as a p-type amorphous silicon carbide layer. The first interface layer 202 may be a heavily doped p-type amorphous silicon layer or a heavily doped p-type amorphous silicon carbide layer. The second interfacial layer 304 may be configured to have a p-type doping concentration less than that of the first interfacial layer 202 (eg, a heavily doped p-type layer) but similar to the p-type silicon-containing layer 106 . In the embodiment shown in FIG. 3, the first interface layer 202 has a thickness between about

make an appointment The heavily doped amorphous silicon carbide layer between, and the second interfacial layer 304 has a thickness between about

make an appointment

between p-type amorphous silicon carbide layers. The p-type silicon-containing layer 106 is a p-type amorphous silicon layer.

FIG. 4 illustrates another embodiment of the interface structure, wherein the interface structure has multiple layers formed between the TCO layer 104 and the p-type silicon-containing layer 106 . In addition to the interface layer 202 depicted in FIGS. 2-3 , an additional TCO layer 302 may be interposed between the bottom TCO layer 104 and the interface layer 202 . In an embodiment, while the bottom TCO layer 104 is configured as a tin oxide layer (SnO ₂ ), the additional TCO layer 302 may be configured as a zinc oxide (ZnO) layer. It is believed that the additional TCO layer 302 provides better chemical resistance to the plasma that is performed later in order to form subsequent layers on the TCO layer 302 . The good chemical resistance of the additional ZnO TCO layer 302 provides good surface texture control when plasma or etch processes are performed, thereby enhancing light harvesting capabilities. In addition, the additional TCO layer 302 can also provide high film transmittance, low film resistivity and high film conductivity, thereby maintaining high conversion efficiency of solar junction cells formed on the TCO layer 302 later. Thus, when the additional TCO layer 302 is formed on the bottom TCO layer 104, the film properties can be controlled in such a way as to improve conversion efficiency, reduce contact resistivity, provide high chemical resistance to plasma, and Good surface texture needed to capture light.

与约

之间。ZnO层302可以通过CVD、PVD、或任何其他适当的沉积技术来形成。In one embodiment, the additional TCO layer 302 may be a zinc oxide (ZnO) layer with a zinc doping concentration between about 5 wt % and about 5 wt %. The additional TCO layer 302 may have an aluminum doping concentration between about 5 wt % and about 5 wt %. The thickness of the additional TCO layer 302 can be controlled between about

make an appointment

between. ZnO layer 302 may be formed by CVD, PVD, or any other suitable deposition technique.

After forming the additional TCO layer 302 on the bottom TCO layer 104, an interfacial layer 202 and a p-type silicon-containing layer 106 may then be formed on the TCO layer 302 to form the desired junction. In an exemplary embodiment, the interfacial layer 202 is a heavily doped amorphous silicon layer, and the p-type silicon-containing layer 106 is a p-type silicon carbide layer.

相信p-型微晶硅层或纳米晶硅层可以比p-型非晶硅层提供更低的接触电阻。在图5绘示的示范性实施例中，TCO层104为含氧化锡(SnO₂)的TCO层。额外的TCO层302为含氧化锌(ZnO)的TCO层，并且p-型含硅层106是p-型纳米晶碳化硅层。FIG. 5 illustrates another embodiment of the interface structure formed between the TCO layer 104 and the p-type silicon-containing layer 106 . An additional TCO layer 302 (similar to the additional TCO layer 302 of FIG. 4 ) is located on the bottom TCO layer 104 . Next, a p-type silicon-containing layer 106 is located on the additional TCO layer 302 . In this particular embodiment, p-type silicon-containing layer 106 may be configured as a p-type microcrystalline/nanocrystalline silicon or silicon carbide layer. It should be appreciated that the nanocrystalline silicon layer has a particle size of about or less than and the grain size of the microcrystalline silicon layer is about or larger than

It is believed that a p-type microcrystalline or nanocrystalline silicon layer can provide lower contact resistance than a p-type amorphous silicon layer. In the exemplary embodiment shown in FIG. 5 , the TCO layer 104 is a TCO layer containing tin oxide (SnO ₂ ). Additional TCO layer 302 is a zinc oxide (ZnO) containing TCO layer, and p-type silicon containing layer 106 is a p-type nanocrystalline silicon carbide layer.

与约

之间的p-型微晶/纳米晶硅层或p-型微晶/纳米晶碳化硅层。然后，p-型含硅层106位于中间界面层602上。在图6绘示的实施例中，TCO层104为含氧化锡(SnO₂)的TCO层。额外的TCO层302为含氧化锌(ZnO)的TCO层。中间界面层602为p-型微晶/纳米晶碳化硅层，并且p-型含硅层106为p-型非晶碳化硅层。FIG. 6 shows another embodiment of the interface structure formed between the TCO layer 104 and the p-type silicon-containing layer 106 . An additional TCO layer 302 (similar to the additional TCO layer 302 of FIGS. 4-5 ) is located on the bottom TCO layer 104 . Next, an intermediate interface layer 602 is located on the additional TCO layer 302 . It is believed that the interfacial layer 602 can help to establish a high electric field between the additional TCO layer 302 and the p-type amorphous silicon layer 106 to be deposited, thereby effectively improving the conversion efficiency of the solar cell. In one embodiment, the intermediate interface layer 602 has a thickness between about

make an appointment

between p-type microcrystalline/nanocrystalline silicon layers or p-type microcrystalline/nanocrystalline silicon carbide layers. A p-type silicon-containing layer 106 is then located on the intermediate interface layer 602 . In the embodiment shown in FIG. 6 , the TCO layer 104 is a TCO layer containing tin oxide (SnO ₂ ). The additional TCO layer 302 is a TCO layer containing zinc oxide (ZnO). The interfacial layer 602 is a p-type microcrystalline/nanocrystalline silicon carbide layer, and the p-type silicon-containing layer 106 is a p-type amorphous silicon carbide layer.

与约

之间的p-型微晶/纳米晶硅层。第二中间层704可以是厚度介于约

与约之间的p-型微晶/纳米晶碳化硅层。在形成该三膜结构后，p-型含硅层106可以形成在该三膜结构上。在一实施例中，形成在该三膜结构上的p-型含硅层106可以是p-型非晶碳化硅层。FIG. 7 illustrates another embodiment of the interface structure formed between the TCO layer 104 and the p-type silicon-containing layer 106 . In this embodiment, a three-film structure is formed between the TCO layer 104 and the p-type silicon-containing layer 106 . The three-film structure includes an additional TCO layer 302 , a first intermediate layer 702 and a second intermediate layer 704 . The additional TCO layer 302 is similar to the additional TCO layer 302 of FIGS. 4-6. It is believed that silicon-based layers (e.g., not doped with carbon) can have relatively high electrical conductivity, while silicon-alloy layers (e.g., doped with carbon or other alloys) will have high film light transmittance and can allow a large amount of light to pass through. Reach the junction battery. Therefore, by utilizing the three-film structure, high film conductivity, high film transmittance for high conversion efficiency, and low contact resistivity can be obtained. In the embodiment shown in FIG. 7, the first intermediate layer 702 may have a thickness between about

make an appointment

between p-type microcrystalline/nanocrystalline silicon layers. The second intermediate layer 704 may be between about

make an appointment between p-type microcrystalline/nanocrystalline SiC layers. After forming the three-film structure, a p-type silicon-containing layer 106 may be formed on the three-film structure. In one embodiment, the p-type silicon-containing layer 106 formed on the three-film structure may be a p-type amorphous silicon carbide layer.

与约

之间的p-型微晶/纳米晶碳化硅层。相信，在等离子体处理以沉积后续的膜层时，使用ZnO系TCO层104可以提供良好的化学阻抗性。替代地，TCO层104也可以被配置为n-型掺杂的氧化铝锌(AZO)层。n-型掺杂可以包括硼、铝、镓、及类似物。在此特定实施例中，含ZnO的TCO层104的厚度可以介于约与约

之间。FIG. 8 illustrates another embodiment of the interface structure formed between the TCO layer 104 and the p-type silicon-containing layer 802 . In this embodiment, the TCO layer 104 is chosen to be made from a zinc oxide (ZnO) containing layer. The p-type silicon-containing layer 802 formed on the TCO layer 104 has a thickness between about

make an appointment

between p-type microcrystalline/nanocrystalline SiC layers. It is believed that the use of the ZnO-based TCO layer 104 provides good chemical resistance during plasma treatment to deposit subsequent layers. Alternatively, the TCO layer 104 may also be configured as an n-type doped aluminum zinc oxide (AZO) layer. N-type dopants may include boron, aluminum, gallium, and the like. In this particular embodiment, the thickness of the ZnO-containing TCO layer 104 can be between about make an appointment

between.

与约

之间的p-型微晶/纳米晶碳化硅层。然后，p-型含硅层106位于界面层602上。在图9绘示的示范性实施例中，TCO层104为含氧化锌(ZnO)的TCO层，并且界面层602为p-型微晶/纳米晶碳化硅层，并且p-型含硅层106为p-型非晶碳化硅层。FIG. 9 illustrates another embodiment of the interface structure formed between the TCO layer 104 and the p-type silicon-containing layer 106 . Similar to the TCO layer 104 of FIG. 8, in this particular embodiment, the TCO layer 104 may be selected to be made from a zinc oxide (ZnO)-containing layer. Next, an interface layer 602 , such as the middle interface layer 602 shown in FIG. 6 , is located on the TCO layer 104 . It is believed that the interfacial layer 602 can help to establish a high electric field between the additional TCO layer 104 and the p-type amorphous silicon layer 106 to be deposited, thereby effectively improving the conversion efficiency of the solar cell. In one embodiment, the interface layer 602 has a thickness between about

make an appointment

between p-type microcrystalline/nanocrystalline SiC layers. A p-type silicon-containing layer 106 is then located on the interfacial layer 602 . In the exemplary embodiment shown in FIG. 9, the TCO layer 104 is a TCO layer containing zinc oxide (ZnO), and the interfacial layer 602 is a p-type microcrystalline/nanocrystalline silicon carbide layer, and the p-type silicon-containing layer 106 is a p-type amorphous silicon carbide layer.

与约

之间的p-型微晶/纳米晶硅层。第二中间层704可以是厚度介于约

与约

之间的p-型微晶/纳米晶碳化硅层。在形成该双膜结构于TCO层104上后，p-型含硅层106可以形成在该双膜结构上。在一实施例中，形成在该双膜结构上的p-型含硅层106可以是p-型非晶碳化硅层。FIG. 10 shows another embodiment of the interface structure formed between the TCO layer 104 and the p-type silicon-containing layer 106 . In the embodiment shown in FIG. 10 , a double film structure is formed between the TCO layer 104 and the p-type silicon-containing layer 106 . Similar to the TCO layer 104 of FIGS. 7-9, in this particular embodiment, the TCO layer 104 may be selected to be made from a zinc oxide (ZnO)-containing layer. The double-film structure includes a first intermediate layer 702 and a second intermediate layer 704 , similar to the first intermediate layer 702 and the second intermediate layer 704 in FIG. 7 . The first intermediate layer 702 may be between about

make an appointment

between p-type microcrystalline/nanocrystalline silicon layers. The second intermediate layer 704 may be between about

make an appointment

between p-type microcrystalline/nanocrystalline SiC layers. After forming the double film structure on the TCO layer 104, a p-type silicon-containing layer 106 may be formed on the double film structure. In one embodiment, the p-type silicon-containing layer 106 formed on the double-film structure may be a p-type amorphous silicon carbide layer.

11 is a cross-sectional view of one embodiment of a plasma-enhanced chemical vapor deposition (PECVD) chamber 1100 in which one or more films of a thin-film solar cell, such as the solar cells of FIGS. Deposition is performed in a vapor phase deposition (PECVD) chamber 1100 . A suitable plasma enhanced chemical vapor deposition chamber is available from Applied Materials, Inc., Santa Clara, CA. It should be understood that other process chambers, including process chambers from other vendors, may also be used to practice the present invention.

In general, chamber 1100 includes walls 1102 , bottom 1104 , showerhead 1110 , and substrate support 1130 that define a process volume 1106 . The process volume 1106 is accessible via a valve 1108 so that substrates can be transferred in and out of the chamber 1100 . The substrate support 1130 includes a substrate receiving surface 1132 for supporting the substrate and a rod 1134 coupled to a lowering system 1136 for raising and lowering the substrate support 1130 . A shadow ring 1133 may optionally be placed over the perimeter of the substrate 102 . Lift pins 1138 are movably disposed through the substrate support 1130 to move the substrate to and from the substrate receiving surface 1132 . The substrate support 1130 may also include heating and/or cooling members 1139 to maintain the substrate support 1130 at a desired temperature. The substrate support 1130 may also include a plurality of ground straps 1131 to provide RF grounding at the perimeter of the substrate support 1130 .

Showerhead 1110 is coupled to backplate 1112 by suspensions 1114 at the perimeter of the backplate. The showerhead 1110 may also be coupled to the backplate by one or more central supports 116 to help prevent sagging and/or control the straightness/curvature of the showerhead 1110 . Gas source 1120 is coupled to backing plate 1112 to provide gas through backing plate 1112 and through showerhead 1110 to substrate receiving surface 1132 . A vacuum pump 1109 is coupled to the chamber 1100 to control the process volume 1106 at a desired pressure. RF power source 1122 is coupled to backplate 1112 and/or showerhead 1110 to provide RF power to showerhead 1110 such that an electric field is established between showerhead and substrate support 1130 and thus can Plasma is generated from a gas. Various RF frequencies may be used, such as frequencies between about 0.3 MHz and about 200 MHz. In one embodiment, the RF power source is provided at a frequency of 13.56 MHz.

A remote plasma source (eg, an inductively coupled remote plasma source) may also be coupled between the gas source and the backplate. Between processing multiple substrates, a cleaning gas may be provided to the remote plasma source 1124, thereby generating and providing a remote plasma to clean chamber components. The cleaning gas may be further excited by the RF power source 1122 provided to the showerhead. Suitable cleaning gases include, but are not limited to, NF ₃ , F ₂ and SF ₆ .

A deposition method for use in one or more layers, such as one or more layers of FIGS. 1-10, in FIG. 11 or other suitable chambers may include the following deposition parameters. A substrate having a surface area of 10,000 cm ² or greater, 40,000 cm ² or greater, or 55,000 cm ² or greater is provided to the chamber. It should be appreciated that after processing the substrate, the substrate may be cut to form smaller solar cells.

In one embodiment, heating and/or cooling member 1139 may be configured to provide about 400°C or less during deposition, for example between about 100°C and about 400°C, or between about 150°C and about A substrate support temperature of between 300°C, such as about 200°C.

During deposition, the separation between the top surface of the substrate disposed on the substrate receiving surface 1132 and the showerhead 1110 may be between about 400 mils and about 1,200 mils, such as between 400 mils and about 800 mils.

FIG. 12 is a top view of an embodiment of a process system 1200 having a plurality of process chambers 1231-1237, such as the PECVD chamber of FIG. 11 or other suitable chambers for depositing silicon films. The process system 1200 includes a transfer chamber 1220 coupled to the load lock chamber 1210 and a plurality of process chambers 1231 - 1237 . The load lock chamber 1210 allows substrates to be transferred between the ambient environment outside the system and the vacuum environment within the transfer chamber 1220 and process chambers 1231-1237. The load lock chamber 1210 includes one or more evacuatable regions that hold one or more substrates. The evacuable regions are pumped down during the transfer of substrates into the system 1200 and vented during transfer of the substrates out of the system 1200 . At least one vacuum robot arm 1222 is disposed in the transfer chamber 1220, and the vacuum robot arm 1222 is adapted to transfer the substrate between the load lock chamber 1210 and the process chambers 1231-1237. Although FIG. 12 shows seven chambers, it is not intended to limit the scope of the invention to this configuration, as the system may have any suitable number of process chambers.

In a particular embodiment of the invention, the system 1200 is configured to deposit a first p-i-n junction (eg, 122, 212) of a multi-junction solar cell. In one embodiment, one of the process chambers 1231-1237 is configured to deposit the interface layer and the p-type layer of the first p-i-n junction, while the remaining process chambers 1231-1237 are each configured to deposit this Signature layer and n-type layer. The intrinsic and n-type layers of the first p-i-n junction can be deposited in the same chamber without any passivation treatment between deposition steps. Thus, in one configuration, a substrate enters the system via a load lock chamber 1210, and the substrate is then transferred by a vacuum robot into a dedicated process chamber configured to deposit a p-type layer. Then, after forming the p-type layer, the substrate is transferred by the vacuum robot into one of the remaining process chambers configured to deposit the intrinsic and n-type layers. After the intrinsic and n-type layers are formed, the substrate is transferred back to the load lock chamber 1210 by the vacuum robot 1222 . In certain embodiments, the process chamber is used to process the substrate to form the p-type layer in about 4 times or more time compared to the time to form the intrinsic and n-type layers in a single chamber times, such as 6 times or more times. Thus, in a particular embodiment of the system for depositing the first p-i-n junction, the ratio of p-chambers to i/n-chambers is 1:4 or greater, such as 1:6 or greater. The throughput of the system (including the time the plasma is provided to clean the process chamber) may be about 10 substrates/hour or greater, such as 20 substrates/hour or greater.

In a particular embodiment of the invention, system 1200 is configured to deposit a second p-i-n junction (eg, reference numeral 124, 214) of a multi-junction solar cell. In one embodiment, one of the process chambers 1231-1237 is configured to deposit the p-type layer of the second p-i-n junction, while the remaining process chambers 1231-1237 are each configured to deposit the intrinsic type layer and n-type layers. The intrinsic and n-type layers of the second p-i-n junction can be deposited in the same chamber without any passivation process between deposition steps. In certain embodiments, the process chamber is used to process the substrate to form the p-type layer in about 4 times or more time compared to the time to form the intrinsic and n-type layers in a single chamber times. Thus, in a particular embodiment of the system for depositing the second p-i-n junction, the ratio of p-chambers to i/n-chambers is 1:4 or greater, such as 1:6 or greater. The throughput of the system (including the time the plasma is provided to clean the process chamber) may be about 3 substrates/hour or greater, such as 5 substrates/hour or greater.

In a particular embodiment, the throughput of the system 1200 configured to deposit a first p-i-n junction comprising an intrinsic type amorphous silicon layer is twice the throughput of a system 1200 configured to deposit a second p-i-n junction comprising an intrinsic type microcrystalline silicon layer times, which is due to the thickness difference between the intrinsic type microcrystalline silicon layer and the intrinsic type amorphous silicon layer. Therefore, a single system 1200 suitable for depositing a first p-i-n junction comprising an intrinsic type amorphous silicon layer can be matched to a single system 1200 suitable for depositing a second p-i-n junction comprising an intrinsic type Two or more systems of microcrystalline silicon layers). Accordingly, the WSR layer deposition process may be configured to be performed in a system suitable for depositing the first p-i-n junction for efficient throughput control. Once the first p-i-n junction has been formed in one system, the substrate can be exposed to ambient (ie, vacuum breaking) and transferred to a second system in which the second p-i-n junction is formed. Dry or wet cleaning of the substrate between the first system depositing the first p-i-n junction and the second system depositing the second p-i-n junction may be necessary. In an embodiment, the WSR layer deposition process may be configured to be performed in a stand-alone system.

Figure 13 depicts a configuration of a portion of a production line 1300 having a plurality of deposition systems 1304, 1305, 1306 or cluster tools that are composed of The automation device 1302 is tranportably connected. In one configuration, as shown in FIG. 13, a production line 1300 includes a plurality of deposition systems 1304, 1305, 1306 that can be used to form one or more layers on a substrate 102, forming p-i-n junction, or form a complete solar cell device. Systems 1304 , 1305 , 1306 may be similar to system 1200 depicted in FIG. 12 , but systems 1304 , 1305 , 1306 are generally configured to deposit different layers or junctions on substrate 102 . Typically, each deposition system 1304, 1305, 1306 has a load lock chamber 1304F, 1305F, 1306F that is similar to load lock chamber 1210, and each load lock chamber 1304F, 1305F, 1306F is in transmissive communication with automation device 1302 . Automation 1302 is configured to move substrates between deposition systems 1304 , 1305 , and 1306 .

Substrates are generally transferred from system automation 1302 to one of systems 1304, 1305, and 1306 during a process sequence. In one embodiment, the system 1306 has a plurality of chambers 1306A-1306H each configured to deposit or process one or more layers in the formation of an interface layer, a first p-i-n junction, the system 1305 has a plurality of chambers 1305A- 1305H configured to deposit one or more WSR layers, and system 1304 has a plurality of chambers 1304A- 1304H configured to deposit one or more WSR layers 1304A- 1304H 1304H is configured to deposit or process one or more layers while forming the second p-i-n junction. It should be appreciated that the number of systems and the number of chambers configured to deposit the various layers in each system can be varied to meet different process requirements and configurations.

The automation device 1302 may generally include a robotic device or conveyor adapted to move and position substrates. In one example, the automation device 1302 is a series of conventional substrate conveyors (e.g., roller conveyors) and/or robotic devices (e.g., 6-axis robotic arms, SCARA robotic arms), which are adapted to Substrates need to be moved and positioned within the production line 1300 . In one embodiment, the one or more automation devices 1302 also include one or more substrate lift components, or drawbridge conveyors, which are used to allow desired A substrate upstream of the system is transported past a substrate blocking its movement to another desired location. In this way, movement of substrates to various systems will not be hindered by other substrates to be delivered to other systems.

In one embodiment of the production line 1300, the patterning chamber 1350 is in communication with one or more conveyors 1302, and the patterning chamber 1350 is configured to process one or more of the formed WSR layers or any of the layers used to form junctions. The layers of the cell perform a patterning process. It will be appreciated that the patterning process can also be used to etch one or more regions of one or more previously formed layers during the solar cell device formation process. Although the configuration of patterning chamber 1350 generally discusses an etch-type patterning process, such a configuration does not limit the scope of the invention described herein. In one embodiment, patterning chamber 1350 is used to remove one or more regions of one or more formed layers and/or deposit one or more layers of materials (e.g., doped materials, metal pastes, etc.) ) on one or more formed layers on the surface of the substrate.

Although the foregoing description has focused on embodiments of the invention, other and further embodiments of the invention can be conceived without departing from the basic scope of the invention, and the scope of the invention is determined by the appended claims. By way of example, the process chamber of Figure 11 has been shown in a horizontal position. It can be understood that in other embodiments of the present invention, the process chamber can be located in any non-horizontal position, such as a vertical position. Embodiments of the invention have been described with reference to the multi-chamber cluster tool of Figures 12 and 13, but in-line and hybrid in-line/cluster systems may also be used. has been made by reference to the first system (the first system configured to form the first p-i-n junction), the second system (the second system configured to form the WSR layer) and the third system (the third system configured to form the first Two p-i-n junctions) to describe embodiments of the present invention, but it is also possible to form the first p-i-n junction, the WSR layer, and the second p-i-n junction in a single system. Embodiments of the invention have been described with reference to process chambers suitable for depositing WSR, intrinsic and n-type layers, but separate chambers may also be suitable for depositing intrinsic and n-type layers and WSR layer, and a single process chamber can be adapted to deposit p-type layer, WSR layer and intrinsic type layer. Finally, the embodiments described herein are generally p-i-n structures applicable to transparent substrates such as glass, but other embodiments are conceivable in which n-i-p junctions (whether single or multiple stacks) can Build up on non-transparent substrates such as stainless steel or polymers in a reverse deposition sequence.

Therefore, the present invention provides an apparatus and method for forming an interface structure between a TCO layer and a solar cell junction. Compared with traditional methods, the interface structure advantageously provides low contact resistance, high film conductivity and high film transmittance, which can effectively improve the photoelectric conversion efficiency and device performance of PV solar cells.

Although the foregoing description has focused on embodiments of the invention, other and further embodiments of the invention can be conceived without departing from the basic scope of the invention, and the scope of the invention is determined by the appended claims.

Claims (15)

1. A photovoltaic device, comprising: a first TCO layer, the first TCO layer is disposed on the substrate; a second TCO layer disposed on the first TCO layer; and a p-type silicon-containing layer formed on the second TCO layer. 2. The photovoltaic device of claim 1, wherein the p-type silicon-containing layer comprises carbon. 3. The photovoltaic device of claim 1, further comprising: A p-type silicon carbide layer disposed between the second TCO layer and the p-type silicon-containing layer, wherein the p-type silicon carbide layer is at least one of the following : Microcrystalline silicon carbide layer, nanocrystalline silicon carbide layer or amorphous silicon carbide layer. 4. The photovoltaic device of claim 3, further comprising: A p-type nanocrystalline silicon layer, the p-type nanocrystalline silicon layer is disposed between the second TCO layer and the p-type silicon carbide layer. 5. The photovoltaic device of claim 1, further comprising: A degenerately doped p-type amorphous silicon layer is disposed between the second TCO layer and the p-type silicon-containing layer. 6. The photovoltaic device of claim 1, wherein the first TCO layer is a tin oxide-containing layer and the second TCO layer is a zinc oxide-containing layer. 7. The photovoltaic device of claim 1, further comprising: an intrinsic type silicon-containing layer disposed on the p-type silicon-containing layer; and An n-type silicon-containing layer disposed on the intrinsic type silicon-containing layer. 8. A photovoltaic device comprising: TCO layer, the TCO layer is arranged on the substrate; an interfacial layer disposed on the TCO layer, wherein the interfacial layer is a p-type silicon-containing layer comprising carbon; and a p-type silicon-containing layer disposed on the interface layer. 9. The photovoltaic device of claim 8, wherein the interfacial layer is a degenerately doped p-type amorphous silicon carbide layer or a p-type microcrystalline silicon carbide layer. 10. The photovoltaic device of claim 8, further comprising: A p-type nanocrystalline silicon layer, the p-type nanocrystalline silicon layer is disposed between the interface layer and the TCO layer. 11. The photovoltaic device of claim 8, wherein the TCO layer is a zinc oxide-containing layer having an n-type doping element selected from aluminum, boron, or gallium. 12. A method of forming a photovoltaic device comprising the steps of: forming a first TCO layer on the substrate; forming a second TCO layer on the first TCO layer; and Forming a first p-i-n junction on the second TCO layer, wherein forming the first p-i-n junction includes the following steps: forming a p-type silicon-containing layer over the second TCO layer, wherein the p-type silicon-containing layer is Microcrystalline silicon layer, nanocrystalline silicon layer or amorphous silicon layer; forming an intrinsic silicon-containing layer over the p-type silicon-containing layer; and An n-type silicon-containing layer is formed over the intrinsic type silicon-containing layer. 13. The method of claim 12, further comprising the steps of: forming a p-type silicon carbide layer located between the second TCO layer and the first p-i-n junction, wherein the p-type silicon carbide layer is at least one of the following: micro A crystalline silicon carbide layer, a nanocrystalline silicon carbide layer or an amorphous silicon carbide layer. 14. The method of claim 13, further comprising the steps of: A p-type nanocrystalline silicon layer is formed between the second TCO layer and the p-type silicon carbide layer. 15. The method of claim 12, wherein the first TCO layer is a tin oxide-containing layer and the second TCO layer is a zinc oxide-containing layer.

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