CN102341864A - Nand flash architecture with multi-level row decoding - Google Patents
Nand flash architecture with multi-level row decoding Download PDFInfo
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- CN102341864A CN102341864A CN2010800099676A CN201080009967A CN102341864A CN 102341864 A CN102341864 A CN 102341864A CN 2010800099676 A CN2010800099676 A CN 2010800099676A CN 201080009967 A CN201080009967 A CN 201080009967A CN 102341864 A CN102341864 A CN 102341864A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
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Abstract
A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.
Description
The cross reference of related application
The application requires the U.S. Provisional Application No.61/157 of submission on March 5th, 2009, the U. S. application No.12/495 that on June 30th, 594 and 2009 submitted to, and 089 rights and interests are incorporated into this with its full content by reference.
Technical field
A kind of NAND flash memory device is disclosed.
Background technology
In traditional NAND flash memory, wipe and be based on every and carry out.Different with it, read and be based on every page with programming operation and carry out.
Description of drawings
Through with reference to accompanying drawing, example embodiment will be described at present, wherein:
Fig. 1 is the block diagram of typical memory nuclear framework in the NAND flash memory;
Fig. 2 is the block diagram of example NAND flash memory device, has wherein realized a NAND nuclear framework described herein;
Fig. 3 is the block diagram of the memory core framework of the NAND flash memory that is used for being provided by example embodiment;
Fig. 4 is the block diagram of the memory core framework in the NAND flash memory that is provided by example embodiment;
Fig. 5 and 6 shows reading single page and reading the multipage operation of the example embodiment that is used for Fig. 3 respectively;
Fig. 7 is the block diagram according to memory core framework in the NAND flash memory of example embodiment;
Fig. 8 is the block diagram according to the overall line decoder of example embodiment;
Fig. 9 is the circuit diagram of example embodiment of the monolithic code translator of Fig. 8;
Figure 10 is the block diagram of another example embodiment of the monolithic code translator of Fig. 8;
Figure 11 is the block diagram according to the local line decoder of example embodiment;
Figure 12 is the circuit diagram of example embodiment of single sector code translator of Figure 10;
Figure 13 is the sequential chart that is used to read according to example embodiment;
Figure 14 is the sequential chart that is used to programme according to example embodiment; With
Figure 15 is the sequential chart that is used to wipe according to example embodiment.
Embodiment
Fig. 1 shows the memory core framework in the NAND flash memory.
NAND flash memory nuclear comprises nand memory cell array 100, line decoder 102 and page buffer circuit 103 and column decoder 104.Line decoder 102 is connected to nand memory cell array 100 through one group of word line, for the sake of simplicity, in Fig. 1, only shows a word line 106.Page buffer circuit 103 is connected to nand memory cell array 100 through one group of bit line, for the sake of simplicity, in Fig. 1, only shows a bit line 108.
But the cell array structure of NAND flash memory comprises one group of n erase block.Each piece is subdivided into m programmable page (OK).
The wiping of memory core framework that is used for Fig. 1 is based on every and carries out.Different with it, read and be based on every page with programming operation and carry out.
NAND flash memory with nuclear framework of Fig. 1 flash memory receives at least three kinds of restrictions.The first, the position only just can be programmed after wiping the target memory array.The second, each unit only can stand limited number of time to be wiped, and it no longer can store data reliably after this.In other words, there is the restriction (that is, permanance is generally 10000 to 100000 circulations) of wiping for the unit with the program cycles number of times.The 3rd, I is wiped array sizes much larger than minimum programmable array size.Because being performed, these restrictions, complex data structures and algorithm effectively use flash memory.
Even only a fraction of data of the page are write or data modification, comprise the piece that to revise the page and will be reprogrammed to one of them that erase unit is regained free time (sky) piece that process states usually when the request of flash controller.In this case, comprise that effective page of primary data is copied to selected free block in the original block.After this, this new, have and in certain page, be modified data and the primary data in all the other pages, be mapped to effective block address once more through the virtual map system in the flash controller.Do not re-use original block now, and after it is wiped free of, the unit's of being wiped free of withdrawal process is claimed as free block.
Wipe-life-span that the limited number of times (permanance) of program cycles has limited flash devices.It is useful having the long as far as possible life-span, and this depends on the access module to flash devices.To individual unit or will cause beginning soon fault with frequent rewriting repeatedly and so can finish very soon in serviceable life of equipment to the sub-fraction unit.
In addition, in having the flash memory system of a plurality of flash devices,, then can cause when miscellaneous equipment also has the significantly long life-span and the life-span of an equipment finishes if there is remarkable uneven behaviour in service between the equipment in flash memory system.Finish when an equipment life, whole accumulator system must be replaced, so this has greatly reduced the life-span of flash memory system.
If rewrite all unit of the equipment that can be distributed evenly at, then fault takes place and will be postponed as far as possible, thus the life-span that has maximized equipment.For all unit through even use equipment prolong equipment life, proposed multiple consume balancing technique and algorithm and in flash memory system, be performed.
At last, the cell array of nand flash memory is miniaturized, anyly further reduces to wipe causing seriously reducing-degree of the maximum quantity of program cycles if make that they have reached in technology, to have.
According to a broad aspect, a kind of NAND flash memory nuclear of multistage row decoding is provided.
According to another broad aspect; A kind of NAND flash memory device that comprises following parts is provided: peripheral circuit, i/o pads, high-voltage generator and NAND flash memory nuclear; This NAND flash memory nuclear comprises: comprise that multirow takes advantage of the nand memory cell array of multiple row; This unit is arranged to a plurality of sectors, and each sector comprises the unit of a plurality of said row; This unit is arranged to a plurality of, and each piece comprises the unit of a plurality of said row; This nand memory cell array is configured to be used for wipe and be configured to resolution with a row in the sector with the resolution of a piece in the sector read and programme.
According to another broad aspect, the method in a kind of NAND flash memory nuclear is provided, comprising: carry out multistage row decoding.Owing to the size between reading/programme and wiping does not match, unnecessary programming operation is introduced in above-mentioned replicate run, and this is because the data that do not become in the page of piece are arrived new piece by reprogramming (duplicating) together with the data that are modified.If minimum wiped array sizes then will prolong less than whole equipment life greatly.
Fig. 2 is the block diagram that comprises the equipment 150 of NAND flash memory device 152.NAND flash memory device 152 has the memory core of multistage row decoding, and total terrestrial reference is designated as 158.In addition, NAND flash memory device 152 has peripheral circuit 154, input and output pad 156 and high-voltage generator 160.Peripheral circuit 154 can for example comprise one or more input and output impact dampers of being used for address and data, be used to control and the input buffer of command signal and the state machine that comprises command decoder, address counter, the preparatory code translator of row and column and status register.Equipment 150 can be to use any apparatus of NAND flash memory device 152.Concrete example comprises mobile device, memory stick, camera, solid magnetic disc driver and MP3 player.Flash devices 152 can be a permanent part of equipment 150 or for movably.The detailed example embodiment of the memory core of multistage row decoding is provided below.More generally, conceived any memory core of multistage row decoding.Cell array is formed by the sector, and each sector comprises the multiple row unit.This unit also forms piece, and each piece comprises a plurality of row, also is called as the page.In certain embodiments, multistage row decoding comprises for all sectors carries out first order row decoding, and for each sector, carries out the second level row decoding that only is used for this sector.In certain embodiments, come wiping in the execute store nuclear with the resolution of a piece in the sector, and read and programming operation with the resolution of a row in the sector.
With reference now to Fig. 3,, it shows the nuclear framework that example embodiment provides.This nuclear framework comprises the nand memory cell array, and this nand memory cell array is implemented as at least two nand memory cell array sectors, after this, abbreviates " sector " as, shows 4 sectors 200,202,204 and 206 in the example shown.This nand memory cell array forms by a plurality of, these a plurality of and then formed by the page again, also is called row.The unit of each sector of this nand memory cell array is also with the column distribution (not shown).The row decoding function is provided by overall line decoder 208 and one group of local line decoder 210,212,214 and 216 jointly; Overall situation line decoder 208 is carried out row decoding on the rank of piece, local line decoder 210,212,214 and 216 is carried out decoding on the rank at the page in the piece that overall line decoder is selected.More generally, overall line decoder 208 is carried out the subclass that first order row decoding is selected multirow.In the example embodiment of describing in detail herein, optional subclass is an adjacent block, all is this situation but need not all embodiments.Local line decoder 210,212,214 and 216 execution second level row decodings come in the subclass of a plurality of row that overall line decoder 208 is selected, to select delegation.Local line decoder 210,212,214 and 216 comprises relevant with each respective sectors 200,202,204 and 206 a local line decoder and in relevant sector execution page selection.The page buffer function realizes each sector (200,202,204 and 206) page buffer circuit by 4 page buffer circuits 220,222,224 and 226.The column decoder function realizes each sector (200,202,204 and 206) column decoder by 4 column decoders 221,223,225 and 227.
Read operation is carried out with the resolution of the page in the piece in the sector.Programming operation is also carried out with the resolution of the page in the piece in the sector.Yet the page in the piece in the sector was wiped free of before being programmed.Erase operation is carried out with the resolution of the piece in the sector.
For read operation, a plurality of of being used in the nand memory cell array of overall line decoder 208 select piece.Select to carry out the sector through carrying out column selection by page buffer circuit relevant and column decoder with the memory sectors of expectation.The page buffer circuit that can for example enable to be correlated with through Memory Controller is accomplished aforesaid operations with column decoder and/or to relevant page buffer circuit and column decoder transmission column decoder signal.Carrying out the page by the local line decoder relevant with selected sector selects.By this way, can read the selected page in the selected block in the selected sector.During read operation, the page buffer circuit of sensor amplifier (not shown) and selected sector is read and be latched into to the data of the selected page in the selected block in the selected sector.Afterwards, the data that are kept in the page buffer circuit are called over and for example are saved in the global buffer (not shown) through relevant column decoder.
For read operation, a plurality of of being used in the nand memory cell array of overall line decoder 208 select piece.Select to carry out the sector through carrying out column selection by page buffer circuit relevant and column decoder with the memory sectors of expectation.Then, apply suitable erase signal.By this way, can wipe selected block in the selected sector.
For programming operation, a plurality of of being used in the nand memory cell array of overall line decoder 208 select piece.Carry out the sector selection through carrying out column selection by page buffer circuit relevant and column decoder with the memory sectors of expectation.Carrying out the page by the local line decoder relevant with selected sector selects.Subsequently, the content of the page buffer circuit relevant with selected sector is programmed into the selected page in the selected block in the selected sector.During programming operation, input data (for example, from the global buffer circuit, not showing) are written into the page buffer circuit of selected sector by order via relevant column decoder.Be latched in the selected page that input data in the page-buffer circuit are programmed into selected sector subsequently.
Fig. 4 shows another example of the nuclear framework that example embodiment provides.This example embodiment is similar to Fig. 2 and similar parts use similar reference marker to identify.The example embodiment of Fig. 4 has the preparatory code translator 230 of piece, and it is connected to overall line decoder 208 through Block decoder line 231.Overall situation line decoder 208 is connected to memory array through a plurality of lines, though only show a piece line 240 in the example shown, each piece all has a piece line.The piece line is connected to all local line decoders 210,212,214 and 216 jointly.Each local line decoder 210,212,214 and 216 is also driven by the corresponding one group of page code translator line 233,235,237 and 239 from respective page code translator 232,234,236 and 238.Each local line decoder 210,212,214 and 216 also is connected to corresponding sector through a plurality of word lines, only shows a word line for each sector, is labeled as 211,213,215 and 219.
In operation, in order to select particular block, preparatory code translator 230 generals of piece for example convert the appropriate signals on the Block decoder line 231 into from the input of Memory Controller.Overall situation line decoder 208 is selected in the piece lines.In order in particular sector, to select specific webpage, enable the page code translator (in the page code translator 232,234,236 and 238) of relevant sectors and use it for and in selected block, select specific webpage.
Described the example that single sector is selected among Fig. 5, it shows for local line decoder 210 and in piece, selects the page.In some example embodiment, this circuit is configured to allow enable simultaneously a plurality of page code translators.In such example embodiment, in selected block, can carry out in a plurality of sectors and select respective page through enabling a plurality of page code translators.The example that many sectors are selected has been shown among Fig. 6, and it shows selects capable in piece by in line decoder 210 and 214 each.The piece line is selected in the piece in all sectors, and selects in the page (that is word line) in the selected block of page code translator line in each sector.
In this example embodiment, read operation will make one or more page buffer circuits comprise sense data.The content of these page buffer circuits is read separately subsequently.Programming operation will make that the content of one or more page buffer circuits is programmed simultaneously.Typically, this is after the write operation to page buffer, is sequentially write through a plurality of page buffer circuits of this write operation.
Fig. 7 shows the more detailed nuclear framework that is provided by example embodiment, and wherein this example embodiment is similar to Fig. 3 and similar parts use similar reference marker to identify.In Fig. 7, similar with other block diagrams, some parts (for example, column decoder) do not illustrate, not blur the characteristic of example embodiment.In this example, NAND nuclear (this can be entire equipment nuclear framework, plane or memory bank) comprises that the page size of 4 sectors and each sector is 512 bytes.More generally, the page size of each sector is at least 1 byte.In this example, there are 2048 pieces, are designated as 217 jointly.Every is divided into 4 sectors.Overall situation line decoder 208 is connected to all local line decoders 210,212,214 and 216, piece line of each piece jointly through 2048 piece line (not shown)s.Each piece has 32 pages.
Described the example embodiment of the overall line decoder 208 of Fig. 7 among Fig. 8.Overall situation line decoder 208 has the relevant block code translator of each piece, corresponding to the quantity of piece, promptly is designated as 2048 Block decoder of 209 always.Each Block decoder is connected to Block decoder line 231.In this example, Block decoder line 231 comprises line xp, xq, xr and xt, is used to carry Block decoder address signal Xp, Xq, Xr and Xt.Xp, Xq, Xr and Xt decipher line in advance.Xp is corresponding to address A
0-A
2Xq is corresponding to address A
3-A
5Xr is corresponding to address A
6-A
8Xt is corresponding to address A
9-A
10Each Block decoder drives relevant block line (not shown).With by the relevant Block decoder of the piece of the indication of the address signal on the Block decoder line 231 the relevant block line being driven is selection mode, and every other line is non-selected state.
Described the exemplary circuit embodiment of monolithic code translator among Fig. 9.Note,, have the multiple variation of circuit implementing scheme, and such variation is to understand easily for those of ordinary skills for Block decoder.
This circuit have comprise latch output BDLCH_out Block decoder address latch 302; This output BDLCH_out is being reset to 0V when RST_BD is high (being actually short pulse); And be high (it can be a short pulse) as LCHBD; When NAND logic gate 303 receives effectively in advance decoded address signal Xp, Xq, Xr and Xt (Block decoder line), latched.Figure 12 that describes below, 13 and 14 shows detailed time sequence information.
Block decoder has local charge pump 300, and it is the high voltage commutation circuit to read, voltage to be provided during programming and the erase operation.Local charge pump 300 comprises that depletion-mode n channel pass transistor 352, natural n channeling diode connect boost transistor 354, high-breakdown-voltage n raceway groove uncoupling transistor 356, high-breakdown-voltage n raceway groove clamp transistor 358, NAND logic gate 360 and capacitor 362.NAND logic gate 360 has another input terminal that is used to receive the input terminal of latch output BDLCH_out and is used to receive control signal OSC, is used for a terminal of drive capacitor device 362.Transmission transistor 352 is by complement code (the being called HVenb) control of signal HVen.The public terminal of uncoupling transistor 356 and clamp transistor 358 is coupled to high voltage Vhv.
The final output signal BD_out of each Block decoder is connected to all local line decoders jointly, and is for example depicted in figure 9.
The operation of local charge pump 350 will be described now.During read operation, HVenb is in high logic level, and OSC remains on low logic level.Therefore, circuit component 362,354,356 and 358 is inoperative, and lead-out terminal BD_out has reflected the logic level that appears on the BDLCH_out.During the programming operation, HVenb is in low logic level, allows OSC to vibrate between high logic level and low logic level with preset frequency.If latch output BDLCH_out is in high logic level, then capacitor 362 will gather electric charge and discharge the electric charge that is gathered through boost transistor 354 times without number on its other terminal.Uncoupling transistor 356 is isolated boosted voltage on the grid of Vhv and boost transistor 354.Clamp transistor 358 remains on about Vhn+Vth with the voltage level of lead-out terminal BD_out, and wherein Vth is the threshold voltage of clamp transistor 358.Local charge pump 300 shown in Fig. 9 be for can being used to drive signal to an exemplary circuit greater than the voltage level of supply voltage VCC, but the one of ordinary skilled in the art will understand and can use other charge pump circuit with similar or same effect.Below table 1 illustrate read with programming operation during for the exemplary bias condition of local charge pump 300.
Table 1
When Block decoder latch output BDLCH_out is Vcc, HVenb when being 0V and OSC vibration, the output signal BD_out of Block decoder rises to Vhv.
With reference to Figure 10, another example of Block decoder uses piece to select transistor.Vhwl is a high voltage source, and it has various level based on operation.In this example embodiment, the driving force of BD_out is selected transistorized size by piece rather than is confirmed by local charge pump.Therefore, under a fairly large number of situation of local line decoder, this circuit provides stronger driving force in nand memory nuclear.
Figure 11 has described the example of local line decoder.Local line decoder has 2048 sector code translators, always is designated as 500, sector code translator of each piece.What be called as the sector code translator and be because select is the page the sector in, different with the selection page in whole memory arrays.The input of local line decoder is a page code translator line, and it comprises string selection (SS), word line selection signal S0-S31 (this word line selection signal of each word line) and ground connection selection (GS) in the example shown.Word line selection signal S0-S31 is connected to the sector code translator jointly.
With reference now to Figure 12,, its description is used for the exemplary circuit of single sector code translator.Transmission transistor TSS, the TS0 of control drive to TS31 and TGS jointly through the output signal BD_out by relevant Block decoder by common signal SS, S0-S31 and GS with ground connection selection wire GSL to WL31 for string selection wire SSL, word line WL0.Page code translator provides page code translator line, and promptly string selects signal SS, ground connection to select signal GS and public string decoded signal S0-S31.
In operation, for selected, the BD_out of the sector code translator that all are corresponding input is activated.For that piece of each sector, this will comprise a sector code translator.For all non-selected rest block, the BD_out of the sector code translator that all are corresponding input is disabled.For will be to the sector of its executable operations, in this sector, all sector code translators come common control by public page code translator line.Can have one or more will be to the sector of its executable operations.For do not have will be to the sector of its executable operations, all public page code translator lines are inoperative, make that the sector code translator of all common connections is inoperative.For the sector code translator by the BD_out of selection mode and movable the two selection of page code translator line, this sector code translator makes corresponding selected word line (among the WL0-WL31) be selected state, and remaining word line is not selected state.
Table 2 show Block decoder, local line decoder and NAND cell array read, the example set of bias condition between programming and erasing period.Should be appreciated that all numerical value can be based on element characteristics and technology and changed.
Table 2
In this example embodiment, can fill order's sector operation or many sector operations.For read operation, but the parallel page that the fill order sector page reads with 4 sectors of as many as reads.More generally, can the walk abreast maximum quantity of the sector of reading is confirmed by the quantity of the sector in the nand memory nuclear.For programming operation, but the parallel page program of fill order sector page program and 4 sectors of as many as.More generally, but the maximum quantity of the sector of multiple programming confirm by the quantity of the sector in the nand memory nuclear.For wiping, but fill order sector piece is wiped with the parallel block of 4 sectors of as many as and is wiped.More generally, but the maximum quantity of the sector of parallel erase confirm by the quantity of the sector in the nand memory nuclear.
Figure 13 shows the example according to the read operation sequential of some example embodiment.For this example, define in the top table 2 for the voltage bias condition during the reading of this example.All signals in each not selected sector remain 0V.This time sequential routine is based on uses the Block decoder shown in Fig. 9.
Figure 14 shows the example according to the programming operation sequential of some example embodiment.For this example, define in the top table 2 for the voltage bias condition during the programming of this example.All signals in each not selected sector remain 0V.This time sequential routine is based on uses the Block decoder shown in Fig. 9.
Figure 15 shows the example according to the erase operation sequential of some example embodiment.For this example, define the voltage bias condition between erasing period in the top table 2.All signals in the not selected sector remain 0V.This time sequential routine is based on uses the Block decoder shown in Fig. 9.
In Figure 13,14 and 15, Sel_Si is arbitrary " selected " Si input signal (Si={S wherein
0... S
31) write a Chinese character in simplified form.Unsel_Si is arbitrary " not selected " Si input signal (Si={S wherein
0... S
31) write a Chinese character in simplified form.Sel_WLi is arbitrary " selected " word-line signal (WLi={WL wherein
0... WL
31), write a Chinese character in simplified form.Unsel_WLi is arbitrary " not selected " word-line signal (WLi={WL wherein
0... WL
31) abbreviation.
Be appreciated that ought claim here element " connection " perhaps " coupling " to other element, it can be directly to connect or be coupled to other element or have intermediary element.With it differently, claim that when here element " directly connects " perhaps " directly coupling " and to other element, then do not have intermediary element.Other word that is used to describe the interelement relation also explain in a similar manner (that is, " and ... between " to " and directly exist ... between ", " adjacent " to " direct neighbor " etc.).
Can make certain change and modification to described embodiment.Therefore, embodiment discussed above is considered to exemplary and nonrestrictive.
Claims (27)
1. the NAND flash memory of a multistage row decoding is examined.
2. NAND flash memory nuclear according to claim 1 comprises:
The nand memory cell array comprises a plurality of sectors, and each sector has multiple row and multirow;
Overall situation line decoder is used for carrying out first order row decoding for all sectors;
The local line decoder that each sector is corresponding is used for only second level row decoding being carried out in this sector.
3. NAND flash memory nuclear according to claim 2, wherein:
This nand memory cell array comprises a plurality of, and each piece comprises multirow, and every row comprises the storage unit of each sector;
This overall situation line decoder is carried out row decoding and is selected a piece from a plurality of.
4. NAND flash memory according to claim 3 nuclear is configured to carry out with the resolution of the delegation in the sector and reads and programming operation and carry out erase operation with one resolution in the sector.
5. NAND flash memory nuclear according to claim 2, wherein:
A plurality of sectors of this nand memory cell array and local line decoder are placed in the cloth intra-office that the sector of the correspondence of local line decoder and this nand memory cell array replaces.
6. NAND flash memory nuclear according to claim 1 also comprises:
Each sector corresponding page buffer circuits.
7. NAND flash memory nuclear according to claim 1 also comprises: each sector corresponding page code translator.
8. NAND flash memory nuclear according to claim 1 also comprises:
The column decoder that each sector is corresponding.
9. NAND flash memory nuclear according to claim 1 also comprises:
This overall situation line decoder and should this locality line decoder between connection, this connection comprises a plurality of lines, each piece line is connected to each local line decoder jointly.
10. NAND flash memory nuclear according to claim 9 wherein should comprise by overall situation line decoder:
A plurality of Block decoder, each is connected to the Block decoder line jointly, and each Block decoder is connected in a plurality of lines.
11. NAND flash memory nuclear according to claim 10 also comprises:
The preparatory code translator of piece is used for the part of receiver address or address, and on the Block decoder line, produces Block decoder output;
This overall situation line decoder comprises a plurality of Block decoder that are connected to this Block decoder line jointly.
12. NAND flash memory nuclear according to claim 1 also comprises:
For each local line decoder, the connection between this this locality line decoder and this nand memory cell array, this connection comprises a plurality of word lines, each word line should this locality line decoder be connected to the memory cell of the associated row in the corresponding sector.
13. NAND flash memory nuclear according to claim 1 also comprises:
For each sector, be connected to the corresponding page code translator of the local line decoder of this sector through page code translator line.
14. NAND flash memory nuclear according to claim 13, wherein each local line decoder comprises a plurality of sectors code translator, and wherein the sector code translator of given local line decoder is connected to the page code translator line of the page code translator that is used for this sector jointly.
15. NAND flash memory nuclear according to claim 1, wherein a plurality of sectors comprise n sector, and this NAND flash memory nuclear is configured to:
Execution is read and programming operation selected single sector; With
Execution is read and programming operation the parallel of selected a plurality of sectors of all n of as many as sector.
16. NAND flash memory nuclear according to claim 2, wherein:
This NAND flash memory nuclear is configured to carry out reading and programming operation selected single sector through following operation:
Overall situation line decoder is carried out the subclass that first order row decoding is selected multirow;
The corresponding local line decoder of selected single sector is carried out second level row decoding and in the subclass of the multirow that this overall situation line decoder is selected, is selected delegation; With
This NAND flash memory nuclear is configured to through following operation execution the parallel of selected a plurality of sectors of all n of as many as sector read and programming operation:
This overall situation line decoder carry out first order row decoding select multirow subclass and
For each sector of selected a plurality of sectors, the local line decoder of the correspondence of this sector is carried out second level row decoding and in the subclass of the multirow that this overall situation line decoder is selected, is selected delegation.
17. NAND flash memory nuclear according to claim 7 comprises: page code translator line, it is connected to corresponding local line decoder with each page code translator;
Wherein this NAND flash memory nuclear is configured to carry out reading and programming operation selected single sector through following operation:
Overall situation line decoder is carried out the subclass that first order row decoding is selected multirow;
The page code translator receiver address of selected single sector or the part of address, and on page code translator line, produce the output of page code translator;
The local line decoder of the correspondence of selected single sector is carried out second level row decoding according to this page code translator output and in the subclass of the multirow that this overall situation line decoder is selected, is selected delegation;
For read operation, with the content delivery of the selected row of selected sector to the corresponding page buffer circuits;
For programming operation, the content delivery of corresponding page buffer circuits is arrived the selected row of selected sector;
For parallel reading and programming operation carried out in the selected a plurality of sectors of all n of as many as sector, this overall situation line decoder is carried out the subclass that first order row decoding is selected multirow, and for each sectors of selected a plurality of sectors:
The page code translator receiver address of this sector or the part of address, and on page code translator line, produce the output of page code translator;
The local line decoder of the correspondence of this sector is carried out second level row decoding according to this page code translator output and in the subclass of the multirow that this overall situation line decoder is selected, is selected delegation;
For read operation, with the content delivery of selected row to the corresponding page buffer circuits;
For programming operation, the content delivery of corresponding page buffer circuits is arrived the selected row of selected sector.
18. NAND flash memory nuclear according to claim 3 is configured to:
Execution is to the erase operation of the selected block in the selected single sector; With
To selected a plurality of sectors of all n of as many as sector, carry out parallel erase operation to selected block.
19. a NAND flash memory device comprises the described NAND flash memory nuclear of claim 1.
20. a NAND flash memory device comprises:
Peripheral circuit, i/o pads and high pressure generator;
NAND flash memory nuclear comprises:
Comprise that multirow takes advantage of the nand memory cell array of multiple row, this unit is arranged to a plurality of sectors, and each sector comprises the unit of a plurality of said row; This unit is arranged to a plurality of, and each piece comprises the unit of a plurality of said row;
This nand memory cell array is configured to be used for wipe and be configured to resolution with a row in the sector with the resolution of a piece in the sector read and programme.
21. NAND flash memory device according to claim 20, wherein this NAND flash memory nuclear comprises:
Overall situation line decoder is used for carrying out first order row decoding for all sectors;
The local line decoder that each sector is corresponding is used for only second level row decoding being carried out in this sector.
22. the method during a NAND flash memory is examined comprises:
Carry out multistage row decoding.
23. according to the said method of claim 22, be used for NAND flash memory nuclear, this NAND flash memory nuclear comprises the nand memory cell array, this nand memory cell array comprises a plurality of sectors, and each sector has multiple row and multirow, and said method comprises:
Carry out first order row decoding for all sectors;
Carry out second level decoding at least one sector.
24. according to the said method of claim 23, be used for this NAND flash memory nuclear, this NAND flash memory nuclear comprises a plurality of, each piece comprises multirow, and each row comprises the memory cell of each sector, wherein:
Carry out first order row decoding and comprise that carrying out row decoding to select a piece from a plurality of.
25. method according to claim 24 also comprises:
Carry out with the resolution of the delegation in the sector and to read and programming operation;
One resolution with in the sector is carried out erase operation.
26. according to the said method of claim 24, be used for this NAND flash memory nuclear, a plurality of sectors are made up of n sector in this NAND flash memory nuclear, this method also comprises:
For selected single sector, carry out with the resolution of the delegation in the sector and to read and programming operation; With
Resolution execution with delegation in the sector is read and programming operation the parallel of selected a plurality of sectors of all n of as many as sector.
27. method according to claim 24 also comprises:
Through following operation selected single sector execution is read and programming operation:
Carry out first order row decoding and select the subclass of multirow;
Carry out second level row decoding and in the selected subclass of multirow, select delegation; With
Through following operation execution the parallel of selected a plurality of sectors of all n of as many as sector read and programming operation:
This overall situation line decoder carry out first order row decoding select multirow subclass and
For each sector of selected a plurality of sectors, carry out second level row decoding and in the selected subclass of this multirow, select delegation.
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| US15759409P | 2009-03-05 | 2009-03-05 | |
| US61/157594 | 2009-03-05 | ||
| US12/495,089 US8189390B2 (en) | 2009-03-05 | 2009-06-30 | NAND flash architecture with multi-level row decoding |
| US12/495089 | 2009-06-30 | ||
| PCT/CA2010/000260 WO2010099597A1 (en) | 2009-03-05 | 2010-03-03 | Nand flash architecture with multi-level row decoding |
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| CN102341864A true CN102341864A (en) | 2012-02-01 |
| CN102341864B CN102341864B (en) | 2015-02-11 |
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| CN201080009967.6A Active CN102341864B (en) | 2009-03-05 | 2010-03-03 | Nand flash architecture with multi-level row decoding |
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| US (2) | US8189390B2 (en) |
| EP (1) | EP2404299A4 (en) |
| JP (1) | JP2012519347A (en) |
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| TW (1) | TWI443661B (en) |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217751A (en) * | 2013-06-03 | 2014-12-17 | 辉达公司 | Memory |
| CN106486144A (en) * | 2015-08-31 | 2017-03-08 | 旺宏电子股份有限公司 | Memory structure |
| CN107993687A (en) * | 2018-01-12 | 2018-05-04 | 成都信息工程大学 | A kind of memory circuitry |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8416609B2 (en) | 2010-02-15 | 2013-04-09 | Micron Technology, Inc. | Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems |
| US8958244B2 (en) | 2012-10-16 | 2015-02-17 | Conversant Intellectual Property Management Inc. | Split block decoder for a nonvolatile memory device |
| US9704580B2 (en) | 2012-10-22 | 2017-07-11 | Conversant Intellectual Property Management Inc. | Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices |
| US9030879B2 (en) | 2012-11-15 | 2015-05-12 | Conversant Intellectual Property Management Incorporated | Method and system for programming non-volatile memory with junctionless cells |
| US10403766B2 (en) | 2012-12-04 | 2019-09-03 | Conversant Intellectual Property Management Inc. | NAND flash memory with vertical cell stack structure and method for manufacturing same |
| KR102021808B1 (en) | 2012-12-04 | 2019-09-17 | 삼성전자주식회사 | Nonvolatile memory including memory cell array having 3-dimensional structure |
| US9007834B2 (en) | 2013-01-10 | 2015-04-14 | Conversant Intellectual Property Management Inc. | Nonvolatile memory with split substrate select gates and hierarchical bitline configuration |
| US9025382B2 (en) | 2013-03-14 | 2015-05-05 | Conversant Intellectual Property Management Inc. | Lithography-friendly local read circuit for NAND flash memory devices and manufacturing method thereof |
| US9202931B2 (en) | 2013-03-14 | 2015-12-01 | Conversant Intellectual Property Management Inc. | Structure and method for manufacture of memory device with thin silicon body |
| US9214235B2 (en) | 2013-04-16 | 2015-12-15 | Conversant Intellectual Property Management Inc. | U-shaped common-body type cell string |
| KR102302591B1 (en) * | 2015-09-22 | 2021-09-15 | 삼성전자주식회사 | Row Decoder with reduced size and Memory Device having the same |
| US9847133B2 (en) * | 2016-01-19 | 2017-12-19 | Ememory Technology Inc. | Memory array capable of performing byte erase operation |
| US10713136B2 (en) * | 2017-09-22 | 2020-07-14 | Qualcomm Incorporated | Memory repair enablement |
| KR102442337B1 (en) * | 2018-05-14 | 2022-09-13 | 삼성전자주식회사 | Nonvolatile memory device and method of operating the same |
| CN112346646B (en) * | 2019-08-06 | 2023-05-23 | 天津光电通信技术有限公司 | High-speed mass storage and writing, reading and erasing method |
| IT201900021165A1 (en) * | 2019-11-14 | 2021-05-14 | St Microelectronics Srl | NON-VOLATILE MEMORY DEVICE WITH AN ASYMMETRIC LINE DECODER AND WORD LINE SELECTION METHOD |
| KR20230066834A (en) * | 2021-11-08 | 2023-05-16 | 삼성전자주식회사 | Nonvolatile memory and storage device including the same |
| US12198753B2 (en) | 2021-11-10 | 2025-01-14 | Samsung Electronics Co., Ltd. | Memory device having row decoder array architecture |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020186590A1 (en) * | 2001-06-11 | 2002-12-12 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device having hierarchical sector structure |
| US7035162B2 (en) * | 2003-07-12 | 2006-04-25 | Samsung Electronics Co., Ltd. | Memory devices including global row decoders and operating methods thereof |
Family Cites Families (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960000616B1 (en) | 1993-01-13 | 1996-01-10 | 삼성전자주식회사 | Nonvolatile Semiconductor Memory Device |
| US5621690A (en) * | 1995-04-28 | 1997-04-15 | Intel Corporation | Nonvolatile memory blocking architecture and redundancy |
| DE69516883T2 (en) * | 1995-12-29 | 2000-10-05 | Stmicroelectronics S.R.L., Agrate Brianza | Erase procedure for a non-volatile memory |
| US5896340A (en) | 1997-07-07 | 1999-04-20 | Invox Technology | Multiple array architecture for analog or multi-bit-cell memory |
| JP3905979B2 (en) * | 1998-06-03 | 2007-04-18 | 株式会社東芝 | Nonvolatile semiconductor memory |
| JP3999900B2 (en) * | 1998-09-10 | 2007-10-31 | 株式会社東芝 | Nonvolatile semiconductor memory |
| EP1028433B1 (en) | 1999-02-10 | 2004-04-28 | SGS-THOMSON MICROELECTRONICS s.r.l. | Nonvolatile memory and reading method therefor |
| JP3920501B2 (en) * | 1999-04-02 | 2007-05-30 | 株式会社東芝 | Nonvolatile semiconductor memory device and data erase control method thereof |
| EP1047077A1 (en) | 1999-04-21 | 2000-10-25 | STMicroelectronics S.r.l. | Nonvolatile memory device with double hierarchical decoding |
| US6088287A (en) * | 1999-08-23 | 2000-07-11 | Advanced Micro Devices, Inc. | Flash memory architecture employing three layer metal interconnect for word line decoding |
| US6662263B1 (en) * | 2000-03-03 | 2003-12-09 | Multi Level Memory Technology | Sectorless flash memory architecture |
| US6950336B2 (en) * | 2000-05-03 | 2005-09-27 | Emosyn America, Inc. | Method and apparatus for emulating an electrically erasable programmable read only memory (EEPROM) using non-volatile floating gate memory cells |
| TW540053B (en) * | 2000-07-13 | 2003-07-01 | Samsung Electronics Co Ltd | Row decoder of a NOR-type flash memory device |
| DE60140039D1 (en) * | 2001-02-05 | 2009-11-12 | St Microelectronics Srl | Deletion procedure for a flash memory |
| US6704241B1 (en) | 2002-09-06 | 2004-03-09 | Winbond Electronics Corporation | Memory architecture with vertical and horizontal row decoding |
| US7009910B2 (en) | 2001-08-23 | 2006-03-07 | Winbond Electronics Corporation | Semiconductor memory having a flexible dual-bank architecture with improved row decoding |
| KR100463197B1 (en) * | 2001-12-24 | 2004-12-23 | 삼성전자주식회사 | Nand-type flash memory device with multi-page program, multi-page read, and multi-block erase operations |
| EP1327992B1 (en) * | 2002-01-11 | 2005-03-30 | STMicroelectronics S.r.l. | Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more different sectors |
| KR100481857B1 (en) | 2002-08-14 | 2005-04-11 | 삼성전자주식회사 | Flash memory device having decoder to reduce chip area and to implement independent operation of each bank |
| JP2005302139A (en) * | 2004-04-09 | 2005-10-27 | Nec Electronics Corp | Semiconductor memory device |
| JP4698583B2 (en) | 2004-05-12 | 2011-06-08 | スパンション エルエルシー | Semiconductor device and control method thereof |
| JP4135680B2 (en) * | 2004-05-31 | 2008-08-20 | ソニー株式会社 | Semiconductor memory device and signal processing system |
| JP2006331501A (en) | 2005-05-24 | 2006-12-07 | Toshiba Corp | Semiconductor memory apparatus |
| KR100669349B1 (en) * | 2005-12-02 | 2007-01-16 | 삼성전자주식회사 | Flash memory device and its reading method |
| KR100830575B1 (en) * | 2006-09-26 | 2008-05-21 | 삼성전자주식회사 | Flash memory device and its multi-block erase method |
| JP2008108382A (en) * | 2006-10-26 | 2008-05-08 | Toshiba Corp | Nonvolatile semiconductor memory device |
| US7577059B2 (en) * | 2007-02-27 | 2009-08-18 | Mosaid Technologies Incorporated | Decoding control with address transition detection in page erase function |
| KR101519061B1 (en) | 2008-01-21 | 2015-05-11 | 삼성전자주식회사 | Flash memory device having row decoder sharing single high voltage level shift |
-
2009
- 2009-06-30 US US12/495,089 patent/US8189390B2/en active Active
-
2010
- 2010-03-03 CA CA2754062A patent/CA2754062A1/en not_active Abandoned
- 2010-03-03 CN CN201080009967.6A patent/CN102341864B/en active Active
- 2010-03-03 JP JP2011552285A patent/JP2012519347A/en active Pending
- 2010-03-03 KR KR20117023334A patent/KR20110132584A/en not_active Application Discontinuation
- 2010-03-03 WO PCT/CA2010/000260 patent/WO2010099597A1/en active Application Filing
- 2010-03-03 EP EP10748249A patent/EP2404299A4/en not_active Withdrawn
- 2010-03-03 DE DE112010000955T patent/DE112010000955T5/en not_active Withdrawn
- 2010-03-04 TW TW99106268A patent/TWI443661B/en active
-
2012
- 2012-05-09 US US13/467,491 patent/US8854884B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020186590A1 (en) * | 2001-06-11 | 2002-12-12 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device having hierarchical sector structure |
| US7035162B2 (en) * | 2003-07-12 | 2006-04-25 | Samsung Electronics Co., Ltd. | Memory devices including global row decoders and operating methods thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217751A (en) * | 2013-06-03 | 2014-12-17 | 辉达公司 | Memory |
| CN106486144A (en) * | 2015-08-31 | 2017-03-08 | 旺宏电子股份有限公司 | Memory structure |
| CN106486144B (en) * | 2015-08-31 | 2019-05-14 | 旺宏电子股份有限公司 | memory structure |
| CN107993687A (en) * | 2018-01-12 | 2018-05-04 | 成都信息工程大学 | A kind of memory circuitry |
| CN107993687B (en) * | 2018-01-12 | 2023-08-11 | 成都信息工程大学 | a memory circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201106358A (en) | 2011-02-16 |
| KR20110132584A (en) | 2011-12-08 |
| WO2010099597A1 (en) | 2010-09-10 |
| US20120218829A1 (en) | 2012-08-30 |
| DE112010000955T5 (en) | 2012-07-19 |
| TWI443661B (en) | 2014-07-01 |
| CN102341864B (en) | 2015-02-11 |
| US8189390B2 (en) | 2012-05-29 |
| JP2012519347A (en) | 2012-08-23 |
| CA2754062A1 (en) | 2010-09-10 |
| EP2404299A1 (en) | 2012-01-11 |
| US20100226179A1 (en) | 2010-09-09 |
| EP2404299A4 (en) | 2013-03-27 |
| US8854884B2 (en) | 2014-10-07 |
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