CN112346646B

CN112346646B - High-speed mass storage and writing, reading and erasing method

Info

Publication number: CN112346646B
Application number: CN201910720242.0A
Authority: CN
Inventors: 李羚梅; 刘博�; 尚进; 云天嵩; 蒋航; 苏晓旭; 李鑫儒; 何海星; 赵保磊
Original assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Current assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Priority date: 2019-08-06
Filing date: 2019-08-06
Publication date: 2023-05-23
Anticipated expiration: 2039-08-06
Also published as: CN112346646A

Abstract

The invention provides a high-speed mass storage and a writing, reading and erasing method, the high-speed mass storage comprises: 8 rows and 8 columns NAND FLASH of memory chips; 8 groups of control lines, each group of control lines controlling 8 pieces NAND FLASH of memory chips in each column; 32 groups of data lines, wherein each group of data lines is respectively and electrically connected with each two NAND FLASH storage chips in the transverse direction and is used for realizing reading and writing; and the FPGA is electrically connected with the 8 groups of control lines and the 32 groups of data lines and is used for performing read-write control on the NAND FLASH memory chip according to time sequence operation. A storage array is formed by adopting 8X8 total 64 pieces NAND FLASH, the storage capacity of each FLASH is 128Gb, and the total storage capacity is 1TB. And the high-speed read-write function is realized by utilizing a time sequence and multiple data line multiplexing mode, and the speed is not less than 819.2MB/S.

Description

High-speed mass storage and writing, reading and erasing method

Technical Field

The invention belongs to the technical field of data storage, and particularly relates to a high-speed large-capacity memory and writing, reading and erasing methods thereof.

Background

The development of technology in the electronic industry has been widely used in the fields of wireless communication, speech recognition, image processing, radar sonar, etc. Under the background, the high-speed data storage technology is generated, the upper computer mainly controls the operations of disk-dropping, erasing and reading of the high-speed storage board in real time under the current technical background, the high-speed storage generally adopts the mode of externally hanging an SATA3.0 hard disk, the theoretical highest speed of the SATA3.0 can reach 6Gb/s, and the SATA driving program is relatively complex. Accordingly, a great burden is caused to the operation of the upper computer.

Disclosure of Invention

The embodiment of the invention provides a high-speed high-capacity memory and a writing, reading and erasing method, which are used for at least solving one of the technical problems.

In a first aspect, an embodiment of the present invention provides a high-speed mass storage device, including:

8 rows and 8 columns NAND FLASH of memory chips;

8 groups of control lines, each group of control lines controlling 8 pieces NAND FLASH of memory chips in each column;

32 groups of data lines, wherein each group of data lines is respectively and electrically connected with each two NAND FLASH storage chips in the transverse direction and is used for realizing reading and writing;

and the FPGA is electrically connected with the 8 groups of control lines and the 32 groups of data lines and is used for performing read-write control on the NAND FLASH memory chip according to time sequence operation.

Further, the memory further includes:

CE#, CLE, W/R, ALE, and WE# control lines.

And when the matching is consistent, running the program.

In a second aspect, an embodiment of the present invention further provides a data writing method using the high-speed mass storage device, including:

writing data to the NAND FLASH chips of the first and second rows sequentially from the first to eighth columns using the common data line;

writing data to the NAND FLASH chips of the third and fourth rows sequentially from the first to eighth columns using the common data line;

writing data to the NAND FLASH chips of the fifth and sixth rows sequentially from the first to eighth columns using the common data line;

data is written to the NAND FLASH chips of the seventh and eighth rows sequentially from the first to eighth columns using the common data line.

Further, before writing data to the NAND FLASH chips of the first and second rows sequentially from the first to eighth columns using the common data line, it further includes:

obtaining a bad block table of the NAND FLASH chip array;

and executing the writing operation according to the bad block table.

Further, the reducing the clock frequency includes:

reducing the clock frequency to 40Mhz using a phase locked loop;

in a third aspect, an embodiment of the present invention further provides a data reading method using the foregoing telling mass storage device, including:

sequentially reading data from the NAND FLASH chips of the first and second rows sequentially from the first to eighth columns using the common data line;

sequentially reading data from the NAND FLASH chips of the third and fourth rows in the order of the first to eighth columns using the common data line;

sequentially reading data from the NAND FLASH chips of the fifth and sixth rows in the order of the first to eighth columns using the common data line;

data is read from the NAND FLASH chips of the seventh and eighth rows sequentially from the first to eighth columns using the common data line.

In a fourth aspect, an embodiment of the present invention further provides a data erasing method using the foregoing telling mass storage device, including:

erasing data of all NAND FLASH chips of the first and second rows by using a common data line;

erasing data of all NAND FLASH chips of the third row and the fourth row by using a common data line;

erasing data of all NAND FLASH chips of the fifth row and the sixth row by using a common data line;

the data of all NAND FLASH chips of the seventh and eighth rows are erased by using the common data line.

The embodiment of the invention provides a high-speed high-capacity memory and a writing, reading and erasing method, wherein the high-speed high-capacity memory comprises: 8 rows and 8 columns NAND FLASH of memory chips; 8 groups of control lines, each group of control lines controlling 8 pieces NAND FLASH of memory chips in each column; 32 groups of data lines, wherein each group of data lines is respectively and electrically connected with each two NAND FLASH storage chips in the transverse direction and is used for realizing reading and writing; and the FPGA is electrically connected with the 8 groups of control lines and the 32 groups of data lines and is used for performing read-write control on the NAND FLASH memory chip according to time sequence operation. A storage array is formed by adopting 8X8 total 64 pieces NAND FLASH, the storage capacity of each FLASH is 128Gb, and the total storage capacity is 1TB. And the high-speed read-write function is realized by utilizing a time sequence and multiple data line multiplexing mode, and the speed is not less than 819.2MB/S.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a high-speed mass storage provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a write timing of a high-speed mass storage according to an embodiment of the present invention;

FIG. 3 is a read timing diagram of a high-speed mass storage according to an embodiment of the present invention;

FIG. 4 is a flowchart of the FLASH chip in the high-speed mass memory according to an embodiment of the present invention;

FIG. 5a is a diagram showing a first row of results of a Flash array data read of a high-speed mass memory according to an embodiment of the present invention;

FIG. 5b is a diagram illustrating a second row of results of the Flash array data read of the high-speed mass storage device according to the embodiment of the present invention;

FIG. 5c is a diagram illustrating a third row of results of Flash array data reading of the high-speed mass storage device according to the embodiment of the present invention;

fig. 5d is a schematic diagram of a fourth row of results of Flash array data reading of the high-speed mass storage according to the embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Fig. 1 is a schematic structural diagram of a high-speed mass storage provided in an embodiment of the present invention, referring to fig. 1, the high-speed mass storage includes: 8 rows and 8 columns NAND FLASH of memory chips; 8 groups of control lines, each group of control lines controlling 8 pieces NAND FLASH of memory chips in each column; 32 groups of data lines, wherein each group of data lines is respectively and electrically connected with each two NAND FLASH storage chips in the transverse direction and is used for realizing reading and writing; and the FPGA is electrically connected with the 8 groups of control lines and the 32 groups of data lines and is used for performing read-write control on the NAND FLASH memory chip according to time sequence operation.

In the figure, D0-D7 are data lines for reading and writing data, CE#, CLE, W/R, ALE and WE# are control lines, and the FLASH can be controlled by time sequence operation.

Specifically, the hardware is specifically connected as follows: 8 FLASH are arranged in each row transversely, wherein 1 group of data lines (D0-D7) are shared by every 2 FLASH, 8 FLASH are arranged in each column longitudinally, and one group of control lines are shared by 8 FLASH in each column. All the data lines and the control lines are connected with the FPGA, and the time sequence operation is carried out on the FLASH through the FPGA. For each column of 8 FLASH chips, each FLASH chip has 8bit data lines (D0-D7), if each column of 8 FLASH chips is operated on, an 8x8 = 64bit data bus can be formed, and if each bus rate is 128Mb/s, the total rate is 128x64 = 8192Mb/s = 1GB/s. The storage of total 1TB data at a 1GB/s rate can be realized by sequentially operating 8 columns of FLASH.

During normal reading and writing, each reading and writing time slot only controls one column, and during writing operation, each time slot writes one column of FLASH, 8 pages in total, and 8×8KB=64 KB in total. Fig. 2 is a schematic diagram of a write timing of a high-speed mass storage according to an embodiment of the present invention. Referring to fig. 2, with 64M as the system clock, 65us is required for each writing of 8 pages (one column), where tprog is 300us to 500us, and the total of 8 columns is 65×8=520 us, which is greater than the tprog maximum, so that the first column has been finalized when the write command has been sent to the eighth column, and the write command has been sent to the first column. By a means ofSince 520us is required to complete 8×8 page=0.5mb with program, 1ms can complete 1MB with program, i.e., 1s can program1GB data, satisfying a write rate not less than 819.2MB/s. FIG. 3 is a read timing diagram of a high speed mass storage device according to an embodiment of the present invention, see FIG. 3, wherein t _R The maximum value is 35us, which makes that 65+35=100 us is needed at most for reading 8 pages (one column), and after fifo conversion clock domains are added, 65us more time is needed for reading fifo, and 165us is needed. 8 columns total 165×8=1320 us, so reading 8×8 page=0.5 MB requires 1320us, i.e. 1s can read 380M data at minimum.

As can be seen from the data and the figures, the high-speed high-capacity memory provided by the embodiment of the invention can realize high-speed read-write performance. Specifically, the workflow of each NAND FLASH chip is still according to the original workflow, and fig. 4 is a workflow diagram of a FLASH chip in the high-speed mass storage according to the embodiment of the present invention.

The high-speed high-capacity memory provided by the embodiment of the invention has a total available memory capacity of 1TB. And the high-speed read-write function is realized by utilizing a time sequence and multiple data line multiplexing mode, and the speed is not less than 819.2MB/S. The purposes of mass storage and high-speed reading and writing are realized.

The result of reading 8 columns of pages, respectively, given the written data values is shown in fig. 5a to 5 d: FIG. 5a is a diagram showing a first row of results of a Flash array data read of a high-speed mass memory according to an embodiment of the present invention; FIG. 5b is a diagram illustrating a second row of results of the Flash array data read of the high-speed mass storage device according to the embodiment of the present invention; FIG. 5c is a diagram illustrating a third row of results of Flash array data reading of the high-speed mass storage device according to the embodiment of the present invention; fig. 5d is a schematic diagram of a fourth row of results of Flash array data reading of the high-speed mass storage according to the embodiment of the present invention. If err_flag is FFFF, 16 paths of dout data are proved to have no error code, and the error code is proved to be free through multiple tests. Can realize the 1Gb/s disc-dropping speed, has low error rate, clear structure and low cost

Correspondingly, the invention also provides a data writing method of the high-speed high-capacity memory, which comprises the following steps:

The write operation is divided into 4 phases in total:

1) LUN1 cnt_wr_stage=1 for T1, T2

2) LUN1 cnt_wr_stage=2 for T3, T4

3) LUN2 cnt_wr_stage=3 for T1, T2

4) LUN2 cnt_wr_stage=4 for T3, T4

The detailed workflow is as follows: (assuming no bad blocks then 128 pages x 4096 block=524288)

LUN1 in T1, T2 is written, sequentially from the first column to the eighth column, cnt_wr1=1-524288;

LUN1 in T3, T4 is written, sequentially from the first column to the eighth column, cnt_wr2=1-524288;

LUN1 in T3, T4 is written, sequentially from the first column to the eighth column, cnt_wr2=524288;

LUN2 in T1, T2 is written, sequentially from the first column to the eighth column, cnt_wr3=1-524288;

LUN2 in T3, T4 is written, sequentially from the first column to the eighth column, cnt_wr4=1-524288;

the write addresses of each column are stored in addr_wr1 through addr_wr8 in an addr_message module, respectively, updated every time 1page is written, and bad blocks are skipped when they are encountered. When the LUN is full, the address is cleared when a transition phase, i.e., cnt_wr_stage, is needed.

The values of cnt_wr_1 to cnt_wr_4 are provided for the upper computer, and the residual space of the FLASH array can be calculated through simple operation.

When the FLASH array is full, the flash_full_flag is pulled up to prompt that the hard disk is full.

In practice, there may be a bad block in the NAND FLASH chip, and when writing data, the bad block in the NAND FLASH chip should be detected and the position of the bad block recorded.

By way of example, the following may be employed:

1 reads bad blocks in LUN1 in the first column T1, T2 and performs OR operation to obtain a bad block table 1

The Die/LUN is the basic unit that receives and executes FLASH commands. Different LUNs may receive and execute different commands at the same time.

8 reading bad blocks in LUN1 in the eighth column T1, T2, and performing OR operation to obtain a bad block table 8

9 reading bad blocks in LUN1 in the first column T3, T4, and performing OR operation to obtain a bad block table 9

16 to read the bad blocks in LUN1 in the eighth column T3, T4, and perform OR operation to obtain a bad block table 16

17 reads bad blocks in LUN2 in the first column T1, T2 and performs OR operation to obtain a bad block table 17

24 to read the bad blocks in LUN2 in the eighth column T1, T2, and OR to obtain a bad block table 24

25 to read the bad blocks in LUN2 in the first column T3, T4 and perform OR operation to obtain a bad block table 25

32 reads bad blocks in LUN2 in eighth columns T3, T4 and performs OR operation to obtain bad block table 32

The timing control is mainly completed by a bad block read completion flag err_table_en_sum, a start read bad block enable en_err_message and a counter cnt_err (1 to 32). The read bad blocks are stored in err_1.Vhd to err_32.Vhd, respectively.

The first debugging is to convert the bad block table err_table (0 to 4095), i is more than or equal to 1 and less than or equal to 32 into serial output, store the result, import Matlab, store into err_1.vhd-err_32.vhd after being processed by Matlab, and import into program as library function. And the en_err_message of the top layer is set to 0, then the bad block table is fixed, and the bad block is not read any more in each work.

The judging basis of the bad blocks is as follows: if a block is a bad block, all data of the first page of the block is x '00', not x 'FF', but some data may not be x '00', so that the standard judgment method is to perform AND operation on the 4096 data read, and if the result is x '00', the block is a bad block.

Correspondingly, the invention also provides a data reading method of the high-speed high-capacity memory, which comprises the following steps:

Specifically, similar to the above writing manner, it can be specifically realized by the following manner:

1 read LUN1 in T1, T2, cnt_rd_1=1 from the first column to the eighth column in order

524288 reads LUN1 in T1, T2, sequentially from first column to eighth column, cnt_rd_1=524288

1 read LUN1 in T3, T4, cnt_rd_2=1 from the first column to the eighth column in order

524288 reads LUN1 in T3, T4, sequentially from first column to eighth column, cnt_rd_2=524288

1 read LUN2 in T1, T2, cnt_rd_3=1 from first column to eighth column in order

524288 reads LUN2 in T1, T2, cnt_rd_3=524288, sequentially from the first column to the eighth column

1 read LUN2 in T3, T4, cnt_rd_4=1 from the first column to the eighth column in order

524288 reads LUN2 in T3, T4, sequentially from first column to eighth column, cnt_rd_4=524288

The read addresses of each column are stored in addr_message modules addr_rd_1 to addr_rd_8 respectively, updated every time 1page is read, and skipped when a bad block is encountered.

When cnt_rd_stage < cnt_wr_stage and cnt_rd_i=cnt_wr_i, a read phase is required to be converted, i.e., cnt_rd_stage=cnt_rd_stage+1, at which time the read address is cleared.

When cnt_rd_stage=cnt_wr_stage and cnt_rd_i=cnt_wr_i, it is verified that the read is completed, the read_complete_flag signal is pulled high, and when cnt_rd_detail=8 and rd_mode= '1', it is pulled high, and at other times, 0 is set, if start_write write enable is pulled high, it is verified that there is a new data write, it will also set read_complete_flag to 0.

Correspondingly, the embodiment of the invention also provides a data erasing method of the high-speed high-capacity memory, which comprises the following steps:

Specifically, the method can be realized by the following steps:

unlike read and write, the formatting phase no longer operates on each column separately, but 8 columns are erased together, the detailed workflow is as follows (4096 blocks per LUN):

1 erase LUN1 in T1, T2, eight columns operate together, cnt_era_1=1

4096 erases LUN1 in T1, T2, with eight columns operating together, cnt_era_1=4096

1 erase LUN1 in T3, T4, eight columns operate together, cnt_era_2=1

4096 erases LUN1 in T3, T4, with eight columns operating together, cnt_era_2=4096

1 erase LUN2 in T1, T2, eight columns operate together, cnt_era_3=1

4096 erases LUN2 in T1, T2, eight columns operate together, cnt_era_3=4096

1 erase LUN2 in T3, T4, eight columns operate together, cnt_era_4=1

4096 erases LUN2 in T3, T4, eight columns operate together, cnt_era_4=4096

The read addresses of eight columns are stored in an addr_era in an addr_message module, the erase addresses are updated every time a block is erased, and the erase_complete_flag is enabled to be pulled high after formatting is completed.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A data writing method of a high-speed mass storage, the high-speed mass storage comprising:

8 rows and 8 columns NAND FLASH of memory chips;

the FPGA is electrically connected with the 8 groups of control lines and the 32 groups of data lines and is used for performing read-write control on the NAND FLASH memory chip according to time sequence operation;

characterized by comprising the following steps:

obtaining a bad block table of the NAND FLASH chip array;

executing writing operation according to the bad block table;

reducing clock frequency to facilitate reading the code of the FPGA;

writing data to the NAND FLASH chips of the seventh and eighth rows sequentially from the first to eighth columns using the common data line;

the obtaining the bad block table of the NAND FLASH chip array includes:

sequentially reading bad blocks in the first row, the second row, the third row and the fourth row of the LUN1 of the first column to the eighth column, and performing OR operation to obtain bad block tables 1-8;

sequentially reading bad blocks in fifth and sixth rows of the first to eighth columns and seventh and eighth rows of LUNs 1, and performing OR operation to obtain bad block tables 9-16;

sequentially reading bad blocks in the first row, the second row, the third row and the fourth row of the first to eighth columns of LUNs 2, and performing OR operation to obtain bad block tables 17-24;

sequentially reading bad blocks in fifth and sixth rows of the first to eighth columns and seventh and eighth rows of LUNs 1, and performing OR operation to obtain bad block tables 25-32;

by ANDed the read 4096 data, if the result is x '00', the block is judged to be bad.

2. The method according to claim 1, characterized in that: the high-speed large capacity further includes:

CE#, CLE, W/R, ALE, and WE# control lines.

3. The method as recited in claim 1, further comprising:

4. The method as recited in claim 1, further comprising: erasing data of all NAND FLASH chips of the first and second rows by using a common data line;

5. The method according to claim 4, wherein the method further comprises:

after the data of each block NAND FLASH chip is erased, the erase address is updated.

6. The method of claim 5, wherein the method further comprises:

after the data erasure of all NAND FLASH chips is completed, the erasure completion flag is raised.