CN102339835A - Semiconductor component, electroluminescent component and manufacturing method thereof - Google Patents

Abstract

A semiconductor component is arranged on a substrate. The semiconductor component comprises a first channel layer, a patterned doped layer, a grid dielectric layer, a conductive grid, a second channel layer, a first electrode, a second electrode, a third electrode and a fourth electrode. The first channel layer is located on the substrate of the first area. The patterned doped layer comprises a doped grid electrode positioned on the substrate of the second region, and two contact electrodes respectively connected with two sides of the first channel layer. The gate dielectric layer covers the first channel layer and the patterned doped layer. The conductive gate is on the gate dielectric layer in the first region. The second channel layer is located on the gate dielectric layer of the second region. The first electrode and the second electrode are respectively electrically connected with each contact electrode. The third electrode and the fourth electrode are respectively and electrically connected with two sides of the second channel layer.

Description

Semiconductor component, electroluminescence component and manufacturing method thereof

【Technical field】

The present invention relates to a semiconductor component, an electroluminescence component and a manufacturing method thereof, in particular to a method of using the same patterned doped layer to define a contact electrode of a thin film transistor component and a doped gate of another thin film transistor component Semiconductor components and electroluminescence components and manufacturing methods thereof.

【Background technique】

Compared with amorphous silicon (amorphous silicon) thin film transistors, the polysilicon material of polysilicon (poly silicon) thin film transistors has better electrical performance due to the characteristic of high electrical mobility. With the continuous improvement of low temperature polysilicon (LTPS) process technology, some major problems such as poor uniformity of large-area thin films have been gradually improved. Therefore, the current low-temperature polysilicon process is also developing towards the application of larger-sized substrates. However, in the known low-temperature polysilicon process, the ion implantation process is generally used to form the doped layer to reduce the contact resistance in the thin film transistor, and the ion implantation machine used for the ion implantation process requires In order to introduce large-size substrate manufacturing process, in addition to many technical problems to be overcome, machine manufacturing cost is another big problem. Therefore, how to form a low-resistance doped layer in other ways is also one of the current development directions in the industry.

【Content of invention】

One of the objectives of the present invention is to provide a semiconductor component, an electroluminescent component and a manufacturing method thereof, so as to solve the problems faced by the prior art.

A preferred embodiment of the present invention provides a semiconductor component disposed on a substrate, and the substrate includes a first region and a second region. The semiconductor component includes a first channel layer, a patterned doped layer, a gate dielectric layer, a conductive gate, a second channel layer, a first electrode and a second electrode, and a third electrode with a fourth electrode. The first channel layer is located on the substrate in the first region. The patterned doped layer includes a doped gate and two contact electrodes. The doped gate is located on the substrate in the second region, and the contact electrodes are respectively connected to two sides of the first channel layer. The gate dielectric layer covers the first channel layer and the patterned doped layer. A conductive gate is located on the gate dielectric layer in the first region. The second channel layer is located on the gate dielectric layer in the second region. The first electrode and the second electrode are respectively electrically connected to each contact electrode. The third electrode and the fourth electrode are respectively electrically connected to two sides of the second channel layer.

Another preferred embodiment of the present invention provides a method for manufacturing a semiconductor device, including the following steps. A substrate is provided, and the substrate includes a first area and a second area. A first channel layer is formed on the substrate in the first region. A patterned doped layer is formed on the substrate. The patterned doped layer includes two contact electrodes connecting the two sides of the first channel layer in the first region, and a doped gate located on the substrate in the second region. A gate dielectric layer is formed on the substrate to cover the first channel layer, the contact electrode and the doped gate. A conductive gate is formed on the gate dielectric layer in the first region. A second channel layer is formed on the gate dielectric layer in the second region. A first electrode and a second electrode are formed in the first region, and are respectively electrically connected with each contact electrode. A third electrode and a fourth electrode are formed in the second region, and are respectively electrically connected to two sides of the second channel layer.

Another preferred embodiment of the present invention provides an electroluminescence component disposed on a substrate, and the substrate includes a first region and a second region. The electroluminescent component includes a first channel layer, a patterned doped layer, a gate dielectric layer, a conductive gate, a second channel layer, a first electrode and a second electrode, a third An electrode, a fourth electrode, and a light-emitting component. The first channel layer is located on the substrate in the first region. The patterned doped layer includes a doped gate and two contact electrodes. The doped gate is located on the substrate in the second region, and the contact electrodes are respectively connected to two sides of the first channel layer. The gate dielectric layer covers the first channel layer and the patterned doped layer. A conductive gate is located on the gate dielectric layer in the first region. The second channel layer is located on the gate dielectric layer in the second region. The first electrode and the second electrode are respectively electrically connected to each contact electrode. The third electrode and the fourth electrode are respectively electrically connected to two sides of the second channel layer. The light emitting component is electrically connected with the first electrode.

The semiconductor component of the present invention uses a non-ion implantation process to form a contact electrode and a doped gate, which can simplify the process. In addition, the annealing process can effectively reduce the resistance of the contact electrode and the doped gate, thereby improving the electrical performance of the semiconductor device. The semiconductor component of the electroluminescence component of the present invention also has contact electrodes formed by non-ion implantation process, and can be applied to manufacture large-sized display panels.

【Description of drawings】

FIG. 1 to FIG. 4 are schematic diagrams illustrating a manufacturing method of a semiconductor device according to a first preferred embodiment of the present invention.

FIG. 5 is a schematic top view of an electroluminescent device according to a second preferred embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of an electroluminescent device according to a second preferred embodiment of the present invention.

FIG. 7 shows the circuit structure diagram of the electroluminescent device according to the second preferred embodiment of the present invention.

FIG. 8 is a schematic diagram of a semiconductor device according to a third preferred embodiment of the present invention.

FIG. 9 is a schematic diagram of a semiconductor device according to a fourth preferred embodiment of the present invention.

FIG. 10 is a schematic diagram of a semiconductor device according to a fifth preferred embodiment of the present invention.

FIG. 11 is a schematic diagram of a storage capacitor structure of an electroluminescent device according to a sixth preferred embodiment of the present invention.

FIG. 12 is a schematic diagram of a storage capacitor structure of an electroluminescent device according to a seventh preferred embodiment of the present invention.

[Description of main component symbols]

10 Substrate 101 The first area

102 The second area 12 The first channel layer

14 patterned doped layer 141 contact electrode

142 doped gate 16 gate dielectric layer

18 conductive grid 20 second channel layer

22 interlayer dielectric layer 231 first contact hole

232 Second contact hole 233 Third contact hole

234 fourth contact hole 235 fifth contact hole

236 sixth contact hole 237 contact hole

241 first electrode 242 second electrode

243 The third electrode 244 The fourth electrode

245 connecting electrodes 30 semiconductor components

301 The first thin film transistor component 302 The second thin film transistor component

40 Electroluminescent component 41 The first protective layer

42 light-emitting components 421 anode electrode

422 light-emitting layer 423 cathode electrode

43 Second protective layer 50 Semiconductor components

501 The first thin film transistor component 502 The second thin film transistor component

70 Semiconductor Components 701 The First Thin Film Transistor Components

702 second thin film transistor components 80 semiconductor components

802 The second thin film transistor component 801 The first thin film transistor component

90 Semiconductor Components 901 First Thin Film Transistor Components

902 second thin film transistor assembly 143 storage electrode

Cst1 first storage capacitor Cst2 second storage capacitor

PL Power Cord SL Scanning Line

DL data line

【Detailed ways】

In order to enable those who are familiar with the technical field of the present invention to further understand the present invention, the preferred embodiments of the present invention are listed below, together with the attached drawings, to describe in detail the composition of the present invention and the desired effects .

Please refer to Figure 1 to Figure 4. FIG. 1 to FIG. 4 are schematic diagrams illustrating a manufacturing method of a semiconductor device according to a first preferred embodiment of the present invention. As shown in FIG. 1 , firstly, a substrate 10 is provided. The substrate 10 can be a transparent substrate such as a glass substrate, a plastic substrate or a quartz substrate, but not limited thereto. In addition, the substrate 10 includes a first region 101 and a second region 102 . The first region 101 is used for disposing a first thin film transistor device, and the second region 102 is used for disposing a second thin film transistor device. Next, a first channel layer 12 is formed on the substrate 10 in the first region 101 . In this embodiment, the first channel layer 12 can be an amorphous silicon semiconductor layer, and an annealing process such as a laser treatment process can be used to modify the first channel layer 12 from an amorphous silicon semiconductor layer to a polysilicon semiconductor layer. layer. The material of the first channel layer 12 is not limited to the above materials, but can also be other various types of semiconductor materials.

As shown in FIG. 2 , a patterned doped layer 14 is then formed on the substrate 10 . The patterned doped layer 14 includes two contact electrodes 141 connected to two sides of the first channel layer 12 in the first region 101 , and a doped gate 142 located on the substrate 10 in the second region 102 . The contact electrode 141 is used as the ohmic contact layer of the first thin film transistor component to reduce the contact resistance between the first channel layer 12 and the subsequently formed electrode; the doped gate 142 is used as the gate of the second thin film transistor component . In this embodiment, the step of forming the patterned doped layer 14 includes a non-implant process, so it can be fabricated on a large-size substrate without being limited by the size of the substrate. For example, the non-ion implantation process may include performing a chemical vapor deposition process, a physical vapor deposition (physical vapor deposition) process, or a coating (spin-on) process to form a semiconductor layer (not shown), and during the process Dopants are mixed together to form a doped semiconductor layer (not shown). Afterwards, a patterning process such as a lithography and etching process is used to form the patterned doped layer 14 . In addition, in this embodiment, the patterned doped layer 14 may include a P-type patterned doped layer, so the dopant may be, for example, boron or a boron-containing compound, but not limited thereto. Furthermore, after forming the patterned doped layer 14 or before the doped semiconductor layer is not patterned, an annealing process, such as a laser treatment process, may be performed to reduce the resistance of the patterned doped layer 14 . In addition, the annealing process for modifying the first channel layer 12 from an amorphous silicon semiconductor layer to a polysilicon semiconductor layer can also be integrated into a single annealing process for reducing the resistance of the patterned doped layer 14 .

As shown in FIG. 3 , a gate dielectric layer 16 is then formed on the substrate 10 to cover the first channel layer 12 , the contact electrode 141 and the doped gate 142 . The material of the gate dielectric layer 16 can be various dielectric materials, such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto. In addition, the gate dielectric layer 16 can be a single-layer dielectric structure or a composite-layer dielectric structure. Next, a conductive gate 18 is formed on the gate dielectric layer 16 in the first region 101 , and a second channel layer 20 is formed on the gate dielectric layer 16 in the second region 102 . The conductive gate 18 is used as the gate of the second thin film transistor, and its material can be various materials with good conductivity, such as metal. The second channel layer 20 may include one of an amorphous silicon semiconductor layer, an oxide semiconductor layer and an organic semiconductor layer, but not limited thereto.

In a variant embodiment, the first channel layer, the doped gate and the contact electrode can also be formed by another method. For example, a patterned undoped semiconductor layer (not shown) is formed on the substrate 10 first, wherein the patterned undoped semiconductor layer corresponds to the positions where the first channel layer, the contact electrode and the doped gate are to be formed. Next, a gate dielectric layer 16 and a conductive gate 18 are formed on the patterned undoped semiconductor layer. Subsequently, the patterned undoped semiconductor layer is doped with ion implantation using the conductive gate 18 as a mask, so that the patterned undoped semiconductor layer covered by the conductive gate 18 forms the required first channel layer 12 , and the patterned undoped semiconductor layer not shielded by the conductive gate 18 will form the contact electrode 141 and the doped gate 142 after doping. In this variant embodiment, the contact electrodes 141 are located on both sides of the first channel layer 12 and on the same plane.

As shown in FIG. 4 , at least one inter-layered dielectric (ILD) 22 is formed on the gate dielectric layer 16 , the conductive gate 18 and the second channel layer 20 . Subsequently, a plurality of first contact holes 231 are formed in the interlayer dielectric layer 22 and the gate dielectric layer 16 to respectively expose the contact electrodes 141, and a plurality of second contact holes 232 are formed in the interlayer dielectric layer 22 to expose the first contact electrodes 141. Two channel layer 20 . The material of the interlayer dielectric layer 22 can be various dielectric materials, such as silicon oxide, silicon nitride or silicon oxynitride, etc., but not limited thereto. Next, a first electrode 241 and a second electrode 242 are formed on the interlayer dielectric layer 22 in the first region 101, and the first electrode 241 and the second electrode 242 are respectively connected to each contact via the first contact hole 231. The electrodes 141 are electrically connected. The first electrode 241 and the second electrode 242 are the source/drain of the first thin film transistor. In addition, a third electrode 243 and a fourth electrode 244 are formed on the interlayer dielectric layer 22 in the second region 102 , and the third electrode 243 and the fourth electrode 244 are respectively electrically connected through the second contact hole 232 two sides of the second channel layer 20 . The third electrode 243 and the fourth electrode 244 are source/drain electrodes of the second thin film transistor. The first electrode 241 , the second electrode 242 , the third electrode 243 and the fourth electrode 244 can be defined by the same layer of photomask, and the material thereof can be, for example, metal, but not limited thereto.

The semiconductor device 30 of this embodiment can be completed through the above-mentioned manufacturing process. In the first region 101, the first channel layer 12, the contact electrode 141, the gate dielectric layer 16, the conductive gate 18, the first electrode 241 and the second electrode 242 form a first thin film transistor assembly 301; In the region 102 , the doped gate 142 , the gate dielectric layer 16 , the second channel layer 20 , the third electrode 243 and the fourth electrode 244 form a second thin film transistor device 302 . In addition, in this embodiment, the first TFT device 301 is a P-type TFT device, and the second TFT device 302 is an N-type TFT device, but not limited thereto.

The semiconductor device of the present invention is not limited to the above-mentioned embodiments, and the present invention further provides an electroluminescent device including the semiconductor device. The semiconductor components and electroluminescent components of other preferred embodiments of the present invention will be introduced in sequence below, and in order to facilitate the comparison of the differences between the various embodiments and simplify the description, the same symbols are used in the following embodiments to mark the same Components, and the description will be mainly focused on the differences between the embodiments, and the repeated parts will not be repeated.

Please refer to FIG. 5 to FIG. 7 , and also refer to FIG. 4 . Fig. 5 depicts a schematic top view of an electroluminescent component according to a second preferred embodiment of the present invention, Fig. 6 illustrates a schematic cross-sectional view of an electroluminescent component according to a second preferred embodiment of the present invention, and Fig. 7 A circuit structure diagram of the electroluminescent device according to the second preferred embodiment of the present invention is shown. As shown in FIGS. 5 to 7 , the electroluminescent device 40 of this embodiment includes a semiconductor device 50 , and further includes a first protection layer 41 , a light emitting device 42 and a second protection layer 43 . The first protective layer 41 covers the interlayer dielectric layer 22 and exposes the first electrode 241; the light emitting component 42 is located on the first protective layer 41 and is electrically connected to the exposed first electrode 241; the second protective layer The layer 43 is located on the first protective layer 41 and at least partially exposes the light emitting component 42 . In this embodiment, the light-emitting element 42 is located on the first protective layer 41, so the light-emitting element 42 can extend into the first region 101 and overlap with the first thin film transistor element 501, so as to increase the aperture ratio, but this is not a limitation. limit. For example, in the condition that the first protection layer 41 is not provided, the light emitting element 42 can also be disposed on the interlayer dielectric layer 22 and not overlap with the first thin film transistor element 501 . In this embodiment, the light emitting component 42 can be, for example, an organic light emitting diode component, but not limited thereto. The light emitting element 42 includes an anode electrode 421 , a light emitting layer 422 and a cathode electrode 423 , wherein the anode electrode 421 is electrically connected to the first electrode 421 , and the cathode electrode 423 is electrically connected to a common signal Vcom. The semiconductor component 50 of this embodiment is similar to the semiconductor component 30 of FIG. And the interlayer dielectric layer 22 further has a fourth contact hole 234 partially exposing the conductive gate 18 . The third electrode 243 is electrically connected to the conductive gate 18 through the fourth contact hole 234 . In this embodiment, the first thin film transistor device 501 is used as a driving thin film transistor device, and the second thin film transistor device 502 is used as a switching thin film transistor device. In addition, the conductive gate 18 partially overlaps the second electrode 242 to form a first storage capacitor Cst1. As shown in FIG. 5 and FIG. 7 , the electroluminescent device 40 of this embodiment further includes a power line PL, a scan line SL and a data line DL, the power line PL is electrically connected to the second electrode 242, and the scan line SL is electrically connected to the second electrode 242. The conductive electrode 18 is electrically connected, and the data line DL is electrically connected to the fourth electrode 244 .

Please refer to Figure 8. FIG. 8 is a schematic diagram of a semiconductor device according to a third preferred embodiment of the present invention. As shown in FIG. 8 , in the semiconductor device 70 of this embodiment, the second electrode 242 of the first TFT device 701 is electrically connected to the third electrode 243 of the second TFT device 702 .

Please refer to Figure 9. FIG. 9 is a schematic diagram of a semiconductor device according to a fourth preferred embodiment of the present invention. As shown in FIG. 9, in the semiconductor component 80 of this embodiment, the doped gate 142 of the second thin film transistor component 802 protrudes from the second channel layer 20, and the interlayer dielectric layer 22 and the gate dielectric layer 16 further has a third contact hole 233 partially exposing the doped gate 142 . In addition, the second electrode 242 of the first TFT component 801 is electrically connected to the doped gate 142 of the second TFT component 802 via the third contact hole 233 .

Please refer to Figure 10. FIG. 10 is a schematic diagram of a semiconductor device according to a fifth preferred embodiment of the present invention. As shown in FIG. 10, in the semiconductor component 90 of this embodiment, the conductive gate 18 of the first thin film transistor component 901 bypasses the second electrode 242 and extends to the outside of the second electrode 242, and the second thin film transistor component The doped gate 142 of 902 protrudes from the second channel layer 20 . The interlayer dielectric layer 22 and the gate dielectric layer 16 further have a fifth contact hole 235 partially exposing the conductive gate 18 , and a sixth contact hole 236 partially exposing the doped gate 142 . In addition, a connection electrode 245 is electrically connected to the conductive gate 18 through the fifth contact hole 235, and is electrically connected to the doped gate 142 through the sixth contact hole 236, so that the conductive gate 18 and the doped gate 142 electrical connection.

The third to fifth preferred embodiments of the present invention respectively disclose different electrical connection modes of the first thin film transistor component and the second thin film transistor component of the semiconductor component, which can be selected and applied depending on the circuit design, but the present invention The electrical connection manner between the first thin film transistor component and the second thin film transistor component of the semiconductor component is not limited to the above manner. In addition, the semiconductor devices disclosed in the third to fifth preferred embodiments of the present invention can also be applied to electroluminescent devices, but not limited thereto.

Please refer to FIG. 11 , and please also refer to FIGS. 5 to 7 . FIG. 11 is a schematic diagram of a storage capacitor structure of an electroluminescent device according to a sixth preferred embodiment of the present invention. As shown in FIG. 11, in this embodiment, the patterned doped layer 14 further includes a storage electrode 143, the storage electrode 143 is electrically connected to the power line PL shown in FIG. 6, and the conductive gate 18 is connected to the storage electrode. 143 partially overlap to form a second storage capacitor Cst2.

Please refer to FIG. 12 , and please also refer to FIGS. 5 to 7 . FIG. 12 is a schematic diagram of a storage capacitor structure of an electroluminescent device according to a seventh preferred embodiment of the present invention. As shown in FIG. 12, in this embodiment, the second electrode 242 is electrically connected to the power line PL shown in FIG. 7, and the conductive gate 18 partially overlaps with the second electrode 242 to form a first storage capacitor Cst1. . In addition, the patterned doped layer 14 further includes a storage electrode 143 , and the interlayer dielectric layer 22 and the gate dielectric layer 16 have a contact hole 237 , so that the storage electrode 143 and the second electrode 242 can pass through the contact hole 237 are electrically connected, and the conductive gate 18 partially overlaps the storage electrode 143 to form a second storage capacitor Cst2. Through the above configuration, the first storage capacitor Cst1 and the second storage capacitor Cst2 are connected in parallel to provide a larger storage capacitor value.

To sum up, the semiconductor device of the present invention uses a non-ion implantation process to form the contact electrode and the doped gate, which can simplify the process. In addition, the annealing process can effectively reduce the resistance of the contact electrode and the doped gate, thereby improving the electrical performance of the semiconductor device. The semiconductor component of the electroluminescence component of the present invention also has contact electrodes formed by non-ion implantation process, and can be applied to manufacture large-sized display panels.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (26)

1. a semiconductor subassembly is arranged on the substrate, and this substrate comprises a first area and a second area, and this semiconductor subassembly comprises:

One first channel layer is positioned on this substrate of this first area;

One patterning doped layer comprises a doping grid and two contact electrodes, and this doping grid is positioned on this substrate of this second area, and said contact electrode connects the both sides of this first passage layer respectively;

One gate dielectric covers this first channel layer and this patterning doped layer;

One conductive grid is positioned on this gate dielectric of this first area;

One second channel layer is positioned on this gate dielectric of this second area;

One first electrode and one second electrode are respectively with respectively this contact electrode electric connection; And

One third electrode and one the 4th electrode electrically connect the both sides of this second channel layer respectively.

2. semiconductor subassembly according to claim 1; It is characterized in that; This first passage layer, said contact electrode, this gate dielectric, this conductive grid, this first electrode and this second electrode constitute a first film transistor component, and this doping grid, this gate dielectric, this second channel layer, this third electrode and the 4th electrode constitute one second thin-film transistor component.

3. semiconductor subassembly according to claim 2; It is characterized in that; This first film transistor component comprises a P type thin-film transistor component, and this second thin-film transistor component comprises a N type thin-film transistor component, and this patterning doped layer comprises a P type patterning doped layer.

4. semiconductor subassembly according to claim 1 is characterized in that, this patterning doped layer comprises nonionic implantation (non-implant) doped layer.

5. semiconductor subassembly according to claim 1 is characterized in that, this first passage layer comprises a polysilicon semiconductor layer, and this second channel layer comprises wherein one of an amorphous silicon semiconductor layer, monoxide semiconductor layer and an organic semiconductor layer.

6. semiconductor subassembly according to claim 1; It is characterized in that; Other comprises at least one interlayer dielectric layer (inter-layered dielectric; ILD) be positioned on this gate dielectric, this conductive grid and this second channel layer; This at least one interlayer dielectric layer and this gate dielectric have a plurality of first and contact the hole and expose respectively this contact electrode respectively; This at least one interlayer dielectric layer has a plurality of second contact holes and exposes this second channel layer, and this first electrode and this second electrode contact the hole via said first and electrically connect with this contact electrode respectively respectively, and this third electrode contacts hole and the electric connection of this second channel layer with the 4th electrode via said second.

7. semiconductor subassembly according to claim 1 is characterized in that, more comprises a luminescence component, is positioned at this first area at least and electrically connects with this first electrode.

8. semiconductor subassembly according to claim 1 is characterized in that, this second electrode and this third electrode electrically connect.

9. semiconductor subassembly according to claim 1 is characterized in that, this second electrode and this doping grid electrically connect.

10. semiconductor subassembly according to claim 1 is characterized in that, this conductive grid and this third electrode electrically connect.

11. semiconductor subassembly according to claim 1 is characterized in that, this conductive grid and this doping grid electrically connect.

12. semiconductor subassembly according to claim 1 is characterized in that, this conductive grid and this second electrode are overlapped and are formed one first storage capacitors.

13. semiconductor subassembly according to claim 1 is characterized in that, this patterning doped layer more comprises a storage electrode, and this conductive grid and this storage electrode are overlapped and formed one second storage capacitors.

14. semiconductor subassembly according to claim 1; It is characterized in that; This patterning doped layer more comprises a storage electrode; This conductive grid and this second electrode are overlapped and are formed one first storage capacitors, and this conductive grid and this storage electrode are overlapped and formed one second storage capacitors, and this second electrode contacts the hole electric connection with this storage electrode via one.

15. the manufacture method of a semiconductor subassembly comprises:

One substrate is provided, and this substrate comprises a first area and a second area:

On this substrate of this first area, form a first passage layer;

On this substrate, form a patterning doped layer, wherein this patterning doped layer comprises that two contact electrodes connect the both sides of this first passage layer in this first area, and a doping grid is positioned on this substrate of this second area;

On this substrate, form a gate dielectric, cover this first passage layer, said contact electrode and this doping grid;

Form a conductive grid on this gate dielectric in this first area;

Form a second channel layer on this gate dielectric in this second area;

In this first area, form one first electrode and one second electrode, respectively with respectively this contact electrode electric connection; And

In this second area, form a third electrode and one the 4th electrode, electrically connect the both sides of this second channel layer respectively.

16. the manufacture method of semiconductor subassembly according to claim 15; It is characterized in that; This first passage layer, said contact electrode, this gate dielectric, this conductive grid, this first electrode and this second electrode constitute a first film transistor component, and this doping grid, this gate dielectric, this second channel layer, this third electrode and the 4th electrode constitute one second thin-film transistor component.

17. the manufacture method of semiconductor subassembly according to claim 16; It is characterized in that; This first film transistor component comprises a P type thin-film transistor component; This second thin-film transistor component comprises a N type thin-film transistor component, and this patterning doped layer comprises a P type patterning doped layer.

18. the manufacture method of semiconductor subassembly according to claim 15; It is characterized in that; This first passage layer comprises a polysilicon semiconductor layer, and this second channel layer comprises wherein one of an amorphous silicon semiconductor layer, monoxide semiconductor layer and an organic semiconductor layer.

19. the manufacture method of semiconductor subassembly according to claim 15 is characterized in that, the step that forms this patterning doped layer comprises nonionic implantation (non-implant) processing procedure.

20. the manufacture method of semiconductor subassembly according to claim 19 is characterized in that, more comprises this patterning doped layer is carried out at least one annealing (anneal) processing procedure.

21. the manufacture method of semiconductor subassembly according to claim 15; It is characterized in that; More be included in and form after said first electrode and this second electrode formation one luminescence component in this first area, wherein this luminescence component and this first electrode electric connection.

22. an electroluminescence part is arranged on the substrate, this substrate comprises a first area and a second area, and this electroluminescence part comprises:

One first channel layer is positioned on this substrate of this first area;

One patterning doped layer comprises a doping grid and two contact electrodes, this doped gate

The utmost point is positioned on this substrate of this second area, and said contact electrode connects the both sides of this first passage layer respectively;

One gate dielectric covers this first channel layer and this patterning doped layer;

One conductive grid is positioned on this gate dielectric of this first area;

One second channel layer is positioned on this gate dielectric of this second area;

One first electrode and one second electrode are respectively with respectively this contact electrode electric connection;

One third electrode and one the 4th electrode electrically connect the both sides of this second channel layer respectively;

And

One luminescence component electrically connects with this first electrode.

23. electroluminescence part according to claim 22 is characterized in that, this luminescence component comprises an anode electrode, a luminescent layer and a cathode electrode, and this anode electrode electrically connects this first electrode.

24. electroluminescence part according to claim 22 is characterized in that, this conductive grid and this third electrode electrically connect.

25. electroluminescence part according to claim 22 is characterized in that, this conductive grid and this second electrode are overlapped and are formed one first storage capacitors.

26. electroluminescence part according to claim 22; It is characterized in that, more comprise a power line, one scan line, with a data wire, this power line electrically connects this second electrode; This scan line electrically connects this conductive electrode, and this data wire electrically connects the 4th electrode.

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