[go: up one dir, main page]

CN102315189A - 半导体衬底上的键合接触部位 - Google Patents

半导体衬底上的键合接触部位 Download PDF

Info

Publication number
CN102315189A
CN102315189A CN2011101860139A CN201110186013A CN102315189A CN 102315189 A CN102315189 A CN 102315189A CN 2011101860139 A CN2011101860139 A CN 2011101860139A CN 201110186013 A CN201110186013 A CN 201110186013A CN 102315189 A CN102315189 A CN 102315189A
Authority
CN
China
Prior art keywords
bonding
layer
island
contact site
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011101860139A
Other languages
English (en)
Other versions
CN102315189B (zh
Inventor
H-G·齐默尔
P·施通普夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK- Maikenasi limited liability company
Original Assignee
MEIKENAS CO
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MEIKENAS CO filed Critical MEIKENAS CO
Publication of CN102315189A publication Critical patent/CN102315189A/zh
Application granted granted Critical
Publication of CN102315189B publication Critical patent/CN102315189B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及一种在半导体衬底(2)上的具有增强结构(10)的键合接触部位(1)，包括：至少一个设置在半导体衬底(2)上的导电材料层(3)，用于接收具有图案的增强结构(10)；一个构成为具有键合面的键合接触层的、设置在导电材料层(3)上的金属层(4)，其中，在键合面(5)下面设置至少一个约2μm厚的氧化层，该氧化层伸出超过键合面(5)的边缘，增强结构(10)位于氧化层(14)中，从上方向键合面(5)看去在键合面(5)以外在氧化层(14)内部。

Description

半导体衬底上的键合接触部位
技术领域
本发明涉及一种如权利要求1前序部分所述的在半导体衬底上的具有增强结构的键合接触部位。
背景技术
键合接触部位通常由介电质层、接触层和金属化层的层序组成。最上层，被称为键合面(键合垫)，通过所谓的键合与“包装”中的细导线电连接。
已知的是，在键合过程期间通过键合毛细触点施加在键合接触部位上的机械负荷和超声波应力可能导致形成裂纹直到位于其下面的介电质断裂、位于其下面的金属结构变形以及金属结构中的层脱离。这些键合故障可能作为焊口出现在键合接触部位和位于其下面的层中并且通常在键合期间不是可见的，而是只有在接下来的拉力和剪切测试或可靠性测试期间才显示出来。
这些问题由于新的工艺选择、如三层金属化、芯片-平面化(化学-机械平面化)和通过铜-键合导线替换金-键合导线而变得尖锐。
已知的是，键合接触部位为了改善其机械特性在横向方向上均匀或周期地设有增强结构。
在EP 0 875 934 B1中描述了具有至少一个介电质层的键合接触部位，它具有一个设有图案的增强结构，该增强结构由相互连接的、例如格栅形设置的金属化导线组成。
发明内容
本发明的任务是，给出一种上述形式的具有改善的特性的键合接触部位，尤其在与铜键合的兼容性方面具有更高的可靠性，铜键合由于在键合时能量吸收更高而且工作温度更高而需要坚固的且均匀的键合垫特性。
该任务通过具有权利要求1特征的键合接触部位解决。
按照本发明的键合接触部位规定：在半导体衬底上具有增强结构；至少一个设置在半导体衬底上的第一金属层，用于接收具有图案的增强结构；一个作为具有键合面(键合垫)的键合接触层设置在第一金属层上方的第三金属层，其中，在键合面下方且在第一金属层上方设置有一个绝缘层，所述绝缘层伸出超过键合面的边缘，从上方向键合面看去，增强结构在键合面下方在第一金属层内部构成，以及增强结构包括介电的岛。
这种在半导体衬底上的具有增强结构的键合接触部位包括至少一个设置在半导体衬底上的用于接收具有图案的增强结构的导电材料层和一个构成为具有键合面(键合垫)的键合接触层、设置在导电材料层上的金属层，，该键合接触部位按照本发明根据改进方案的特征在于，
增强结构由规则地设置的第一和第二形状的岛构成，
第一形状的岛格栅形地设置，
分别在四个直接相邻的、构成格栅点的第一形状的岛之间设置有一个第二形状的岛，以及
第二形状的岛构成格栅形的结构。
通过按照本发明结构化的导电材料层、优选金属如铝或铜实现键合接触部位的良好机械特性，由此更好地接收在键合时的力，以便由此抑制或者至少减小直至衬底上的裂纹形成。
通过按照本发明有利改进方案框架形地包围中心设置的增强结构，可以优选在该框架形包围的区域中通过设置在至少一个介电质层中的敷镀通孔(via)建立与键合接触层的电接触。因此，在通过键合受到机械负载的键合垫区域以外实现这些敷镀通孔，这些敷镀通孔在机械上起到不利作用，但是对于导电材料层的电连接是必需的。接收敷镀通孔的介电质层也在键合垫下面的区域没有这种敷镀通孔。因此，这种键合接触部位特别适用于汽车应用，因为在增强结构的区域中在其下面的半导体衬底中部实现有源的电子结构元件。
本发明的另一改进方案的特征在于，
增强结构具有一个由规则地设置的岛构成的图案，
导电材料层框架形地包围增强结构，以及
导电材料层在边缘区域中通过设置在至少一个介电质层中的敷镀通孔与键合接触层电连接。
因此在通过键合受到机械负载的键合垫区域以外实现所需的敷镀通孔，它们在机械上起到不利作用，但是对于导电材料层的电连接是必需的。接收敷镀通孔的介电质层也在键合垫下面的区域中没有这种敷镀通孔。因此这种按照本发明的键合接触部位特别适用于汽车应用，因为在增强结构区域中在其下面的半导体衬底中不实现有源的电子结构元件。
按照改进方案在上述两个解决方案中所述岛以第一形状和第二形状构成，其中第一形状的岛格栅形地设置，并且分别在四个相邻的、形成格栅点的第一形状的岛之间设置有一个第二形状的岛，并且第二形状的岛同样形成格栅形的结构。
在本发明的改进方案中，所述第一形状的岛在导电材料层的平面中具有正方形或矩形的横截面，由此能够容易地制造这种岛，因为在此产生的结构四重旋转对称。
在本发明另一扩展结构中，所述第二形状的岛在导电材料层的平面中具有十字形的横截面并因此形成同样格栅形的、四重旋转对称的结构，从而由此产生的增强结构图案也是四重旋转对称的。在此优选已经证实特别有利的是，在导电材料层的平面中相邻的第二形状的岛的边界以及第一形状的岛与第二形状的岛之间的边界具有一致的间距。因此在优选由介电质制成的增强结构图案的区域中、即在接收这个增强结构的材料层的区域中介电质含量与导电材料层的材料含量相比是主要的。
以有利的方式按照本发明的改进方案设有另一导电材料层，它设置在具有增强结构的导电材料层上并且具有中心设置的由介电质制成的岛，该岛被导电材料层框架形地包围。由此在本发明的这个改进方案中在键合垫下面的区域也保持没有其它结构。这样产生的键合接触部位具有在键合垫下面的、垂直于衬底表面平放的由介电质制成的区域，这些区域在层序中不中断。由此得到键合接触部位直到材料弹性变形极限的承载能力。
因此优选在两个导电材料层之间或者在键合垫与位于其下面的导电材料层之间的介电质层以相同方式只在边缘区域中具有对于电连接必需的敷镀通孔。
最后按照本发明的改进方案在两个导电材料层之间设置一个介电质层，它通过设置在边缘区域中的敷镀通孔使两个导电材料层电连接。
为了使实际的键合垫保持没有会降低负荷能力的结构，通过开孔在钝化层中限定的键合垫没有敷镀通孔。按照本发明的改进方案，这些敷镀通孔设置在钝化层的边缘区域中。
此外特别有利的是，具有增强结构的导电材料层以其它材料层和/或介电质层为参照设置在衬底侧，即，该导电材料层尽可能靠近衬底。由此通过这种结构化的材料层截住可能出现的裂纹。
导电材料层由金属、优选由铝和/或铜产生，介电质层中的敷镀通孔为了电接通以金属、优选以钨或铝充满。
根据一种优选的实施方式，键合接触层的边缘相对于第二金属层的金属框架的外边缘而且相对于内边缘错开。此外，第二金属层的框架的外边缘以及内边缘也相对于第一金属层的框架的外边缘和内边缘错开。第一金属层的框架的外边缘和内边缘也相对于键合接触层的边缘错开，使得第一金属层中的边缘、第二金属层中的边缘和键合接触层中的边缘不相互叠置。换言之，各个金属层中的这些金属框架和键合面的相应外边缘分别相对彼此横向地错开。
申请人的研究已经表明：借助金属层的相对彼此错开的边缘能够有效地抑制裂纹形成。要注意的是，各个框架和键合接触层仅在变换实施方式中借助通路或敷镀通孔电连接。
显然，各个框架的相对彼此错开的边缘的以上原理可以扩展到超过3个金属层。
附图说明
下面借助于实施例参照附图详细描述本发明。其中：
图1示出按照本发明的键合接触部位的第一实施例的横截面图，
图2按照图1的键合接触部位的按照本发明的增强结构的俯视图，和
图3示出按照本发明的键合接触部位的第二实施例的横截面图。
具体实施方式
按照图1的键合接触部位1设置在半导体衬底2上，在其中在以x表示的区域以外可以实现有源的半导体结构元件，例如晶体管、二极管、存储器或传感器元件和类似元件。
这个键合接触部位1包括：多个、优选三个上下叠置的材料层；一个设置在衬底2上的、但是通过两个薄的介电质层9与衬底2分开的、由铝制成的第一金属层3，它具有由介电质制成的增强结构10，增强结构与第二金属层7通过第一介电质层8间隔；以及最后一个表示键合接触层4的第三金属层、同样由铝制成。键合接触层4的表面形成键合面或键合垫5，其中这个面由钝化层13矩形地包围，如同在图2中以俯视图表示的那样。键合接触层4具有边缘5a，该边缘构成在钝化层13下方，即钝化层13在该边缘的所有侧上与键合接触层4搭接。在第二金属层7与键合接触层4之间设置第二介电质层6。不仅第一介电质层8而且第二介电质层6的材料通常由二氧化硅SiO2制成。
由图1清楚地看出，在键合接触层4或键合接触部位5以外将增强结构设置在绝缘层14内部，它至少要有2μm厚。在此绝缘层14可以作为唯一的层这样厚地构成或者由多个上下叠置的分绝缘层组成，如同在图1中所示的那样。
在第一金属层3中实现的增强结构10图案由各个图案元件组成，它们构成为具有不同形状的岛11和12并且分别由介电质、例如二氧化硅组成。在按照图2的这个第一金属层3的俯视图中，岛11由在金属层3的平面中具有正方形横截面的第一形状组成并且岛12在横截面中由十字形的第二形状组成。
不仅正方形的岛11而且十字形的岛12分别格栅形地设置，其中，十字形的岛12位于四个相邻的岛11之间，其中这四个相邻的岛11形成由岛11撑开的格栅形结构的格栅点。
相邻十字形的岛12的边界和在十字形的岛11与正方形的岛12之间的边界都具有相同的、恒定的距离，由此在岛11和12之间保留金属层3的短臂形材料。因此在十字形的岛12之间的金属短臂以3a表示，在格栅形的岛11与十字形的岛12之间的金属短臂以3b表示。
增强结构10由金属层3的封闭边缘3c包围，其中所述金属层3在这个边缘3c的区域中利用设置在第一介电质层8中的敷镀通孔15与第二金属层7电连接。
这个第二金属层7框架形地结构化，由此金属的框架7a包围介电质岛14。代替介电质岛14也可以设有氧化物岛14。这个金属的框架7a通过第一介电质层8中的敷镀通孔15电连接第一金属层3的金属框架3c。
此外第二金属层7的这个框架7a通过设置在第二介电质层6中的敷镀通孔16与第三金属层4连接。这些敷镀通孔16同样位于第二介电质层6的边缘区域中，尤其是与第一介电质层8的敷镀通孔15一致。
敷镀通孔15或16由钨或铝制成。
如图2所示，这些敷镀通孔15和16设置在键合接触部位1的所有四个侧上，即完全框住该键合接触部位并因此不属于真正的键合垫结构，而是垂直地位于钝化层13下面。这一点也可以由图2的俯视图看出，因此增强结构10位于由钝化层13形成的框架内部。连接在其上的包围框架由第二金属层7的框架7a的内部棱边形成。
在增强结构10的区域中、即在由钝化层13限定的键合面5下面存在垂直延伸的由所有层的介电质制成的柱，该柱从第一金属层的岛11或12开始直到第二介电质层6，由此实现高的机械抵抗能力。
在图3中示出键合接触部位1的有利的第二实施方式。下面仅阐述相对于在图1的视图中所示的实施方式的不同。键合接触层4通过边缘5a限定。在此，键合接触层4的边缘5a相对于第二金属层7的金属框架7a的外边缘以及相对于内边缘错开。此外，第二金属层的框架7a的外边缘以及内边缘也相对于第一金属层3的框架3c的外边缘和内边缘错开。第一金属层3的框架3c的外边缘和内边缘也相对于边缘5a错开，使得第一金属层3中的边缘、第二金属层7中的边缘和键合接触层4中的边缘不相互上下叠置。换言之，这些金属框架3c、7a和键合面5a的相应外边缘分别相对彼此横向地错开。要注意的是，各个框架3c和7a以及键合接触层4仅在变换实施方式中借助通路或敷镀通孔15和16电连接。
显然，各个框架的相对彼此错开的边缘的以上原理可以扩展到超过3个金属层。
附图标记清单
1    键合接触部位
2    半导体衬底
3    导电材料层，金属层
3a   金属层3的在相邻的岛12之间的短臂
3b   金属层3的在岛12与13之间的短臂
3c   金属层3的环绕增强结构10的框架
4    金属层
5    键合面(键合垫)
5a   键合面的边缘
6    介电质层
7    导电材料层，金属层
7a   材料层7的框架
8    介电质层
9    介电质层
10   增强结构
11   第一形状的岛
12   第二形状的岛
13   钝化层
14   金属层7的介电质岛
15   介电质层8中的敷镀通孔
16   介电质层6中的敷镀通孔

Claims (12)

1.在半导体衬底(2)上的具有增强结构(10)的键合接触部位(1)，包括：
至少一个设置在所述半导体衬底(2)上的第一金属层(3)，用于接收具有图案的增强结构(10)，
一个作为具有键合面(键合垫)(5)的键合接触层设置在所述第一金属层(3)上方的第三金属层(4)，
在所述键合面(5)下方且在所述第一金属层(3)上方设置有一个绝缘层(14)，所述绝缘层伸出超过所述键合面(5)的边缘(5a)，
其特征在于，
从上方向所述键合面(5)看去，所述增强结构(10)在所述键合面(5)下方在所述第一金属层(3)内部构成，并且
所述增强结构(10)包括介电的岛(11，12)。
2.如权利要求1所述的键合接触部位(1)，其特征在于，所述绝缘层(14)具有至少约2μm的厚度，由多个分层组成。
3.如权利要求1或2所述的键合接触部位(1)，其特征在于，
所述增强结构(10)由规则地设置的第一和第二形状的岛(11，12)构成，
所述第一形状的岛(11)格栅形地设置，以及
分别在四个直接相邻的第一形状的岛(11)之间设置有第二形状的岛(12)，以及
所述第二形状的岛(12)形成格栅形的结构。
4.如权利要求1至3中任一项所述的键合接触部位(1)，其特征在于，在所述第一金属层(3)中构成一框架(3c)，所述框架包围所述增强结构(10)。
5.如权利要求1至4中任一项所述的键合接触部位(1)，其特征在于，所述第一金属层(3)在边缘区域中通过设置在至少一个介电质层(8)中的敷镀通孔(15)与所述键合接触层(4)电连接。
6.如权利要求1至5中任一项所述的键合接触部位(1)，其特征在于，所述第一形状的岛(11)在所述第一金属层(3)的平面中具有正方形的或矩形的横截面。
7.如上述权利要求中任一项所述的键合接触部位(1)，其特征在于，所述第二形状的岛(12)在所述第一金属层(3)的平面中具有十字形的横截面。
8.如上述权利要求中任一项所述的键合接触部位(1)，其特征在于，设有第二金属层(7)，所述第二金属层设置在具有所述增强结构(10)的第一金属层(3)上并且具有设置在中心的由介电质制成的岛，该岛被所述第二金属层(7)框架形地包围。
9.如权利要求8所述的键合接触部位(1)，其特征在于，在所述第一金属层(3)与所述第二金属层(7)之间设置有介电质层(8)，所述介电质层通过设置在边缘区域中的敷镀通孔(15)使两个导电材料层(3，7)电连接。
10.如权利要求8或9所述的键合接触部位(1)，其特征在于，所述键合面(5)在边缘区域中通过设置在介电质层(6)中的敷镀通孔(16)与所述第二金属层(7)电连接。
11.如上述权利要求中任一项所述的键合接触部位(1)，其特征在于，所述键合面(5)通过钝化层(13)的开孔限定并且所述敷镀通孔(15，16)设置在所述钝化层(13)的边缘区域中。
12.如上述权利要求中任一项所述的键合接触部位(1)，其特征在于，所述金属框架(3c，7a)和所述键合面(5a)的相应的外部边缘分别相对彼此横向地错开。
CN201110186013.9A 2010-06-30 2011-06-30 半导体衬底上的键合接触部位 Active CN102315189B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102010025754 2010-06-30
DE102010025754.0 2010-06-30

Publications (2)

Publication Number Publication Date
CN102315189A true CN102315189A (zh) 2012-01-11
CN102315189B CN102315189B (zh) 2015-07-29

Family

ID=45347039

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110186013.9A Active CN102315189B (zh) 2010-06-30 2011-06-30 半导体衬底上的键合接触部位

Country Status (3)

Country Link
JP (1) JP5550606B2 (zh)
CN (1) CN102315189B (zh)
DE (1) DE102011107349B4 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021072341A (ja) 2019-10-30 2021-05-06 キオクシア株式会社 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030047794A1 (en) * 2001-09-07 2003-03-13 Fujitsu Limited Semiconductor device capable of suppressing current concentration in pad and its manufacture method
CN1519923A (zh) * 2003-01-30 2004-08-11 恩益禧电子股份有限公司 半导体器件及其制造方法
US20050073058A1 (en) * 2003-10-07 2005-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package bond pad having plurality of conductive members
US20090212425A1 (en) * 2008-02-25 2009-08-27 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
US7632749B1 (en) * 2004-04-13 2009-12-15 Spansion Llc Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143396A (en) * 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
JP3632725B2 (ja) * 1997-12-05 2005-03-23 ソニー株式会社 半導体装置
US6552438B2 (en) * 1998-06-24 2003-04-22 Samsung Electronics Co. Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same
TW445616B (en) * 1998-12-04 2001-07-11 Koninkl Philips Electronics Nv An integrated circuit device
US6274474B1 (en) * 1999-10-25 2001-08-14 International Business Machines Corporation Method of forming BGA interconnections having mixed solder profiles
US7629689B2 (en) * 2004-01-22 2009-12-08 Kawasaki Microelectronics, Inc. Semiconductor integrated circuit having connection pads over active elements

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030047794A1 (en) * 2001-09-07 2003-03-13 Fujitsu Limited Semiconductor device capable of suppressing current concentration in pad and its manufacture method
CN1519923A (zh) * 2003-01-30 2004-08-11 恩益禧电子股份有限公司 半导体器件及其制造方法
US20050073058A1 (en) * 2003-10-07 2005-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package bond pad having plurality of conductive members
US7632749B1 (en) * 2004-04-13 2009-12-15 Spansion Llc Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer
US20090212425A1 (en) * 2008-02-25 2009-08-27 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same

Also Published As

Publication number Publication date
DE102011107349A1 (de) 2012-01-05
CN102315189B (zh) 2015-07-29
JP2012015516A (ja) 2012-01-19
JP5550606B2 (ja) 2014-07-16
DE102011107349B4 (de) 2016-05-12

Similar Documents

Publication Publication Date Title
US20060273385A1 (en) Trenched MOSFET device with contact trenches filled with tungsten plugs
US20170338189A1 (en) Insulated circuit board, power module and power unit
CN101150118A (zh) 半导体装置
CN102610584B (zh) 用于基板的交错布置的引脚结构
CN104105332A (zh) 电子元件内置基板
CN102738104B (zh) 集成电路器件及制造集成电路器件的方法
CN107683567A (zh) 弹性波装置
CN102315189A (zh) 半导体衬底上的键合接触部位
US8304963B2 (en) Piezoactuator with a predetermined breaking layer
CN100536120C (zh) 半导体芯片及其制造方法
CN102376675A (zh) 嵌埋有半导体元件的封装结构及其制法
JP3648596B2 (ja) 半導体チップの接合構造およびその構造を備えた表示装置
US9064707B2 (en) Bonding contact area on a semiconductor substrate
US8836150B2 (en) Semiconductor device
CN112271211B (zh) 分段式复合场板的终端结构
KR20150032497A (ko) 반도체 장치
JP2004505449A (ja) 応力低減層を有する合成樹脂により封止された半導体デバイス
US11869948B2 (en) Power semiconductor device with reduced strain
JP5485132B2 (ja) 半導体装置
US8198738B1 (en) Structure of bond pad for semiconductor die and method therefor
CN215731690U (zh) 半导体器件及引线框架
CN107026243B (zh) 一种显示面板以及显示装置
CN100472805C (zh) 半导体器件
CN217847935U (zh) 半导体装置的电性连接垫结构及覆晶芯片
CN203882993U (zh) 一种带有再钝化层开槽的Low-K芯片封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Freiburg

Patentee after: TDK- Maikenasi limited liability company

Address before: Freiburg

Patentee before: Meikenas Co.

CP01 Change in the name or title of a patent holder