CN102306691B - Method for raising light emitting diode luminescence efficiency - Google Patents

Abstract

The invention discloses a method for raising light emitting diode luminescence efficiency. A novel method is employed to a growth mode of a barrier layer in a luminescent layer in a light emitting diode epitaxial wafer structure: through growing barrier layers of different thicknesses, compound efficiency of an electron hole is raised, thus luminescence efficiency is raised. According to design of the method, high compound efficiency is ensured, low forward voltage is maintained, through increasing thickness of a barrier layer close to a side of an N type layer, migration motion of an electron is restricted, the electron is prevented from passing an MQW area to compound with the hole at a P type layer, thus thickness of a barrier layer close to a side of the P type layer is reduced, and the hole is facilitated to pass the barrier layer and compound with the electron at quantum well to raise light extraction efficiency.

Description

A method for improving the luminous efficiency of light-emitting diodes

technical field

The invention relates to a new method which can be applied to semiconductor light-emitting diodes, especially gallium nitride-based blue-green light-emitting diodes, and can effectively improve its luminous efficiency.

Background technique

Semiconductor light-emitting diodes have the advantages of small size, high efficiency and long life, and are widely used in traffic indication, outdoor full-color display and other fields. In particular, the use of high-power light-emitting diodes (LEDs) may realize semiconductor solid-state lighting, which has caused a revolution in the history of human lighting, and has gradually become a research hotspot in the field of optoelectronics. However, the current industrialized LED luminous efficiency is only about 50lm/W, which is much lower than traditional light sources. In order to obtain high-brightness LEDs, the key is to improve the quantum efficiency of the device.

Contents of the invention

The purpose of the present invention is to propose a new method to increase the quantum efficiency of semiconductor light-emitting diodes. This method is directly applied to the epitaxial wafer growth process. By changing the thickness of the barrier layer in the light-emitting layer MQW, the electrons and holes in the MQW are improved The efficiency of recombination increases its luminous efficiency.

The technical solution of the present invention is: a structure for improving the luminous efficiency of a light-emitting diode. The sequence of the diode epitaxial wafer structure from bottom to top is substrate, low-temperature buffer layer, high-temperature buffer layer, N-type layer, N-type layer, N-type layer, N-type layer, light-emitting layer, P-type layer, P-type layer, P-type layer. In the light-emitting layer MQW (Multiple Quantum Well), barrier layers with different thicknesses are used to improve luminous efficiency: the thickness of the barrier layer near the N-type layer is 15nm to 25nm, and the thickness of the barrier layer near the P-type layer is 5nm. to 15nm. The growth thickness of the barrier layer is between 5nm and 20nm, the growth temperature is between 800°C and 1050°C, and the V/IH molar ratio is between 1000 and 20000. In the light-emitting layer MQW, the structure of the barrier layer may be AlxInyGal-x-yN 0≤x<1, 0≤y<1, x+y<1. The X barrier layers in the middle of the light-emitting layer MQW are thicker, the remaining Y barrier layers are thinner, and the X barrier layers in the middle are thicker than the remaining Y barrier layers.

In the present invention, high-purity hydrogen (H2) or nitrogen (N2) is used as carrier gas, and trimethylgallium (TMGa), trimethylaluminum (TMAl), trimethylindium (TMIn) and ammonia (NH3) are respectively used as Ga, Al, In and N sources, use silane (SiH4), dimagnesium (Cp2Mg) as n and p type dopants respectively.

The epitaxial structure is shown in Figure 4:

(1) Substrate 1

The substrate 1 in the present invention is a material suitable for the growth of gallium nitride and other semiconductor epitaxial materials, such as gallium nitride single crystal, sapphire, single crystal silicon, silicon carbide (SiC) single crystal, and the like.

First, anneal the substrate material in a hydrogen atmosphere, clean the substrate surface, control the temperature between 1050°C and 1180°C, and then perform nitriding treatment;

(2) Low temperature buffer layer 2

Lower the temperature to between 500°C and 650°C, and grow a low-temperature GaN nucleation layer with a thickness of 15 to 30 nm. During this growth process, the growth pressure is between 300 Torr and 760 Torr, and the V/III molar ratio is between 500 and 3000;

(3) High temperature buffer layer 3

After the growth of the low-temperature buffer layer 2 is completed, stop feeding TMGa, raise the substrate temperature to between 1000°C and 1200°C, and anneal the low-temperature buffer layer 2 in situ, and the annealing time is between 5 minutes and 10 minutes ; After annealing, adjust the temperature to between 1000°C and 1200°C, and epitaxially grow high-temperature undoped GaN with a thickness between 0.8 μm and 2 μm under the condition of a relatively low V/III molar ratio. During this growth process, The growth pressure is between 50Torr and 760Torr, and the V/III molar ratio is between 300 and 3000;

(4) N-type layer 4

After the growth of U-GaN 3 is completed, grow an N-type layer 4 with a gradient increase in doping concentration, the thickness is between 0.2 μm and 1 μm, the growth temperature is between 1000 ° C and 1200 ° C, and the growth pressure is between 50 Torr and 760 Torr Between, the V/III molar ratio is between 300 and 3000;

(5) N-type layer 5

After the growth of the N-type layer 4 is completed, an N-type layer 5 with a stable doping concentration is grown, the thickness is between 1.2 μm and 3.5 μm, the growth temperature is between 1000° C. and 1200° C., the growth pressure is between 50 Torr and 760 Torr, V /III molar ratio between 300 and 3000;

(6) N-type layer 6

After the growth of N-type layer 5 is completed, grow N-type layer 6 with a thickness between 10nm and 100nm, a growth temperature between 1000°C and 1200°C, a growth pressure between 50Torr and 760Torr, and a V/III molar ratio between 300 and 1200°C. Between 3000;

(7) N-type layer 7

After the growth of N-type layer 6 is completed, grow N-type layer 7 with a thickness between 10nm and 50nm; the doping concentration is stable, the growth temperature is between 1000°C and 1200°C, and the growth pressure is between 50Torr and 760Torr, V/III The molar ratio is between 300 and 3000;

(8) Light-emitting layer MWQ 8

The light-emitting layer 8 is composed of 6 to 15 periods of InaGa1-aN (0<a<1)/GaN multiple quantum wells. The thickness of the well is between 2nm and 3nm, the growth temperature is between 720 and 820°C, the growth pressure is between 200Torr and 400Tor r, the V/III molar ratio is between 300 and 5000; the thickness of the barrier is between 5 and 30nm The growth temperature is between 820 and 920°C, the growth pressure is between 200Torr and 400Torr, and the V/III molar ratio is between 300 and 5000;

(9) P-type layer 9

After 6 to 15 cycles of InaGa1-aN (0<a<1)/GaN multi-quantum well light-emitting layer 8 growth, the temperature is raised, the temperature is controlled between 950°C and 1080°C, and the growth pressure is between 50Torr and 500Torr. P-type AlxInyGa1-x-yN (0<x<1, 0≤y<1, x+y<1) wide bandgap electron barrier with V/III molar ratio between 1000 and 20000 and growth thickness between 10nm and 200nm layer. The forbidden band width of this layer is larger than that of the last barrier, which can be controlled between 4eV and 5.5eV; the Mg doping concentration of this layer, the Mg/Ga molar ratio is between 1/100 and 1/4.

(10) P-type layer 10

After the growth of the P-type layer 9 is completed, grow a P-type AlxInyGa1-x-yN (0≤x<1, 0≤y<1, x+y<1) layer with a thickness between 100nm and 800nm, that is, the P-type layer 10 The Mg doping concentration Mg/Ga molar ratio of the layer is between 1/100 and 1/4, and the growth temperature is between 850°C and 1050°C.

(11) P-type layer 11

After the growth of the P-type layer 10 is completed, the P-type contact layer is grown, the growth temperature is between 850°C and 1050°C, the growth pressure is between 100Torr and 760Torr, and the V/III molar ratio is between 1000 and 20000. This layer is Mg-doped The impurity concentration Mg/Ga molar ratio is between 1/100 and 1/4, and the growth thickness is between 5nm and 20nm.

After the epitaxial growth is completed, the temperature of the reaction chamber is lowered to 650-850° C., annealing is performed in a pure nitrogen atmosphere for 5 to 15 minutes, and then the temperature is lowered to room temperature to end the epitaxial growth.

Subsequently, a single small-sized chip is made through semiconductor processing processes such as cleaning, deposition, photolithography, and etching.

The advantage of the present invention is that: the design of the epitaxial growth process described in the present invention not only improves the electron-hole recombination efficiency, but also can reduce the working voltage, improve the ESD yield, and improve leakage.

Description of drawings

Fig. 1 chip structure diagram;

FIG. 2 is a schematic diagram of the MQW region structure of a traditional LED structure;

3 is a schematic diagram of the MQW region structure of a method for improving the luminous efficiency of a light-emitting diode according to the present invention;

4 is a schematic diagram of the MQW region structure of a method for improving the luminous efficiency of a light-emitting diode according to the present invention;

FIG. 5 is a schematic diagram of the MQW region structure of a method for improving the luminous efficiency of a light-emitting diode according to the present invention.

In the picture:

Among them, 1 is the substrate, 2 is the low-temperature buffer layer, 3 is the high-temperature buffer layer, 4, 5, 6, and 7 are N-type layers, 8 is the light-emitting layer, 9, 10, and 11 are P-type layers, and 12 is transparent Conductive layer (Ni/Au or ITO), 13 is P electrode, 14 is N electrode, 101 is quantum well, 102 is quantum barrier, 201 is quantum well, 202 203 204 205 206 is quantum barrier, 301 is quantum well, 302303 is a quantum barrier, 401 is a quantum well, and 402403 is a quantum barrier.

Detailed ways

Below in conjunction with embodiment the present invention is described further, all embodiments of the present invention all utilize Thomas Swan (AIXTRON subsidiary company) CCS MOCVD system to implement.

Example 1

As shown in Figure 1:

(1) Substrate 1

First, anneal the sapphire substrate at a temperature of 1120°C in a pure hydrogen atmosphere, and then perform nitriding treatment;

(2) Low temperature buffer layer 2

Lower the temperature to 585°C to grow a 20nm-thick low-temperature GaN nucleation layer. During this growth process, the growth pressure is 420 Torr, and the V/III molar ratio is 900;

(3) High temperature buffer layer 3

After the growth of the low-temperature buffer layer 2 is completed, stop feeding TMGa, raise the substrate temperature by 1120° C., and perform annealing treatment on the low-temperature buffer layer 2 in situ. The annealing time is 8 minutes; after the annealing, adjust the temperature to 1120° C. Epitaxial growth of high-temperature undoped GaN with a thickness of 1.2 μm under a lower V/III molar ratio. During this growth process, the growth pressure is 200 Torr, and the V/III molar ratio is 1500;

(4) N-type layer 4

After the growth of the high-temperature buffer layer 3 is completed, an N-type layer with a gradient increase in doping concentration is grown, the doping concentration is changed from 1×1017/cm3 to 5×1018/cm3, the thickness is 0.8 μm, and the growth temperature is 1120°C. The growth pressure is 150 Torr, and the V/III molar ratio is 1800;

(5) N-type layer 5

After the growth of the N-type layer 4 is completed, an N-type layer 5 with a stable doping concentration is grown, with a thickness of 3.5 μm, a growth temperature of 1120° C., a growth pressure of 150 Torr, and a V/III molar ratio of 1800;

(6) N-type layer 6

After the growth of N-type layer 5 is completed, grow N-type layer 6 with a thickness of 20nm and a stable doping concentration, which is lower than the average concentration of N-type layer 4, lower than the doping concentration of N-type layer 5, and far lower than N-type The doping concentration of layer 7 is to increase the mobility of carriers; the growth temperature is 1120°C, the growth pressure is 150 Torr, and the V/III molar ratio is 2800;

(7) N-type layer 7

After the growth of N-type layer 6 is completed, grow N-type layer 7 with a thickness of 10nm, a stable doping concentration, and a concentration higher than that of N-type layer 5. This layer is the region with the highest concentration in the entire N-type region, and its purpose is to obtain a higher concentration. carrier concentration. The growth temperature is 1120°C, the growth pressure is 150 Torr, and the V/III molar ratio is 2800;

(8) Light-emitting layer MQW 8

The light emitting layer 8 is composed of 6 periods of In _0.3 Ga _0.7 N/GaN multiple quantum wells. The thickness of the well is 2.5nm, the growth temperature is 780°C, the growth pressure is 200Torr, and the V/III molar ratio is 4500; the thickness of the barrier is 18nm, the growth temperature is 900°C, the growth pressure is 200Torr, and the V/III molar ratio is 4500 ;

As shown in FIG. 2, the thickness of the side 202 close to the N-type layer is between 18 and 24 nm, the thickness of the barrier layer 202 > 203 > 204 > 205 > 206, and the thickness of the last barrier layer 206 close to the P-type layer is between 5 and 5 nm. to 15nm.

(9) P-type layer 9

After 6 to 15 cycles of InaGa1-aN (0<a<1)/GaN multi-quantum well light-emitting layer 8 growth, the temperature is raised, the temperature is controlled between 950°C and 1080°C, and the growth pressure is between 50Torr and 500Torr. P-type AlxInyGa1-x-yN (0<x<1, 0≤y<1, x+y<1) wide bandgap electron barrier with V/III molar ratio between 1000 and 20000 and growth thickness between 10nm and 200nm layer. The forbidden band width of this layer is larger than that of the last barrier, which can be controlled between 4eV and 5.5eV; the Mg doping concentration of this layer, the Mg/Ga molar ratio is between 1/100 and 1/4.

(10) P-type layer 10

After the growth of the P-type layer 9, grow a 0.4 μm thick P-type layer 10, namely: P-type AlxInyGa1-x-yN (0≤x<1, 0≤y<1, x+y<1), the layer The forbidden band width is greater than the forbidden band width of the last barrier, but smaller than the forbidden band width of the P-type layer 9 . The growth temperature is 1000° C., the growth pressure is 200 Torr, the V/III molar ratio is 8000, and the Mg doping concentration Mg/Ga molar ratio of the P-type layer Mg is: 1/80.

(11) P-type layer 11

After the growth of the P-type layer 10 is completed, the P-type contact layer, that is, the P-type layer 11, is grown at a growth temperature of 1050° C., a growth pressure of 200 Torr, a V/III molar ratio of 10000, and a P-type doping concentration of 1×1020/cm3. The growth thickness was 15 nm.

After all the epitaxial growth is completed, the temperature of the reaction chamber is lowered to 800° C., annealing is performed in a pure nitrogen atmosphere for 10 min, and then the temperature is lowered to room temperature to end the epitaxial growth.

(12) ITO transparent conductive layer 12

(13) P electrode 13

(14) N electrode 14

Embodiment 1, after cleaning, deposition, photolithography and etching and other semiconductor processing processes, it is divided into LED chips with a size of 10×8 mil. After the LED chip test, the test current is 10mA, the light output power of a single small chip is 6.5mW, the working voltage is 3.21V, and it can be anti-static: the human body model is 5000V. In the traditional epitaxial growth method, the light output power of a single small chip with the same chip manufacturing process is only 5mW.

Example 2

In Example 2, the growth methods of the epitaxial layers 1, 2, 3, 4, 5, 6, 7, 9, 10, and 11 are the same as those in Example 1. The difference lies in the growth method of the barrier layer in the light-emitting layer MQW: as shown in Figure 3, the thickness of the first three barrier layers 302 on the side close to the N-type layer is the same, ranging from 12 to 24 nm, and the thickness of the middle three barrier layers 303 is the same The thicknesses of the last three barrier layers 302 on the side close to the P-type layer are also between 12 and 24 nm. Among them, the middle three barrier layers 302 have the thickest thickness.

Example 3

In Example 3, the growth methods of the epitaxial layers 1, 2, 3, 4, 5, 6, 7, 9, 10, and 11 are the same as those in Example 1. The difference lies in the growth method of the barrier layer in the light-emitting layer MQW: as shown in Figure 4, the thickness of the first three barrier layers 402 on the side close to the N-type layer is the same, ranging from 16 to 30 nm, and the thickness of the last six barrier layers 402 on the side close to the P-type layer is the same. The thickness of the barrier layer 403 also ranges from 12 to 24 nm. Among them, the thickness of the first three barrier layers on the side close to the N-type layer is the thickest.

After the chip manufacturing process and testing under the same conditions, the optical output power of a 10×8mil single small chip is 6.3mW, the working voltage is 3.15V, and it can be antistatic: the human body model is 5000V.

Claims (3)

1. A method for improving the luminous efficiency of a light-emitting diode. The sequence of the epitaxial wafer structure of the light-emitting diode is a substrate, a low-temperature buffer layer, a high-temperature buffer layer, a first N-type layer, a second N-type layer, and a third N-type layer from bottom to top. N-type layer, the fourth N-type layer, light-emitting layer, the first P-type layer, the second P-type layer, and the third P-type layer; it is characterized in that: barrier layers with different thicknesses are used in the light-emitting layer to improve luminous efficiency: The thickness of the barrier layer near the N-type layer is 15nm to 20nm, while the thickness of the barrier layer near the P-type layer is 5nm to 15nm; the growth thickness of the barrier layer is between 5nm and 20nm, and the growth temperature is between 800 °C to 1050 °C, V/III molar ratio is between 1000 and 20000. the 2. The method for improving the luminous efficiency of light-emitting diodes as claimed in claim 1, characterized in that: in the light-emitting layer, the structure of the barrier layer can be AlxInyGa1-x-yN 0≤x<1, 0≤y<1, x+y <1. the 3. The method for improving the luminous efficiency of a light-emitting diode as claimed in claim 1 or 2, wherein the X barrier layers in the middle of the light-emitting layer are thicker, the remaining Y barrier layers are thinner, and the X barrier layers in the middle are thicker. The thickness of is greater than the thickness of the remaining Y barrier layers. the

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