CN102291146B - Sampling hold circuit and method - Google Patents
Sampling hold circuit and method Download PDFInfo
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- CN102291146B CN102291146B CN2011101020367A CN201110102036A CN102291146B CN 102291146 B CN102291146 B CN 102291146B CN 2011101020367 A CN2011101020367 A CN 2011101020367A CN 201110102036 A CN201110102036 A CN 201110102036A CN 102291146 B CN102291146 B CN 102291146B
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- 238000005070 sampling Methods 0.000 title claims abstract description 94
- 238000000034 method Methods 0.000 title abstract description 11
- 239000003990 capacitor Substances 0.000 abstract description 33
- 230000001186 cumulative effect Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Abstract
The invention discloses a sampling hold circuit, which comprises an operational amplifier, and a first-stage sampling hold circuit and a second-stage sampling hold circuit which are connected with the operational amplifier respectively, wherein the operational amplifier is provided with a positive input end, a negative input end, a positive output end and a negative output end; the sampling hold circuit has a first phase and a second phase; the second-stage sampling hold circuit comprises a sampling capacitor; when the sampling hold circuit is at the first phase, the sampling capacitor is connected between the positive input end and the negative output end of the operational amplifier; and when the sampling hold circuit is at the second phase, the sampling capacitor is connected between the negative input end and the positive output end of the operational amplifier. The invention also provides a sampling hold method. The circuit has a simple structure; and the accuracy of the sampling hold circuit is improved.
Description
Technical field
The present invention relates to a kind of sampling hold circuit and method, espespecially a kind of sampling hold circuit and the method that can eliminate the offset error cumulative effect of operational amplifier.
Background technology
Sampling hold circuit is a kind of circuit be used in the analog/digital conversion system, and effect is to gather analog input voltage instantaneous value at a time, and at analog to digital converter, carries out the transition period and keep output voltage constant, for analog-to-digital conversion.
Refer to Fig. 1, shown in Figure 1 is existing two-stage sampling hold circuit, and it is formed by the independent sampling hold circuit cascade of two-stage, and the operation principle of every grade of sampling hold circuit is as follows: in the PH1 phase place, and capacitor C 11 and capacitor C 12 sampled input signals; In the PH2 phase place, capacitor C 13 and capacitor C 14 keep input signal; Due in the PH1 phase sample, operational amplifier does not need work, therefore, can utilize this phase place to carry out the offset voltage elimination to operational amplifier.But, for this two-stage sampling hold circuit, need two operational amplifiers, greatly increased system power dissipation.
In order to reduce power consumption, operational amplifier shares between the two-stage sampling hold circuit sampling hold circuit has also appearred in existing two-stage sampling hold circuit, and when the first order was sampled, operational amplifier was connected with second level holding circuit; When sample in the second level, operational amplifier is connected with first order holding circuit.Because operational amplifier is in the operating state that signal keeps always, offset error can be accumulated on input signal always, affects the precision of sampling hold circuit.
Summary of the invention
In view of above content, be necessary to provide a kind of sampling hold circuit and the method that can eliminate the offset error cumulative effect of operational amplifier.
A kind of sampling hold circuit, comprise an operational amplifier, one first order sampling hold circuit be connected with described operational amplifier respectively and a second level sampling hold circuit, described operational amplifier has a positive input terminal, one negative input end, one positive output end and a negative output terminal, described sampling hold circuit has one first phase place and one second phase place, described second level sampling hold circuit comprises a sampling capacitance, when described the first phase place, described sampling capacitance is connected between the positive input terminal and negative output terminal of described operational amplifier, when described the second phase place, described sampling capacitance is connected between the negative input end and positive output end of described operational amplifier.
A kind of sample hold method comprises the following steps:
One operational amplifier is provided, and described operational amplifier has a positive input terminal, a negative input end, a positive output end and a negative output terminal;
One first order sampling hold circuit and a second level sampling hold circuit be connected with described first order sampling hold circuit are provided, and described second level sampling hold circuit has a sampling capacitance;
When in second phase place, described sampling capacitance is connected between the positive input terminal and negative output terminal of described operational amplifier; And
When in first phase place, described sampling capacitance is connected between the negative input end and positive output end of described operational amplifier.
Relative prior art, sampling hold circuit of the present invention and method by the first phase place and the second phase place by the sampling hold circuit of the second level sampling capacitance be connected to the cumulative effect of eliminating the operational amplifier offset error on the different feedback networks of operational amplifier, circuit structure of the present invention is simple and improved the precision of sampling hold circuit.
The accompanying drawing explanation
Fig. 1 is the circuit diagram of sampling hold circuit of the prior art.
Fig. 2 is the circuit diagram of sampling hold circuit preferred embodiments of the present invention.
Fig. 3 is the flow chart of sample hold method preferred embodiments of the present invention.
Embodiment
Refer to Fig. 2, sampling hold circuit of the present invention comprises an operational amplifier A MP, a first order sampling hold circuit, a second level sampling hold circuit, a first input end Vinp, one second input Vinn, one first output end vo 2n and one second output end vo 2p.This operational amplifier A MP has a positive input terminal Vip, a negative input end Vin, a positive output end Vop and a negative output terminal Von.This first order sampling hold circuit comprises one first K switch 1, a second switch K2, one the 3rd K switch 3, one the 4th K switch 4, one the 5th K switch 5, one the 6th K switch 6, minion pass K7, one the 8th a switch K8, one the 9th K switch 9,1 the tenth K switch 10,1 the 11 K switch 11, twelvemo pass K12, a common-mode voltage end Vcom, one first capacitor C 11, one second capacitor C 12, one the 3rd capacitor C 13 and one the 4th capacitor C 14.This second level sampling hold circuit comprises that 1 the 13 K switch 13,1 the 14 K switch 14,1 the 15 K switch 15, a sixteenmo close K16,1 the tenth minion is closed K17, an eighteenmo pass K18,1 the 19 K switch 19, one the 20 K switch 20, one the 21 K switch 21, one second twelvemo pass K22, one the 23 K switch 23, one the 24 K switch 24, one the 5th capacitor C 15, one the 6th capacitor C 16, one the 7th capacitor C 17 and one the 8th capacitor C 18.This common-mode voltage end Vcom shares in this first order sampling hold circuit and this second level sampling hold circuit.This sampling hold circuit comprises one first phase place PH1 phase place and one second phase place PH2 phase place, wherein, the first K switch 1, second switch K2, the 5th K switch 5, the 6th K switch 6, the 11 K switch 11, twelvemo is closed K12, the 15 K switch 15, sixteenmo closes K16, the 19 K switch 19, the 20 K switch 20, the 21 K switch 21 and the second twelvemo are closed K22 by the PH1 phase control, the 3rd K switch 3, the 4th K switch 4, minion is closed K7, the 8th switch K8, the 9th K switch 9, the tenth K switch 10, the 13 K switch 13, the 14 K switch 14, the tenth minion is closed K17, eighteenmo closes K18, the 23 K switch 23 and the 24 K switch 24 are by the PH2 phase control.The 5th capacitor C 15 is the sampling capacitance of this second level sampling hold circuit.
The concrete annexation of sampling hold circuit of the present invention is as follows: this first input end Vinp is connected with an end of this first K switch 1, the other end of this first K switch 1 is connected with an end of this first capacitor C 11 and an end of the 3rd K switch 3, the other end of this first capacitor C 11 is connected with an end of the 5th K switch 5, and be connected with the end that this minion is closed K7 by one first voltage end Vi1p, the other end that this minion is closed K7 is connected with the positive input terminal Vip of this operational amplifier A MP, this second input Vinn is connected with the end of this second switch K2, the other end of this second switch K2 is connected with an end of an end of this second capacitor C 12 and the 4th K switch 4, the other end of this second capacitor C 12 is connected with an end of the 6th K switch 6, and be connected with the end of the 8th switch K8 by a second voltage end Vi1n, the other end of the 8th switch K8 is connected with the negative input end Vin of this operational amplifier A MP.The other end of the other end of the other end of the other end of the 3rd K switch 3, the 4th K switch 4, the 5th K switch 5 and the 6th K switch 6 is connected with this common-mode voltage end Vcom.One end of the 3rd capacitor C 13 is connected with this first voltage end Vi1p, the other end is by an end of a tertiary voltage end Vo1n and the 9th K switch 9, one end of the 11 K switch 11 and an end of the 13 K switch 13 are connected, the other end of the 9th K switch 9 is connected with the negative output terminal Von of this operational amplifier A MP, one end of the 4th capacitor C 14 is connected with this second voltage end Vi1n, the other end is by an end of one the 4th voltage end Vo1p and the tenth K switch 10, this twelvemo is closed the end of K12 and an end of the 14 K switch 14 is connected, the other end of the tenth K switch 10 is connected with the positive output end Vop of this operational amplifier A MP.The other end that the other end of the 11 K switch 11 and this twelvemo are closed K12 is connected with this common-mode voltage end Vcom.One end of the 5th capacitor C 15 is connected with the other end of the 13 K switch 13 and an end of the 15 K switch 15, the other end is connected with the end that the tenth minion is closed K17, and be connected with an end of the 19 K switch 19 by one the 5th voltage end Vi2p, the other end of the 19 K switch 19 is connected with the negative input end Vin of this operational amplifier A MP, one end of the 6th capacitor C 16 is connected with the end that the other end of the 14 K switch 14 and this sixteenmo close K16, the other end is connected with the end that this eighteenmo closes K18, and be connected with an end of the 20 K switch 20 by one the 6th voltage end Vi2n, the other end of the 20 K switch 20 is connected with the positive input terminal Vip of this operational amplifier A MP.The other end of the 15 K switch 15, this sixteenmo close the other end of K16, the other end of the tenth minion pass K17 and the other end that this eighteenmo closes K18 and are connected with this common-mode voltage end Vcom.One end of the 7th capacitor C 17 is connected with the 5th voltage end Vi2n, one end of the other end and the 21 K switch 21, one end of the 23 K switch 23 and this first output end vo 2n are connected, the other end of the 21 K switch 21 is connected with the positive output end Vop of this operational amplifier A MP, one end of the 8th capacitor C 18 is connected with the 6th voltage end Vi2p, the other end and this second twelvemo are closed the end of K22, one end of the 24 K switch 24 and this second output end vo 2p are connected, the other end that this second twelvemo is closed K22 is connected with the negative output terminal Von of this operational amplifier A MP.The other end of the 23 K switch 23 and the 24 K switch 24 is connected with this common-mode voltage end Vcom.
The operation principle of sampling hold circuit of the present invention is as follows: the offset error of supposing this operational amplifier A MP is Voffset, is added on the positive input terminal Vip of this operational amplifier A MP; When in the PH1 phase place, this first capacitor C 11 is sampled the signal of first input end Vinp and the second input Vinn input with this second capacitor C 12, and when in the PH2 phase place, the 3rd capacitor C 13 keeps the signal of input with the 4th capacitor C 14.
When in the PH2 phase place, the 5th capacitor C 15 is connected on the positive input terminal Vip and negative output terminal Von feedback path of this operational amplifier A MP, now, and the output voltage on the 5th capacitor C 15, i.e. the voltage Vo1n=Vinp+Voffset of this voltage end Vo1n.
When in the PH1 phase place, the 5th capacitor C 15 is connected on the negative input end Vin and positive output end Vop feedback path of this operational amplifier A MP, now, and the output voltage V o2p=Vo1n-Voffset=Vinp of the first output end vo 2p.
By above analysis, can be found out, sampling hold circuit of the present invention has been eliminated the cumulative effect of the offset error of this operational amplifier A MP, makes the precision of sampling hold circuit be guaranteed.
Refer to Fig. 3, sample hold method preferred embodiments of the present invention comprises the following steps:
Step 1, provide an operational amplifier A MP, and this operational amplifier A MP has positive input terminal Vip, negative input end Vin, positive output end Vop and negative output terminal Von.
Step 2, provide a first order sampling hold circuit and a second level sampling hold circuit be connected with this first order sampling hold circuit, and this first order sampling hold circuit and this second level sampling hold circuit have respectively at least one sampling capacitance.
Step 3, when in the PH2 phase place, the sampling capacitance of this second level sampling hold circuit is connected on the positive input terminal Vip and negative output terminal Von feedback path of this operational amplifier A MP, now, the output voltage on this sampling capacitance is the input voltage of this first order sampling hold circuit reception and the offset error sum on this operational amplifier.
Step 4, when in the PH1 phase place, be connected to the sampling capacitance of this second level sampling hold circuit on the negative input end Vin and positive output end Vop feedback path of this operational amplifier A MP.
Step 5, the output voltage of this second level sampling hold circuit equals input voltage.
Sampling hold circuit of the present invention and method by PH1 phase place and PH2 phase place by the sampling hold circuit of the second level sampling capacitance be connected to the cumulative effect of eliminating the operational amplifier offset error on the different feedback networks of operational amplifier, circuit structure of the present invention is simple and improved the precision of sampling hold circuit.
Claims (5)
1. sampling hold circuit, comprise an operational amplifier, one first order sampling hold circuit be connected with described operational amplifier respectively and a second level sampling hold circuit, described operational amplifier has a positive input terminal, one negative input end, one positive output end and a negative output terminal, described sampling hold circuit has one first phase place and one second phase place, described second level sampling hold circuit comprises a sampling capacitance, it is characterized in that: when described the first phase place, described sampling capacitance is connected between the positive input terminal and negative output terminal of described operational amplifier, when described the second phase place, described sampling capacitance is connected between the negative input end and positive output end of described operational amplifier, described sampling hold circuit also comprises a first input end, one second input, one first output and one second output, described first order sampling hold circuit comprises one first switch, one second switch, one the 3rd switch, one the 4th switch, one the 5th switch, one the 6th switch, one minion is closed, one the 8th switch, one the 9th switch, the tenth switch, the 11 switch, one twelvemo is closed, one common-mode voltage end, one first electric capacity, one second electric capacity, one the 3rd electric capacity and one the 4th electric capacity, described second level sampling hold circuit comprises 1 the 13 switch, the 14 switch, the 15 switch, one sixteenmo closes, the tenth minion is closed, one eighteenmo closes, the 19 switch, one the 20 switch, one the 21 switch, one second twelvemo is closed, one the 23 switch, one the 24 switch, one the 6th electric capacity, one the 7th electric capacity and one the 8th electric capacity, described sampling capacitance is one the 5th electric capacity, and described the first switch, second switch, the 5th switch, the 6th switch, the 11 switch, twelvemo pass, the 15 switch, sixteenmo pass, the 19 switch, the 20 switch, the 21 switch and the second twelvemo are closed by described the first phase control, described the 3rd switch, the 4th switch, minion pass, the 8th switch, the 9th switch, the tenth switch, the 13 switch, the 14 switch, the tenth minion pass, eighteenmo pass, the 23 switch and the 24 switch are by described the second phase control.
2. sampling hold circuit as claimed in claim 1, it is characterized in that: described first input end is connected with an end of described the first switch, the other end of described the first switch is connected with an end of described the first electric capacity and an end of described the 3rd switch, the other end of described the first electric capacity is connected with an end of described the 5th switch, and the end closed by one first voltage end and described minion is connected, the other end that described minion is closed is connected with the positive input terminal of described operational amplifier, described the second input is connected with an end of described second switch, the other end of described second switch is connected with an end of described the second electric capacity and an end of described the 4th switch, the other end of described the second electric capacity is connected with an end of described the 6th switch, and be connected with an end of described the 8th switch by a second voltage end, the other end of described the 8th switch is connected with the negative input end of described operational amplifier, the other end of described the 3rd switch, the other end of described the 4th switch, the other end of the other end of described the 5th switch and described the 6th switch is connected with described common-mode voltage end.
3. sampling hold circuit as claimed in claim 2, it is characterized in that: an end of described the 3rd electric capacity is connected with described the first voltage end, the other end is by an end of a tertiary voltage end and described the 9th switch, one end of described the 11 switch and an end of described the 13 switch are connected, the other end of described the 9th switch is connected with the negative output terminal of described operational amplifier, one end of described the 4th electric capacity is connected with described second voltage end, the other end is by an end of one the 4th voltage end and described the tenth switch, the end that described twelvemo is closed and an end of described the 14 switch are connected, the other end of described the tenth switch is connected with the positive output end of described operational amplifier, the other end that the other end of described the 11 switch and described twelvemo are closed is connected with described common-mode voltage end.
4. sampling hold circuit as claimed in claim 3, it is characterized in that: an end of described the 5th electric capacity is connected with the other end of described the 13 switch and an end of described the 15 switch, the other end is connected with the end that described the tenth minion is closed, and be connected with an end of described the 19 switch by one the 5th voltage end, the other end of described the 19 switch is connected with the negative input end of described operational amplifier, one end of described the 6th electric capacity is connected with the end that the other end of described the 14 switch and described sixteenmo close, the other end is connected with the end that described eighteenmo closes, and be connected with an end of described the 20 switch by one the 6th voltage end, the other end of described the 20 switch is connected with the positive input terminal of described operational amplifier, the other end of described the 15 switch, the other end that described sixteenmo closes, the other end that the other end that described the tenth minion is closed and described eighteenmo close is connected with described common-mode voltage end.
5. sampling hold circuit as claimed in claim 4, it is characterized in that: an end of described the 7th electric capacity is connected with described the 5th voltage end, one end of the other end and described the 21 switch, one end of described the 23 switch and described the first output are connected, the other end of described the 21 switch is connected with the positive output end of described operational amplifier, one end of described the 8th electric capacity is connected with described the 6th voltage end, the end that the other end and described the second twelvemo are closed, one end of described the 24 switch and described the second output are connected, the other end that described the second twelvemo is closed is connected with the negative output terminal of described operational amplifier, the other end of described the 23 switch and described the 24 switch is connected with described common-mode voltage end.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011101020367A CN102291146B (en) | 2011-04-22 | 2011-04-22 | Sampling hold circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011101020367A CN102291146B (en) | 2011-04-22 | 2011-04-22 | Sampling hold circuit and method |
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| CN102291146A CN102291146A (en) | 2011-12-21 |
| CN102291146B true CN102291146B (en) | 2013-11-27 |
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| CN2011101020367A Expired - Fee Related CN102291146B (en) | 2011-04-22 | 2011-04-22 | Sampling hold circuit and method |
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| CN118508964A (en) * | 2024-05-09 | 2024-08-16 | 成都华微电子科技股份有限公司 | Pipeline ADC Sample and Hold Circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2708007B2 (en) * | 1995-03-31 | 1998-02-04 | 日本電気株式会社 | Sample and hold circuit |
| CN101295983A (en) * | 2007-04-25 | 2008-10-29 | 中国科学院微电子研究所 | A double-sampling fully differential sample-and-hold circuit |
| CN101295985A (en) * | 2007-04-25 | 2008-10-29 | 中国科学院微电子研究所 | Multiplication digital-to-analog conversion circuit using two-phase unbalanced clock scheme and its application |
| CN201966892U (en) * | 2011-04-22 | 2011-09-07 | 四川和芯微电子股份有限公司 | Sampling holding circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002052574A1 (en) * | 2000-12-22 | 2002-07-04 | Koninklijke Philips Electronics N.V. | Low voltage sample and hold circuit with voltage range compression and expansion |
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- 2011-04-22 CN CN2011101020367A patent/CN102291146B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2708007B2 (en) * | 1995-03-31 | 1998-02-04 | 日本電気株式会社 | Sample and hold circuit |
| CN101295983A (en) * | 2007-04-25 | 2008-10-29 | 中国科学院微电子研究所 | A double-sampling fully differential sample-and-hold circuit |
| CN101295985A (en) * | 2007-04-25 | 2008-10-29 | 中国科学院微电子研究所 | Multiplication digital-to-analog conversion circuit using two-phase unbalanced clock scheme and its application |
| CN201966892U (en) * | 2011-04-22 | 2011-09-07 | 四川和芯微电子股份有限公司 | Sampling holding circuit |
Non-Patent Citations (1)
| Title |
|---|
| JP第2708007号B2 1998.02.04 |
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