CN102280997A - Charge pump system and memory - Google Patents
Charge pump system and memory Download PDFInfo
- Publication number
- CN102280997A CN102280997A CN2010102039629A CN201010203962A CN102280997A CN 102280997 A CN102280997 A CN 102280997A CN 2010102039629 A CN2010102039629 A CN 2010102039629A CN 201010203962 A CN201010203962 A CN 201010203962A CN 102280997 A CN102280997 A CN 102280997A
- Authority
- CN
- China
- Prior art keywords
- clock signal
- charge pump
- clock
- unit
- supply voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 16
- 238000007493 shaping process Methods 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 14
- 230000005540 biological transmission Effects 0.000 abstract description 10
- 230000000087 stabilizing effect Effects 0.000 abstract description 4
- 230000002708 enhancing effect Effects 0.000 abstract 2
- 239000003990 capacitor Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 10
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 8
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 8
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 8
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 8
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 8
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 8
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 3
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Landscapes
- Dc-Dc Converters (AREA)
Abstract
Discloses are a charge pump system and a memory. The charge pump system comprises a charge pump unit, a clock drive unit connected to the charge pump unit, and a power stabilizing unit, wherein the clock drive unit is provided with a first clock drive unit controlled by a first power supply voltage, enhancing the obtained current of a first type clock signal and outputting to the charge pump unit, and a second clock drive unit controlled by a second power supply voltage, enhancing the obtained current of a second type clock signal and outputting to the charge pump unit; and the power stabilizing unit is used for adjusting the second power supply voltage, so as to obtain the first power supply voltage. Compared with the prior art, in the invention, the first clock drive unit and the second clock drive unit are separately arranged and respectively provide different power supply voltages, thus improving the charging efficiency and the transmission efficiency.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of charge pump system and memory.
Background technology
In the information age, information stores is one of most important technology contents in the information technology.Memories such as DRAM, EEPROM, flash memory obtain application more and more widely.
Based on low-power consumption, requirement cheaply, the supply voltage VDD of memory is lower usually, for example 2.5V, 1.8V etc., yet " writing " and " wiping " in order to realize information, usually need be far above program voltage and the erasing voltage of supply voltage VDD, for example 8V, 11V etc.Therefore, charge pump system is widely used in the memory, is used for obtaining higher program voltage and erasing voltage by lower supply voltage VDD.
With reference to figure 1, show a kind of schematic diagram of charge pump circuit, described charge pump circuit comprises two voltage-boosting stages, wherein, first voltage-boosting stage comprises: first K switch 1 that transfer clock drives, first capacitor C 1 that is connected in described first K switch 1 constitute, the other end of described first capacitor C 1 is driven by the charging clock, and charging clock high level voltage is the lifting voltage V of charge pump system.During charge pump system work, when the charging clock is low level, power supply Vin is by 1 charging of 1 pair first capacitor C of first K switch, after charging finishes, the top crown voltage of first capacitor C 1 is Vin, and when the charging clock was high level, the bottom crown voltage of first capacitor C 1 was V, because electric capacity has the character that the two poles of the earth voltage difference can not be suddenlyd change, this moment, the top crown voltage jump of first capacitor C 1 was V+Vin.Afterwards, first capacitor C 1 is charged to second electric capacity 12 by second switch 22 again ..., electric charge has just passed to the right from the left side.Like this, along with the increase of charge pump progression, electric charge just continuously from the power source transition to the output, thereby obtain having the output voltage V out of high-voltage value.
Fig. 2 has shown charge pump system schematic diagram in one embodiment in the prior art.As shown in Figure 2, in the prior art, described charge pump system comprises crystal oscillator unit 10, overlapping shaping unit 12, clock drive unit 14 and charge pump unit 16, and wherein, crystal oscillator unit 10 is controlled by supply voltage VDD, is used to produce initial clock signal clk; Overlapping shaping unit 12 is controlled by supply voltage VDD, be used for the clock signal that crystal oscillator unit 10 the produces shaping that overlaps, output charging clock signal (CLK1_L, CLK3_L) and transmit clock signal (CLK2_L, CLK4_L); Clock drive unit 14, controlled by supply voltage VDD, be used for receiving overlapping shaping unit 12 output ground charging clock signal (CLK1_L, CLK3_L) and transmit clock signal (CLK2_L, CLK4_L) carry out the signal enhancement process after, output charging clock signal (CLK1, CLK3) and transmit clock signal (CLK2 is CLK4) to charge pump unit 16.Wherein, through overlapping shaping unit 12 output ground charging clock signal (CLK1_L, CLK3_L) and transmit clock signal (CLK2_L, CLK4_L) signal code is lower, and the charging clock signal (CLK1 that after clock drive unit 14 is handled, exports, CLK3) and transmit clock signal (CLK2, electric current CLK4) is higher.
In the above-described embodiments, owing to be used to control the magnitude of voltage lower (1.08V to 1.98V) of the supply voltage VDD of clock drive unit 14, provide the ability of charging charge and transmission charge just on the weak side, comparatively speaking, charge efficiency and efficiency of transmission are also just lower.In addition, because clock drive unit 14 is used to drive two class clock signals (first kind clock signal and the second type clock signal), cause power consumption bigger, therefore needing provides big electric current to clock drive unit 14, but existing supply voltage VDD can't meet the demands.
Fig. 3 has shown charge pump system schematic diagram in another embodiment in the prior art.As shown in Figure 3, similar with Fig. 2, described charge pump system comprises crystal oscillator unit 20, overlapping shaping unit 22, clock drive unit 24 and charge pump unit 26.Especially, the described charge pump system among Fig. 3 also comprises power supply voltage regulation unit 25, is used for the output supply voltage VDDQ_R after adjusting with primary power voltage VDDQ, offers clock drive unit 24.The supply voltage VDD that supply voltage VDDQ_R in the charge pump system shown in Figure 3 is compared in the charge pump system shown in Figure 2 has bigger magnitude of voltage, and bigger electric current can be provided.
But, because clock drive unit 24 still is used to drive two class clock signals (first kind clock signal and the second type clock signal), also can cause power consumption bigger inevitably, therefore power supply voltage regulation unit 25 needs to provide big electric current to clock drive unit 24, this needs the conducting resistance of power supply voltage regulation unit 25 smaller usually, in order to realize less conducting resistance, generally adopt the power supply voltage regulation unit 25 of big breadth length ratio, this can cause the size of power supply voltage regulation unit 25 bigger.
Simultaneously, because clock drive unit 24 can extract the electric currents of power supply voltage regulation units 25 in a large number, the tertiary voltage VDDQ_R that power supply voltage regulation unit 25 is exported can descend to some extent, and this can cause the clock high level of clock drive unit 24 outputs to reduce, and can influence the efficient of charge transfer in the charge pump system; The charging clock is lower, then can cause charging clock high level to be lower than the switching voltage of NMOS pipe, makes the charge pump system can't operate as normal.
Summary of the invention
The problem that the present invention solves is charge efficiency and the low problem of efficiency of transmission in the existing charge pump system.
For addressing the above problem, the invention provides a kind of charge pump system, comprising: charge pump unit; The clock drive unit that is connected with described charge pump unit, described clock drive unit has: by the first clock driver element of first supply voltage control, strengthen the electric current of the first kind clock signal that is obtained and export described charge pump unit to; By the voltage-controlled second clock driver element of second source, strengthen the electric current of the second type clock signal that is obtained and export described charge pump unit to; The power supply voltage regulation unit is used to adjust second source voltage, to obtain first supply voltage.
Alternatively, described charge pump system also comprises: be subjected to the crystal oscillator unit of the 3rd supply voltage control, produce initial clock signal; The overlapping shaping unit that is connected with described crystal oscillator unit, be used for the initial clock signal that described crystal oscillator unit the produces shaping that overlaps, output first kind clock signal is to the described first clock driver element and export the second type clock signal to described second clock driver element.
Alternatively, described first kind clock signal is the charging clock signal, and the described second type clock signal is a transmit clock signal.
Alternatively, the first kind clock signal of described first clock driver element output is a two-phase charging clock signal, and the second type clock signal of described second clock driver element output is the two-phase transmit clock signal.
Alternatively, the range of voltage values of described first supply voltage is 2.5 volts to 3.6 volts, and the range of voltage values of described second source voltage is 2.5 volts to 5.5 volts.
The opposing party of the present invention is bright also to provide a kind of memory that comprises above-mentioned charge pump system.
Compared with prior art, the present invention has the following advantages: will be used to export first clock driver element of first kind clock signal (clock signal of promptly charging) and the discrete setting of second clock driver element that is used to export the second type clock signal (being transmit clock signal), wherein the first clock driver element is controlled by first supply voltage, reduce current loading, can improve charge efficiency; The second clock driver element because second source voltage is higher, can improve efficiency of transmission by the second source voltage control.
Description of drawings
Fig. 1 has shown the circuit theory diagrams of charge pump system in the prior art;
Fig. 2 has shown charge pump system schematic diagram in one embodiment in the prior art;
Fig. 3 has shown charge pump system schematic diagram in another embodiment in the prior art;
Fig. 4 has shown the schematic diagram in charge pump system one execution mode of the present invention;
Fig. 5 has shown and the invention provides a kind of charge pump system schematic diagram in one embodiment.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, prior art is used for the charge pump system of memory, be to utilize to be subjected to the same clock drive unit of same supply voltage control to produce charging clock signal and transmit clock signal, can cause the reduction of charge efficiency and/or efficiency of transmission.
At the problems referred to above, the invention provides a kind of charge pump system.With reference to figure 4, shown the schematic diagram in charge pump system one execution mode of the present invention.
As shown in Figure 4, described charge pump system comprises charge pump unit 36 and the clock drive unit that is connected with described charge pump unit, described clock drive unit comprises the first clock driver element 341 and second clock driver element 342, wherein, the first clock driver element 341 is controlled by first supply voltage, is used to carry out export first kind clock signal after the signal enhancement process; Second clock driver element 342 is subjected to the second source voltage control, is used to carry out export the second type clock signal after the signal enhancement process.In addition, in actual applications, described first supply voltage is adjusted the back by power supply voltage regulation unit 35 with described second source voltage and is produced.
Compare with the charge pump system that utilizes the same clock drive unit that is subjected to same supply voltage control to produce charging clock signal and transmit clock signal in the prior art, charge pump system provided by the invention, to be used to export first clock driver element of first kind clock signal (clock signal of promptly charging) and the discrete setting of second clock driver element that is used to export the second type clock signal (being transmit clock signal), wherein the first clock driver element is by the special-purpose control of first supply voltage, load current can be reduced relatively, charge efficiency can be improved; The second clock driver element because second source voltage is higher, can improve efficiency of transmission by the special-purpose control of second source voltage.
Fig. 5 demonstration the invention provides a kind of charge pump system schematic diagram in one embodiment.As shown in Figure 5, in the present embodiment, described charge pump system comprises: crystal oscillator unit 30, overlapping shaping unit 32, the first clock driver element 341, second clock driver element 342, power supply voltage regulation unit 35 and charge pump unit 36.
Overlapping shaping unit 32, be connected with crystal oscillator unit 30, controlled by supply voltage VDD, be used for the initial clock signal clk that crystal oscillator unit 30 the produces shaping that overlaps, output charging clock signal clk 1_L, CLK3_L to the first clock driver element 341 and output transmit clock signal CLK2_L, CLK4_L are to second clock driver element 342, wherein, the duty ratio of the duty ratio of charging clock signal clk 1_L, CLK3_L and transmit clock signal CLK2_L, CLK4_L is inequality.Charging clock signal clk 1_L and transmit clock signal CLK2_L are the non-overlapped clock signal of two-phase, and charging clock signal clk 3_L and transmit clock signal CLK4_L are the non-overlapped clock signal of two-phase.Here, the non-overlapped clock signal of so-called two-phase refers to that specifically the phase place of described two clock signals does not overlap.
The first clock driver element 341, controlled by supply voltage VDDQ_R, be used for charging clock signal clk 1, CLK3 that after behind the charging clock signal clk 1_L, the CLK3_L that receive overlapping shaping unit 32 it being carried out signal enhancement process output has bigger current value.In the present invention, described supply voltage VDDQ_R utilizes power supply voltage regulation unit 35 that supply voltage VDDQ is carried out voltage stabilizing and handles the back generation, the ripple of described supply voltage VDDQ_R is less, it has kept the high-voltage value of supply voltage VDDQ, therefore also have good stable simultaneously, make the voltage of charging clock signal clk 1 that the clock driver element 341 of winning provided, CLK3 higher.Simultaneously, in the present invention, the first clock driver element 341 is exclusively used in provides the charging of charge pump unit 36 clock signal.Like this, load current by the first clock driver element 341 of supply voltage VDDQ_R control just can reduce, charging clock signal clk 1, CLK3 can obtain bigger electric current, can charge into more electric charge for for example electric capacity in the charge pump unit 36, corresponding raising charge efficiency.
Generally, the range of voltage values of supply voltage VDDQ is 2.5 volts to 5.5 volts, and the supply voltage VDDQ_R after voltage stabilizing is handled is 2.5 volts to 3.6 volts.
Second clock driver element 342, controlled by supply voltage VDDQ, be used for transmit clock signal CLK2, CLK4 that after behind the transmit clock signal CLK2_L, the CLK4_L that receive overlapping shaping unit 32 it being carried out signal enhancement process output transmission has bigger current value.In the present invention, second clock driver element 342 is exclusively used in the transmit clock signal that charge pump unit 36 is provided.Like this, load current by the second clock driver element 342 of supply voltage VDDQ control just can reduce, transmit clock signal CLK2, CLK4 can obtain bigger electric current, the switch in the conducting charge pump unit better 36 (for example NMOS pipe), corresponding raising efficiency of transmission.
Specifically, and simultaneously with reference to figure 1, with transmit clock signal CLK2, CLK4 respectively as the transfer clock of control first K switch 1 and second switch K2 among Fig. 1, with charging clock signal clk 1, CLK3 respectively as among Fig. 1 to the charging clock of first capacitor C 1, second capacitor C 2.
During charge pump unit work, when transmit clock signal CLK2 is high level, 1 conducting of first K switch; When charging clock signal clk 1 was low level, power supply Vin was by 1 pair first capacitor C of first K switch, 1 charging of conducting, and after charging finished, the top crown voltage of first capacitor C 1 was Vin; And when charging clock signal clk 1 was high level, the bottom crown voltage of first capacitor C 1 was V, because electric capacity has the character that the two poles of the earth voltage difference can not be suddenlyd change, this moment, the top crown voltage jump of first capacitor C 1 was V+Vin.Afterwards, when transmit clock signal CLK4 is high level, second switch K2 conducting; When charging clock signal clk 3 was low level, the top crown voltage V+Vin on first capacitor C 1 charged to second capacitor C 2 by the second switch K2 of conducting, and after charging finished, the top crown voltage of second capacitor C 2 was V+Vin; And when charging clock signal clk 3 was high level, the bottom crown voltage of second capacitor C 2 was V, because electric capacity has the character that the two poles of the earth voltage difference can not be suddenlyd change, this moment, the top crown voltage jump of second capacitor C 2 was 2V+Vin.Like this, electric charge has just passed to the right from the left side, along with the increase of charge pump progression, electric charge just continuously from the power source transition to the output, thereby obtain having the output voltage V out of high-voltage value.
The present invention also provides a kind of memory, described memory includes aforesaid charge pump system, described charge pump system comprises charge pump unit and the clock drive unit that is connected with described charge pump unit, and described clock drive unit comprises by the first clock driver element of first supply voltage control with by the voltage-controlled second clock driver element of second source.Because in the present invention,, can improve charge efficiency and efficiency of transmission, strengthen the memory property of memory described first clock driver element and the discrete setting of described second clock driver element.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (6)
1. a charge pump system is characterized in that, comprising:
Charge pump unit;
The clock drive unit that is connected with described charge pump unit, described clock drive unit has:
By the first clock driver element of first supply voltage control, strengthen the electric current of the first kind clock signal that is obtained and export described charge pump unit to;
By the voltage-controlled second clock driver element of second source, strengthen the electric current of the second type clock signal that is obtained and export described charge pump unit to;
The power supply voltage regulation unit is used to adjust second source voltage, to obtain first supply voltage.
2. charge pump system as claimed in claim 1 is characterized in that, also comprises:
Be subjected to the crystal oscillator unit of the 3rd supply voltage control, produce initial clock signal;
The overlapping shaping unit that is connected with described crystal oscillator unit, be used for the initial clock signal that described crystal oscillator unit the produces shaping that overlaps, output first kind clock signal is to the described first clock driver element and export the second type clock signal to described second clock driver element.
3. charge pump system as claimed in claim 1 is characterized in that, described first kind clock signal is the charging clock signal, and the described second type clock signal is a transmit clock signal.
4. charge pump system as claimed in claim 3, it is characterized in that, the first kind clock signal of described first clock driver element output is a two-phase charging clock signal, and the second type clock signal of described second clock driver element output is the two-phase transmit clock signal.
5. charge pump system as claimed in claim 1 is characterized in that, the range of voltage values of described first supply voltage is 2.5 volts to 3.6 volts, and the range of voltage values of described second source voltage is 2.5 volts to 5.5 volts.
6. one kind comprises the memory as each described charge pump system in the claim 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102039629A CN102280997A (en) | 2010-06-09 | 2010-06-09 | Charge pump system and memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102039629A CN102280997A (en) | 2010-06-09 | 2010-06-09 | Charge pump system and memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102280997A true CN102280997A (en) | 2011-12-14 |
Family
ID=45106226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010102039629A Pending CN102280997A (en) | 2010-06-09 | 2010-06-09 | Charge pump system and memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102280997A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106712498A (en) * | 2017-01-09 | 2017-05-24 | 格科微电子（上海）有限公司 | Voltage stabilization charge pump device and control method thereof |
| CN112636587A (en) * | 2020-12-30 | 2021-04-09 | 深圳市芯天下技术有限公司 | Charge pump circuit and nonvolatile memory |
| CN114915163A (en) * | 2022-04-06 | 2022-08-16 | 杭州士兰微电子股份有限公司 | Charge pump circuit and control method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001157437A (en) * | 1999-11-25 | 2001-06-08 | Hitachi Ltd | Charge pump type booster circuit |
| JP2005352497A (en) * | 2005-06-17 | 2005-12-22 | Rohm Co Ltd | Power source unit for driving display device, and display device |
| WO2009028394A1 (en) * | 2007-08-30 | 2009-03-05 | Sanyo Electric Co., Ltd. | Charge pump type booster circuit |
-
2010
- 2010-06-09 CN CN2010102039629A patent/CN102280997A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001157437A (en) * | 1999-11-25 | 2001-06-08 | Hitachi Ltd | Charge pump type booster circuit |
| JP2005352497A (en) * | 2005-06-17 | 2005-12-22 | Rohm Co Ltd | Power source unit for driving display device, and display device |
| WO2009028394A1 (en) * | 2007-08-30 | 2009-03-05 | Sanyo Electric Co., Ltd. | Charge pump type booster circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106712498A (en) * | 2017-01-09 | 2017-05-24 | 格科微电子（上海）有限公司 | Voltage stabilization charge pump device and control method thereof |
| CN112636587A (en) * | 2020-12-30 | 2021-04-09 | 深圳市芯天下技术有限公司 | Charge pump circuit and nonvolatile memory |
| CN112636587B (en) * | 2020-12-30 | 2022-03-08 | 芯天下技术股份有限公司 | Charge pump circuit and nonvolatile memory |
| CN114915163A (en) * | 2022-04-06 | 2022-08-16 | 杭州士兰微电子股份有限公司 | Charge pump circuit and control method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101369775B (en) | High efficiency charge pump DC to DC converter circuits and methods | |
| CN104205594B (en) | Charge pump circuit and its operating method comprising multi-gated transistor | |
| US8294509B2 (en) | Charge pump systems with reduction in inefficiencies due to charge sharing between capacitances | |
| CN102457179B (en) | Electronic pump with low noise and high output voltage and current | |
| CN101303832B (en) | Power supply circuit, liquid crystal drive device, liquid crystal display device | |
| CN102629822B (en) | Charge pump and liquid crystal display screen driving chip | |
| CN101159412A (en) | Electronic device including boosting circuit | |
| CN208190514U (en) | Multi stage charge pump and IC chip | |
| CN105513525A (en) | Shifting register unit, shifting register, grid drive circuit and display device | |
| CN109192173A (en) | Gate driving circuit and its driving method, display device | |
| US20130257522A1 (en) | High input voltage charge pump | |
| CN102290981A (en) | Charge pump circuit and flash memory adopting same | |
| CN102280127B (en) | Clock generation circuit and charge pump system | |
| US20040155699A1 (en) | Capacitor charge sharing charge pump | |
| CN102237788B (en) | Charge pump circuit and memory | |
| CN103107695A (en) | Charge pump circuit and memorizer | |
| CN103036411A (en) | Charge pump circuit | |
| CN102456395B (en) | Electronic pumps for low supply voltages | |
| CN201629731U (en) | Bootstrap circuit with reinforced low voltage | |
| CN106787691A (en) | Charge pump circuit, charge pump system and memory | |
| CN102280997A (en) | Charge pump system and memory | |
| CN201237887Y (en) | Negative pressure generation circuit of LCD module | |
| CN104091613B (en) | Charge pump system and memory | |
| CN108092501A (en) | Booster circuit and the nonvolatile memory for possessing the booster circuit | |
| CN101005236A (en) | Booster circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20131225 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20131225 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20111214 |