CN102270444B - Data flow control and frame buffer device of video processing chip - Google Patents
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Abstract
The invention provides a data flow control and frame buffer device of a video processing chip, which comprises an input buffer pool for receiving and buffering external data flow; an output buffer pool for realizing the output of the processed data stream; and the control module is used for controlling the input and the output of the data stream in real time, controlling the reading and writing of the frame buffer and converting the video frame rate of the data stream. The input buffer pool chip is connected with an OSD control module and a video input processing module, the output buffer pool chip is connected with a video output processing module, and the control module is connected with a frame buffer outside the chip. The input buffer pool and the output buffer pool both contain a plurality of FIFO structure asynchronous buffers, the control module comprises an arbitration module, an address management module and a display controller, the arbitration module is composed of a finite state converter, the input and output of each path of data stream are controlled in real time by adopting a direct jump strategy and a priority dynamic adjustment strategy, the display controller adopts a burst transmission mode, and the frame buffer adopts an SDRAM or DDR SDRAM memory.
Description
Technical field
The present invention relates to a kind of data flow con-trol and frame buffer device, specifically, relate in a kind of video frequency processing chip, realization is to the real-time control of multiplex data stream I/O with to frame buffer read-write control, and video frequency processing chip data flow con-trol and the frame buffer device of realizing video frame rate translation function.
Background technology
In DTV, HDTV real-time video aftertreatment chip, need to process in real time a large amount of video signal data and screen display (OSD) data.For example, for SD vision signal 720*576@50Hz, need to process the data throughput that is greater than 300Mb/s, and the data volume of a two field picture is greater than 800K byte.In addition, data are single channel not often, but multiple signals I/O depositing.For example, in typical application scenario, there are osd signal and Y, U, V tri-tunnel vision signals.
In order to solve in above-mentioned video frequency processing chip multiple signals and to deposit, and large two problems of data traffic, in fact adopted the mode of ram in slice and chip external memory collaborative process.High-speed RAM in sheet is as the impact damper of multi-channel video signal, and the buffering for multi-path video data, prevents loss of data; And storer outside sheet is as frame buffer (or be called " video memory "), for buffer memory video processing unit, will process or processed frame data.
For the consideration of cost and chip power-consumption, frame buffer often adopts the SDRAM (also can adopt speed DDR SDRAM, DD2 SDRAM etc. faster) outside sheet, and does not adopt the RAM in sheet to realize.RAM in sheet has the features such as read or write speed is fast, with high costs.Frame buffer needs frame data amount to be processed large, if adopt the RAM in sheet, must take a large amount of chip areas, increases chip cost.In addition, on-chip memory is also the main source of chip power-consumption.Therefore, the SDRAM outside employing sheet can effectively reduce the power consumption of chip.
Adopt the SDRAM outside sheet also to exist the input/output port of another one problem: SDRAM to only have one as frame buffer, and the data stream that chip is processed have more than one group.Current signal to be processed has four group data streams, i.e. osd signal, brightness signal Y, and carrier chrominance signal U and V.The existing input of every group data stream also has output, has 8 circuit-switched data streams to need to process.The time of each circuit-switched data stream access sdram must strictly be controlled, otherwise can clash, overflow, the intolerable mistake such as loss of data.
In addition, video input and output format are often different, make the frame per second of video not necessarily identical.In order to meet the transmission requirement of system input and output interface, must solve the video data transmitting problem under frame per second different situations.
Summary of the invention
For above deficiency, the invention provides in a kind of video frequency processing chip, realization is to the real-time control of multiplex data stream I/O with to frame buffer read-write control, and video frequency processing chip data flow con-trol and the frame buffer device of realizing video frame rate translation function, it comprises: realize and receive the also input Buffer Pool of buffer memory external data stream; Realize the output Buffer Pool of the data stream output after processing; Realization is controlled in real time and frame buffer is read and write to control the input of data stream, output, and realizes the control module that the video frame rate of data stream is changed.In described input Buffer Pool sheet, connect OSD control module and video input processing module, connect video output processing module in described output Buffer Pool sheet, described control module sheet connects frame buffer outward.
Described input Buffer Pool contains a plurality of fifo structure asynchronous buffer devices, it comprises the OSD input buffer being connected with OSD control module, and the Y-signal input buffer being connected with video input processing module respectively, U signal input buffer and V signal input buffer.
Described output Buffer Pool contains a plurality of fifo structure asynchronous buffer devices, and it comprises OSD output buffer, Y-signal output buffer, U signal output buffer and the V signal output buffer being connected with video output processing module.
Described control module comprises realizing carries out the arbitration modules of control effectively in real time to the input and output of each circuit-switched data stream; Realization is to the response of the read-write requests of arbitration modules and calculating and provide read/write address to video memory controller, and by three frame video datas in management frames buffer, realizes the address administration module of video frame rate conversion; Realization reads and writes to the frame buffer of the outer connection of sheet with it the video memory controller of controlling.
Described arbitration modules is comprised of a finite state interpreter, and it adopts direct jump strategy and priority dynamically to adjust strategy and realizes the effective control to the input and output of each circuit-switched data stream.
Described video memory controller adopts burst transfer mode.
Described frame buffer adopts common SDRAM or DDRSDRAM storer.
Beneficial effect of the present invention:
(1) arbitration modules has adopted direct jump strategy and priority dynamically to adjust strategy and has realized controlling effectively in real time the input and output of each circuit-switched data stream, can make full use of the data throughput capabilities of video memory, dynamically adjust the access privileges of each data path to video memory, the situation of effectively having avoided data buffering to overflow, therefore the in the situation that of the equal data throughput capabilities of frame buffer, reduced the degree of depth of data buffering, the shared area of data buffering while having reduced that chip is realized.
(2) address administration module provides simple video frame rate translation function, can realize high frame per second and transfer the video playback that low frame per second or low frame per second transfer high frame per second to.
(3) video memory controller adopts the burst transfer mode of optimizing, and has not only saved unnecessary refresh operation and random read-write function etc., has simplified controller architecture simultaneously, has improved data throughput.
(4) input Buffer Pool and output Buffer Pool all contain a plurality of fifo structure asynchronous buffer devices, make input clock and the output clock of each impact damper can be completely asynchronous, for other processing modules of processing system for video provide data-interface flexibly, the design of asynchronous buffer device also makes the present invention incessantly can be used for the Video Data Storage in Video processing, more generally can be used in the signal processing module that needs large throughput as data storage cell.
Accompanying drawing explanation
Fig. 1 is the system chart of video frequency processing chip data flow con-trol of the present invention and frame buffer device;
Fig. 2 is the implementation pattern schematic diagram of arbitration mechanism of the present invention;
Fig. 3 is that arbitration mechanism priority of the present invention is dynamically adjusted tactful implementation pattern schematic diagram;
Fig. 4 is the structured flowchart of address administration module of the present invention;
Fig. 5 is the storage organization schematic diagram of frame buffer of the present invention;
Fig. 6 is the read operation mode schematic diagram of address administration module of the present invention to frame of video;
Fig. 7 is the write operation mode schematic diagram of address administration module of the present invention to frame of video;
Fig. 8 is the implementation structure schematic diagram of asynchronous buffer device of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further elaborated.
As shown in Figure 1, video frequency processing chip data flow con-trol of the present invention and frame buffer device 10 comprise input Buffer Pool 12, output Buffer Pool 13 and control module 11, in 12 of described input Buffer Pools, connect OSD control module 14 and video input processing module 15, in 13 of described output Buffer Pools, connect video output processing module 16,11 outer frame buffers 17 that connect of described control module.Wherein, input Buffer Pool 12 is realized and being received and buffer memory external data stream, output Buffer Pool 13 is realized the data stream output after processing, control module 11 realizes to be controlled in real time and frame buffer 17 is read and write to control the input of data stream, output, and realizes the video frame rate of data stream is changed.
Wherein, described input Buffer Pool 12 contains a plurality of fifo structure asynchronous buffer devices, it comprises the OSD input buffer 121 being connected with OSD control module, and the Y-signal input buffer 122 being connected with video input processing module respectively, U signal input buffer 123 and V signal input buffer 124, it is as video inputs.
Described output Buffer Pool 13 contains a plurality of fifo structure asynchronous buffer devices, it comprises OSD input buffer 131, Y-signal input buffer 132, U signal input buffer 133 and the V signal input buffer 134 being connected with video output processing module, and it is as video output terminals.
Described control module 11 comprises realizing carries out the arbitration modules 111 of control effectively in real time to the input and output of each circuit-switched data stream; Realization is to the response of the read-write requests of arbitration modules and calculating and provide read/write address to video memory controller 112, and by three frame video datas in management frames buffer, realizes the address administration module of video frame rate conversion; Realization reads and writes to the frame buffer of the outer connection of sheet with it the video memory controller 113 of controlling.Described arbitration modules 111 is comprised of a finite state interpreter, it adopts direct jump strategy and priority dynamically to adjust strategy and realizes the effective control to the input and output of each circuit-switched data stream, described video memory controller 113 adopts burst transfer mode, and described frame buffer adopts common SDRAM or DDR SDRAM storer.
Below in conjunction with accompanying drawing, each functional module is described in detail:
One, controller
Controller 11 is comprised of arbitration modules 111, address administration module 112,113 3 submodules of video memory controller.Wherein, arbitration modules 111 is mainly comprised of a finite state interpreter, and has adopted direct jump strategy and priority dynamically to adjust strategy, realizes the effective control to the input and output of each circuit-switched data stream, the situation of avoiding data buffering to overflow; A frame osd data in address administration module 112 management frames buffers 17 and three frame video datas are realized video frame rate translation function simultaneously; Video memory controller 113 has been realized the control sequential to frame buffer, and it is directly connected with the frame buffer 17 outside sheet.
1,1 arbitration modules
Arbitration modules 111 has realized arbitration mechanism of the present invention, and it has adopted direct jump strategy and priority dynamically to adjust strategy, has realized the effective control to the input and output of each circuit-switched data stream, the situation of simultaneously avoiding data buffering to overflow.
Arbitration modules 111 is mainly comprised of a finite state interpreter, when system completes after the initial work of reset and frame buffer 17, state machine enters idle condition, and arbitration modules 111, according to the request of different data I/O, determines to enter or be withdrawn into different data manipulation states.Data manipulation state in current typical case application has 8: the I/O of osd data, Y-signal, U signal and V signal, certainly, the present invention also can be for the I/O state of the signal of other type.
Figure 2 shows that the implementation pattern schematic diagram of arbitration mechanism, and expressing the direct jump strategy and the priority that adopt when arbitration mechanism exit status, Fig. 3 dynamically adjusts strategy, for simplified characterization, to current 8 or more data manipulation state, only taking out S1-S4 one of four states is that representative is described.Their original priority is S1-S2-S3-S4 from high to low, their each operation requests that will produce to arbitration modules 111, and arbitration modules can be carried out response request according to certain rule, because the input/output end port of frame buffer 17 only has one, so arbitration modules can only respond an operation requests at synchronization, its arbitration mechanism is as follows:
(1) enter and exit mode of operation: system can detect the state of each impact damper in input Buffer Pool 12 and output Buffer Pool 13, thereby produce different data operation request, if arbitration modules at a time the clock cycle receive only the request of a data processing, directly enter corresponding mode of operation; If receive the request of a plurality of data processings simultaneously,, according to priority height, the request that first processing priority is high, the higher request of processing priority, enter corresponding mode of operation.For example, suppose that S2 represents the input state of Y-signal, S3 represents the input state of U signal, when moderator receives the operation requests of S2 and S3 simultaneously, because the priority ratio S3 of S2 is high, so S2 operation requests meets with a response, system is written to the data in Y-signal input buffer in frame buffer, complete after the operation of certain state, system will dynamically be adjusted strategy according to direct jump strategy and priority and exit this state.
(2) directly jump strategy and priority are dynamically adjusted strategy (as shown in Figure 3): 1) directly jump strategy refers to when exiting some data manipulation states, system is not got back to idle condition at once, and can determine whether and then by arbitration modules 111, determined whether the data operation request that has other directly to jump to this mode of operation; When not there is not other data operation request, just can get back to idle condition.2) priority is dynamically adjusted the priority that strategy refers to system and is not fixed as S1-S2-S3-S4, and can when exiting certain mode of operation, dynamically adjust at every turn, then according to the priority after dynamically adjusting, carries out redirect.For example, suppose that system has just completed the operation of S3 state, then system can dynamically be adjusted priority level, the priority of S3 can be reduced to minimum, and the original S4 lower than S3 priority can obtain the highest priority, is then by the S1 of original order and S2, be that priority is adjusted into S4-S1-S2-S3 from high in the end, again for example, if just completed the mode of operation of S2, priority is dynamically adjusted into S3-S4-S1-S2.
Above-mentioned adopted direct jump strategy and priority are dynamically adjusted strategy, although make the design of arbitration modules more complicated, can effectively alleviate data volume when larger, the tight slightly situation of handling capacity that system may occur.If there is no direct redirect mechanism, complete after the state of a certain operation, must get back to idle condition, this need to spend the time of a clock period, and directly redirect mechanism can dispense this clock period, maximally utilise time resource, thereby alleviated the tight slightly situation of handling capacity.
1.2 address administration modules
Address administration module 112, except the basic address computation function completing, also, by three frame video datas in management frames buffer 17, realizes video frame rate translation function.
Fig. 4 represents the formation of address administration module 112, and it is present in controller 11, steering logic unit 1121, base address register 1122 and address counter 1123, consists of.The read-write requests of its response arbitration modules 111, calculates and provides read/write address to video memory controller 113, thereby having assisted corresponding read-write operation.
For the ease of introducing the frame rate conversion function of address administration module 112, first simply introduce the storage organization of frame buffer 17 below, the handling capacity of frame buffer 17 is also one of the major reason that affects the handling capacity of system, frame buffer generally adopts the storeies such as SDRAM and DDR SDRAM, if the handling capacity of the storer adopting can not meet the requirement of message transmission rate, in the time of can making video playback because obliterated data causes watching.Figure 5 shows that the storage organization of the frame buffer 17 outside sheet, it is storing the osd data (osd data frame 171) of a frame and the video signal data of three frames (video the first frame 172, video the second frame 173 and video the 3rd frame 174), the frame data amount of different video formats is different, so will choose enough large storer as frame buffer according to application demand.
The frame per second of the video of input and output may be not identical, and this is because the video format of input and output is not necessarily identical.At input end, system need to be synchronizeed with the frame per second of video input processing module 15; At output terminal, system need to be synchronizeed with the frame per second of video output processing module 16, and this just needs system to realize the function of video frame rate conversion.
Three frame video datas in address administration module management frame buffer, have realized this function by certain mechanism, and its implementation is as follows:
The read operation of frame of video (as shown in Figure 6): when system reset, read pointer PR points to the first frame (being PR=1), reads the video data of the first frame in frame buffer 17 in output Buffer Pool 13, completes the output of video data; When running through the first frame, the state of the current write pointer PW of address administration module check, still points to the second frame (PW=2) if be checked through write pointer PW, return to the data of reading again first frame, otherwise (being PW ≠ 2) starts to read the data of the second frame; Read the second frame and also analogize with the situation of reading the 3rd frame,, when running through a certain frame, if be checked through write pointer PW, still point to next frame, return and read again once original those frame data, otherwise read next frame data; So circulation is gone down, and completes the read operation to frame of video.
The write operation of frame of video (as shown in Figure 7): similar to the read operation of frame, during system reset, write pointer PR points to the second frame (being PW=2), and the data in input Buffer Pool 12 are written in the second frame of frame buffer 17, completes the input of video data; When writing the second frame, the state of address administration module check current read pointer PR, points to the 3rd frame (being PR=3) if be checked through read pointer PR, return to the data of writing again second frame, otherwise (PR ≠ 3) starts to write the data of the 3rd frame; Write the 3rd frame and also can analogize with the situation of writing the first frame,, when writing a certain frame, if be checked through read pointer PR, still point to next frame, return and write again once original that frame, otherwise write next frame data; So circulation is gone down, and can complete the write operation to frame of video.
By above-mentioned frame of video read-write operation, circulation is always gone down, can realize the function of video frame rate conversion, in fact this function is exactly when input frame rate is higher than output frame rate, carry out frame losing processing, and when input frame rate is lower than output frame rate, some frames is repeated to output and process.
Two, input Buffer Pool 12 is comprised of OSD input buffer 121, Y-signal input buffer 122, U signal input buffer 123 and V signal input buffer 124, and it realizes the buffering to input traffic, avoids loss of data.All impact dampers are all to consist of asynchronous FIFO, input clock and the output clock of buffering can be completely asynchronous, and their degree of depth is all 256 bytes, when the data of setting in impact damper are less than 32 bytes here, it is " sky " state, and be " expiring " state while being greater than 256-32=214 byte, system according to " sky " of impact damper or " expiring " condition judgement whether reading and writing data in frame buffer 17.
Three, output Buffer Pool 13 is comprised of OSD input buffer 131, Y-signal input buffer 132, U signal input buffer 133 and V signal input buffer 134, and it realizes the buffering to output stream, avoids loss of data.All impact dampers are all to consist of asynchronous FIFO, input clock and the output clock of buffering can be completely asynchronous, and their degree of depth is all 256 bytes, when the data of setting in impact damper are less than 32 bytes here, it is " sky " state, and be " expiring " state while being greater than 256-32=214 byte, system according to " sky " of impact damper or " expiring " condition judgement whether reading and writing data in frame buffer 17.
At video inputs, data are input to input Buffer Pool 12 from video output processing module 15 and OSD control module 14 incessantly, in order to prevent from inputting Buffer Pool 12 (OSD input buffer 121, Y-signal input buffer 122, U signal input buffer 123 and V signal input buffer 124) in data from overflow, must make to input all impact dampers maintenances state of normal " sky " (being less than 32 bytes) in Buffer Pool 12, when impact damper being detected for " non-NULL " (being more than or equal to 32 bytes) state, the data of impact damper are written in frame buffer 17 on corresponding frame address.This process is continuously and at a high speed, and the time that data stop at input Buffer Pool 12 is very of short duration, can think that data are from module 15 and 14, to be written to frame buffer 17 continuously and at high speed.
At video output terminals, situation and video inputs are similar, data continuously output to video output processing module 16 from output Buffer Pool 13, in order to prevent from exporting Buffer Pool 13 (OSD input buffer 131, Y-signal input buffer 132, U signal input buffer 133 and V signal input buffer 134) because emptying, data cause output frame to interrupt, the situation of " falling frame ", all impact dampers that must make to export in Buffer Pool keep normal " expiring " (being greater than 214 bytes) state, when impact damper being detected for " non-full " state (be less than or equal 214 bytes), video memory controller 17 at once from frame buffer 17 reading out data in output Buffer Pool 13.
In above-mentioned input Buffer Pool 12 and output Buffer Pool 13, all contain a plurality of impact dampers, input and output buffering for data stream, avoid loss of data, they are all fifo structure asynchronous buffer devices, input clock and output clock can be completely asynchronous, and all impact dampers are all the degree of depth of 256 bytes, but width is according to actual data stream situation and different, there are 32 enter 32 and go out, also have 8 to enter 32 and go out.
Figure 8 shows that the implementation of these impact dampers: in order to judge " sky " of impact damper and the state of " expiring ", need to calculate the data length in impact damper, this length is that control module 11 draws by calculating the difference of the address of read pointer rd sensing and the address of write pointer wr sensing, but, because the read and write operation of impact damper is operated under different clock frequencies, asynchronous carrying out, so can not directly subtract each other read-write pointer.As shown in Figure 1, the impact damper for input in Buffer Pool 12, write operation need to the clock synchronous of osd controller 14 and video input processing module 15, and read operation need to the clock synchronous of control module 11; Impact damper for output in Buffer Pool 13, write operation need to the clock synchronous of control module 11, and read operation need to the clock synchronous of video output processing module 16.Because reading and writing asynchronous operation, if the address that write pointer wr is pointed to directly deducts the address that read pointer rd points to, may occur metastable situation, cause miscount.
In order to solve the synchronous problem of above-mentioned impact damper clock zone, for the impact damper in input Buffer Pool 12, the present invention is first synchronized to write address the clock zone (being synchronized to control module 11) of reading address, then write address is directly deducted and reads address, thereby draws the data length in impact damper; For the impact damper in output Buffer Pool 13, first reading address synchronization to the clock zone (being synchronized to control module 11) of write address, then write address is directly deducted and reads address, thereby draw the data length in impact damper.
After control module 11 has been the calculating of the data length in impact damper, can judge " sky " of impact damper and the state of " expiring ", the input and output that complete data stream are controlled.Above narrated, when the impact damper in input Buffer Pool being detected is " non-NULL " (being more than or equal to 32 bytes) state, the data of handle are written in frame buffer; When the impact damper of output in Buffer Pool being detected for " non-full " state (be less than or equal 214 bytes), controller from frame buffer reading out data in output Buffer Pool.32 bytes of usining are to using 32 bytes as a burst read operation or write operation as basis for estimation because of controller burst transfer of the present invention.If select other burst transfer length, can change empty full decision threshold and realize data flow con-trol function.
The foregoing is only better embodiment of the present invention, the present invention is not limited to above-mentioned embodiment, in implementation process, may there is local small structural modification, if various changes of the present invention or modification are not departed to the spirit and scope of the present invention, and within belonging to claim of the present invention and equivalent technologies scope, the present invention is also intended to comprise these changes and modification.
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| CN102497527B (en) | 2011-12-16 | 2013-11-27 | 杭州海康威视数字技术股份有限公司 | Multi-processor video processing system and video image synchronous transmission and display method thereof |
| CN102665073B (en) * | 2012-04-25 | 2015-09-09 | 北京瀚景锦河科技有限公司 | For forwarding the apparatus and method of SDI audio, video data |
| CN102801936B (en) * | 2012-08-02 | 2015-04-15 | 东莞中山大学研究院 | Method for realizing on-screen display |
| CN104125424B (en) * | 2014-08-06 | 2017-06-06 | 中航华东光电（上海）有限公司 | A kind of high speed based on FPGA, variable frame video video memory method for designing |
| CN108108148B (en) * | 2016-11-24 | 2021-11-16 | 舒尔电子(苏州)有限公司 | Data processing method and device |
| CN106601160B (en) * | 2016-12-14 | 2020-04-14 | 昆山龙腾光电股份有限公司 | Refresh rate conversion device and method and display device |
| CN107040784B (en) * | 2017-03-22 | 2020-12-15 | 深圳市中航世星科技有限公司 | Video buffering processing method, system and device |
| CN109766285A (en) * | 2019-01-10 | 2019-05-17 | 中国科学院长春光学精密机械与物理研究所 | A burst mode SDRAM access control system and control method |
| CN110390626A (en) * | 2019-07-02 | 2019-10-29 | 深兰科技（上海）有限公司 | A kind of image processing method and device of convolutional neural networks |
| CN111182306B (en) * | 2020-01-04 | 2021-12-28 | 苏州浪潮智能科技有限公司 | Video extraction method, system, terminal and storage medium for video compression |
| CN111813717B (en) * | 2020-06-10 | 2022-03-01 | 烽火通信科技股份有限公司 | Device and method for data frame storage switching |
| CN111885410B (en) * | 2020-07-30 | 2022-08-30 | 京东方科技集团股份有限公司 | Image data processing device, method and display device |
| CN112511861B (en) * | 2020-12-03 | 2022-05-03 | 威创集团股份有限公司 | Low-delay video transmission method and system and storage medium thereof |
| CN115802095B (en) * | 2023-01-06 | 2023-04-18 | 北京象帝先计算技术有限公司 | Video stream transmission device, system, equipment and video stream transmission method |
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| CN201773441U (en) * | 2010-08-12 | 2011-03-23 | 上海古鳌电子机械有限公司 | Synchronous dynamic random access memory (SDRAM) double-port image data read and write controller based on field programmable gate array (FPGA) |
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| CN102270444A (en) | 2011-12-07 |
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