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CN109766285A - A burst mode SDRAM access control system and control method - Google Patents

A burst mode SDRAM access control system and control method Download PDF

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Publication number
CN109766285A
CN109766285A CN201910021683.1A CN201910021683A CN109766285A CN 109766285 A CN109766285 A CN 109766285A CN 201910021683 A CN201910021683 A CN 201910021683A CN 109766285 A CN109766285 A CN 109766285A
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sdram
module
control module
data
main control
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刘阳
孙亮
韩振伟
宋克非
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Abstract

The present invention relates to the SDRAM access control systems and method of a kind of burst mode, it solves extremely complex cumbersome for the write operation of storage chip SDRAM, read operation and refresh operation at present, the problem of being easy to happen data transmission storage mistake, and then influencing entire ccd image quality.Control system of the invention includes SDRAM write-in control module, SDRAM main control module, SDRAM chip, SDRAM reading control module and SDRAM refreshing control module.The present invention uses modularized processing to every kind of operation, makes calling program modification easy to maintain, realizes large capacity ccd image pin-saving chip SDRAM high reliability and efficient control mode, significantly improve the performance of system.

Description

A kind of the SDRAM access control system and control method of burst mode
Technical field
The present invention relates to large capacity ccd image field of data access technologies, more particularly to a kind of SDRAM of burst mode Access control system and control method.
Background technique
Currently, in large capacity ccd image field of data access technology, for storage chip synchronous DRAM The write operation of (Synchronous Dynamic RandomAccess Memory, SDRAM), read operation and refresh operation are non- It is often complicated cumbersome, it is easy to happen data transmission storage mistake, and then influence entire ccd image quality.
Summary of the invention
Based on this, it is necessary to existing large capacity ccd image Data Access Technology there are aiming at the problem that, provide a kind of prominent The SDRAM access control system and control method of hair mode.
To solve the above problems, the invention adopts the following technical scheme:
A kind of SDRAM access control system of burst mode, the system include SDRAM write-in control module, SDRAM master control Module, SDRAM chip, SDRAM read control module and SDRAM refreshing control module；
SDRAM write-in control module receives the data that data source transmits, and received data are transferred to SDRAM master control mould Block, SDRAM main control module store data in SDRAM chip；
When data destination needs to obtain data, SDRAM reads control module and is read by SDRAM main control module Data in SDRAM chip, and the data of reading are transferred to data destination；
SDRAM refreshing control module refreshes SDRAM chip by SDRAM main control module.
Correspondingly, the present invention also proposes a kind of SDRAM access control method of burst mode, and this method includes following step It is rapid:
Step 1: SDRAM main control module uninterruptedly monitors whether SDRAM refreshing control module sends refresh requests, if so, Then SDRAM refreshing control module refreshes SDRAM chip by SDRAM main control module, otherwise executes step 2；
Step 2: SDRAM main control module uninterruptedly monitor write-in buffer control submodule whether send write data requests and Read whether buffer control submodule sends reading request of data, if monitoring write-in buffer control submodule and reading caching control Any one in system module sends request, thens follow the steps three, otherwise return step one；
Step 3: if SDRAM main control module only monitors write-in, buffer control submodule sends write data requests, executes Step 4；If SDRAM main control module monitors that reading buffer control submodule sends reading request of data, thens follow the steps five；
Step 4: the data that write-in buffer control submodule transmits data source are spliced and are cached in the first caching Module, then filling data are cached in the first cache sub-module, the first cache sub-module by the data of caching and filler accordingly In whole page burst mode write-in SDRAM chip；
Step 5: it reads buffer control submodule and reads data from SDRAM chip with whole page burst mode, then will have Data buffer storage is imitated in the second cache sub-module, the second cache sub-module is exported valid data are cached to data destination.
Compared with prior art, the invention has the following advantages:
The present invention uses modularized processing to every kind of operation, makes calling program modification easy to maintain, realizes large capacity CCD figure As pin-saving chip SDRAM high reliability and efficient control mode, the performance of system is significantly improved.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the SDRAM access control system of burst mode of the present invention；
Fig. 2 is the communication protocol schematic diagram of CCD_4720 detector；
Fig. 3 is a kind of flow diagram of the SDRAM access control method of burst mode of the present invention.
Specific embodiment
Technical solution of the present invention is described in detail below in conjunction with attached drawing and preferred embodiment.
In one of the embodiments, as shown in Figure 1, the present invention discloses a kind of SDRAM access control system of burst mode System, the system include SDRAM write-in control module 1, SDRAM main control module 2, SDRAM chip 3, SDRAM reading control module 4 With SDRAM refreshing control module 5.
Specifically, SDRAM is written control module 1 and receives the data that data source 6 transmits, and data source 6, which is examined, can select E2V public The CCD_4720 detector of department, the ccd detector use the four-wire system way of output, i.e. frame synchronizing signal, line synchronising signal, clock Signal and ccd image data, as shown in Fig. 2, clock signal uses 40 megahertzs of frequency, pixel is 1034 row × 1072 Column, video capture processor select AD9814, and AD9814 data bit width is 14bit, in order to easy to operate before AD9814 data Supplement two zero makes it export bit wide 16bit；SDRAM is written control module 1 and received data is transferred to SDRAM master control Module 2, SDRAM main control module 2 store data in SDRAM chip 3, and SDRAM chip 3 can select 3D_PLUS company 3DSD1G32VS2141；
When data destination 7 needs to obtain data, SDRAM reads control module 4 and is read by SDRAM main control module 2 Data in SDRAM chip 3, and SDRAM reads control module 4 and the data of reading is transferred to data destination 7, data mesh Ground 7 can be for image display system etc..
SDRAM refreshing control module 5 carries out refresh operation to SDRAM chip 3 by SDRAM main control module 2.
A kind of SDRAM access control system for burst mode that the present embodiment is proposed is to every kind of operation using at modularization Reason, makes calling program modification easy to maintain, realizes large capacity ccd image pin-saving chip SDRAM high reliability and high efficiency Control mode, significantly improve the performance of system.
Further, control module is written in the SDRAM in a kind of SDRAM access control system of burst mode of the present embodiment 1 includes write-in buffer control submodule 1-1 and the first cache sub-module 1-2, wherein the first cache sub-module 1-2 can be selected The FIFO memory of 32bit × 1024.After the completion of the shooting of data source 6, data source 6 transfers data to write-in buffer control Module 1-1, write-in buffer control submodule 1-1 receive the data that data source 6 transmits and write number to the sending of SDRAM main control module 2 According to request, after writing data permission signal of the feedback of SDRAM main control module 2, write-in are received when buffer control submodule 1-1 is written Buffer control submodule 1-1 passes through received data buffer storage to the first cache sub-module 1-2, the first cache sub-module 1-2 SDRAM main control module 2 stores data in SDRAM chip 3.Behaviour is write to large capacity ccd image pin-saving chip SDRAM Make, the present embodiment prevents program from timing error occur by the way of challenge-response.
Further, the SDRAM in a kind of SDRAM access control system of burst mode of the present embodiment reads control module 4 include reading buffer control submodule 4-1 and the second cache sub-module 4-2, wherein the second cache sub-module 4-2 can be selected The FIFO memory of 16bit × 2048.Buffer control submodule 4-1 is read to ask to the sending reading data of SDRAM main control module 2 It asks, after the reading data that reading buffer control submodule 4-1 receives the feedback of SDRAM main control module 2 allow signal, reads slow Control submodule 4-1 is deposited by the data in the reading SDRAM chip 3 of SDRAM main control module 2, and reads buffer control submodule Data are exported the data buffer storage of reading to data mesh to the second cache sub-module 4-2, the second cache sub-module 4-2 by block 4-1 Ground 7.Read operation to large capacity ccd image pin-saving chip SDRAM, the present embodiment are prevented by the way of challenge-response Only there is timing error in program.
Further, SDRAM refreshing control module 5 issues the request for refreshing SDRAM chip 3 to SDRAM main control module 2, After the refreshing that SDRAM refreshing control module 5 receives the feedback of SDRAM main control module 2 allows signal, SDRAM refresh control mould Block 5 refreshes SDRAM chip 3 by SDRAM main control module 2.To large capacity ccd image pin-saving chip SDRAM's Refresh operation, the present embodiment prevent program from timing error occur by the way of challenge-response.
Further, SDRAM is written control module 1, SDRAM main control module 2, SDRAM and reads control module 4 and SDRAM Refreshing control module 5 realizes that slave computer can select the XQR2V3000 of Xilinx company in slave computer.
In another embodiment, as shown in figure 3, the present invention discloses a kind of SDRAM access based on above-mentioned burst mode The control method of control system, method includes the following steps:
Step 1: uninterruptedly whether monitoring SDRAM refreshing control module 5 sends refresh requests to SDRAM main control module 2, if It is that then SDRAM refreshing control module 5 refreshes SDRAM chip 3 by SDRAM main control module 2, otherwise executes step 2；
Step 2: uninterruptedly whether monitoring write-in buffer control submodule 1-1 sends and writes data and ask SDRAM main control module 2 Summation read buffer control submodule 4-1 whether send reading request of data, if monitor write-in buffer control submodule 1-1 and Any one read in buffer control submodule 4-1 sends request, thens follow the steps three, otherwise return step one；
Step 3: if SDRAM main control module 2 only monitors write-in, buffer control submodule 1-1 sends write data requests, Execute step 4；If SDRAM main control module 2 monitors that reading buffer control submodule 4-1 sends reading request of data, executes Step 5；
Step 4: the data that data source 6 transmits are spliced and are cached in first by write-in buffer control submodule 1-1 to be delayed Submodule 1-2 is deposited, then filling data are cached in the first cache sub-module 1-2, the first cache sub-module 1-2 for the data of caching SDRAM chip 3 is written in whole page burst mode accordingly with filler；
Step 5: being read buffer control submodule 4-1 and read data from SDRAM chip 3 with whole page burst mode, then Valid data are cached in the second cache sub-module 4-2, the second cache sub-module 4-2 to export valid data are cached to data mesh Ground 7.
Specifically, in the present embodiment in the step of one, SDRAM main control module 2 uninterruptedly monitors SDRAM refresh control mould Whether block 5 sends refresh requests, if monitoring that SDRAM refreshing control module 5 sends refresh requests, SDRAM refreshes control Molding block 5 refreshes SDRAM chip 3 by SDRAM main control module 2, otherwise executes step 2.
After the completion of data source 6 (such as CCD_4720 detector) shooting, image data is sent to write-in by data source 6 line by line Buffer control submodule 1-1, at this point, write-in buffer control submodule 1-1 can send write data requests to SDRAM main control module 2.
When data destination 7 needs image data, reading buffer control submodule 4-1 can send out to SDRAM main control module 2 Send reading request of data.
In step 2, whether SDRAM main control module 2 uninterruptedly monitors write-in buffer control submodule 1-1, which sends, is write number According to request and read whether buffer control submodule 4-1 sends reading request of data, if monitoring write-in buffer control submodule 1-1 and any one read in buffer control submodule 4-1 send request, then follow the steps three；If SDRAM main control module 2, which do not monitor that write-in buffer control submodule 1-1 sends write data requests and reads buffer control submodule 4-1, sends reading Request of data, then return step one.
In step 3, if SDRAM main control module 2 only monitor write-in buffer control submodule 1-1 send write number According to request, without monitoring that reading buffer control submodule 4-1 sends reading request of data, then executing step 4, that is, writes Enter buffer control submodule 1-1 and the data that data source 6 transmits are spliced to and are cached in the first cache sub-module 1-2, is written Filling data are cached in the first cache sub-module 1-2 again by buffer control submodule 1-1, and the first cache sub-module 1-2 will be cached Data and filler SDRAM chip 3 is written in whole page burst mode accordingly.Below only with data source 6 for CCD_4720 detector For be illustrated: the 16bit that write-in buffer control submodule 1-1 exports the video capture processor AD9814 of data source 6 believes It number is spliced into 32bit and is cached in the first cache sub-module 1-2, when 1072 pixels of CCD_4720 detector a line are all cached in After first cache sub-module 1-2,488 32bit zeros (i.e. filling data) are cached in the by write-in buffer control submodule 1-1 By the data of caching and filler, whole page burst mode is written one cache sub-module 1-2, the first cache sub-module 1-2 accordingly again In 1024 32bit storage units of a line of SDRAM chip 3, step 1 is repeated to step 4, CCD_4720 can be detected 1034 row * 1072 of the entire image column of device shooting are stored in SDRAM chip 3.
If SDRAM main control module 2 only monitor to read the reading request of data sent of buffer control submodule 4-1 or SDRAM main control module 2 monitors the write data requests that write-in buffer control submodule 1-1 is sent simultaneously and reads buffer control The reading request of data that module 4-1 is sent, then executing step 5, i.e., reading buffer control submodule 4-1 is by data with whole page Burst mode is read from SDRAM chip 3, then valid data are cached in the second cache sub-module 4-2, the second cache sub-module 4-2 is exported valid data are cached to data destination 7.It is also only carried out so that data source 6 is CCD_4720 detector as an example below Illustrate: reading buffer control submodule 4-1 and read out data from SDRAM chip 3 with whole page burst mode, then reads slow It deposits control submodule 4-1 and the CCD_4720 detector valid data of 536 32bit is become into 1072 16bit data buffer storages again In the second cache sub-module 4-2, the second last cache sub-module 4-2 is by CCD_4720 detector a line figure of 1072 16bit As data are exported to data destination 7, repeat Step 1: Step 2: step 3 and step 5, can detect CCD_4720 1034 row of entire image of device shooting × 1072 column read out from SDRAM chip 3, and are transferred to data destination 7.
Further, as shown in figure 3, in step 1, when SDRAM main control module 2 monitors SDRAM refreshing control module When 5 refresh requests sent are system free time refresh requests, SDRAM refreshing control module 5 is right by SDRAM main control module 2 SDRAM chip 3 carries out single refreshing, and after refreshing, SDRAM main control module 2 continues uninterruptedly to monitor SDRAM refreshing control module 5 Whether refresh requests are sent.
Further, as shown in figure 3, in step 1, when SDRAM main control module 2 monitors SDRAM refreshing control module When 5 refresh requests sent are nonsystematic free time refresh requests, SDRAM refreshing control module 5 is right by SDRAM main control module 2 SDRAM chip 3 carries out 1024 refreshings, and after refreshing, SDRAM main control module 2 continues uninterruptedly to monitor SDRAM refreshing control module Whether 5 send refresh requests.
Various operations of the present invention to large capacity ccd image pin-saving chip SDRAM, for example, write operation, read operation with And refresh etc., by the way of challenge-response, prevent program from timing error occur, meanwhile, the modularization that every kind of operation is used Processing, make calling program modification easy to maintain, realize large capacity ccd image pin-saving chip SDRAM high reliability and efficiently The control mode of rate significantly improves the performance of system.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.

Claims (8)

1.一种突发模式的SDRAM存取控制系统，其特征在于，包括SDRAM写入控制模块(1)、SDRAM主控模块(2)、SDRAM芯片(3)、SDRAM读出控制模块(4)和SDRAM刷新控制模块(5)；1. the SDRAM access control system of a burst mode, is characterized in that, comprises SDRAM write control module (1), SDRAM main control module (2), SDRAM chip (3), SDRAM read control module (4) and SDRAM refresh control module (5); SDRAM写入控制模块(1)接收数据源(6)传来的数据，并将接收的数据传输给SDRAM主控模块(2)，SDRAM主控模块(2)将数据存储于SDRAM芯片(3)；The SDRAM write control module (1) receives the data from the data source (6), and transmits the received data to the SDRAM main control module (2), which stores the data in the SDRAM chip (3) ; 当数据目的地(7)需要获取数据时，SDRAM读出控制模块(4)通过SDRAM主控模块(2)读取SDRAM芯片(3)中的数据，并将读取的数据传输给数据目的地(7)；When the data destination (7) needs to acquire data, the SDRAM read control module (4) reads the data in the SDRAM chip (3) through the SDRAM main control module (2), and transmits the read data to the data destination (7); SDRAM刷新控制模块(5)通过SDRAM主控模块(2)对SDRAM芯片(3)进行刷新。The SDRAM refresh control module (5) refreshes the SDRAM chip (3) through the SDRAM main control module (2). 2.根据权利要求1所述的一种突发模式的SDRAM存取控制系统，其特征在于，SDRAM写入控制模块(1)包括写入缓存控制子模块(1-1)和第一缓存子模块(1-2)；2. The SDRAM access control system of a burst mode according to claim 1, wherein the SDRAM write control module (1) comprises a write cache control submodule (1-1) and a first cache submodule module(1-2); 写入缓存控制子模块(1-1)接收数据源(6)传来的数据，并向SDRAM主控模块(2)发出写数据请求；The write cache control sub-module (1-1) receives data from the data source (6), and sends a write data request to the SDRAM main control module (2); 当写入缓存控制子模块(1-1)接收到SDRAM主控模块(2)反馈的写数据允许信号后，写入缓存控制子模块(1-1)将接收的数据缓存到第一缓存子模块(1-2)，第一缓存子模块(1-2)通过SDRAM主控模块(2)将数据存储于SDRAM芯片(3)。After the write cache control sub-module (1-1) receives the write data permission signal fed back by the SDRAM main control module (2), the write cache control sub-module (1-1) caches the received data into the first cache sub-module (1-1). The module (1-2), the first cache sub-module (1-2) stores data in the SDRAM chip (3) through the SDRAM main control module (2). 3.根据权利要求1或2所述的一种突发模式的SDRAM存取控制系统，其特征在于，SDRAM读出控制模块(4)包括读出缓存控制子模块(4-1)和第二缓存子模块(4-2)；3. The SDRAM access control system of a burst mode according to claim 1 or 2, wherein the SDRAM readout control module (4) comprises a readout cache control submodule (4-1) and a second Cache submodule (4-2); 读出缓存控制子模块(4-1)向SDRAM主控模块(2)发出读取数据请求；The read-out cache control sub-module (4-1) sends a read data request to the SDRAM main control module (2); 当读出缓存控制子模块(4-1)接收到SDRAM主控模块(2)反馈的读取数据允许信号后，读出缓存控制子模块(4-1)通过SDRAM主控模块(2)读取SDRAM芯片(3)中的数据，并将读取的数据缓存到第二缓存子模块(4-2)，第二缓存子模块(4-2)将数据输出至数据目的地(7)。After the read-out cache control sub-module (4-1) receives the read data permission signal fed back by the SDRAM main control module (2), the read-out cache control sub-module (4-1) reads the data through the SDRAM main control module (2). The data in the SDRAM chip (3) is taken, and the read data is cached in the second cache sub-module (4-2), and the second cache sub-module (4-2) outputs the data to the data destination (7). 4.根据权利要求1或2所述的一种突发模式的SDRAM存取控制系统，其特征在于，4. the SDRAM access control system of a kind of burst mode according to claim 1 and 2 is characterized in that, SDRAM刷新控制模块(5)向SDRAM主控模块(2)发出刷新SDRAM芯片(3)的请求；The SDRAM refresh control module (5) sends a request to refresh the SDRAM chip (3) to the SDRAM main control module (2); 当SDRAM刷新控制模块(5)接收到SDRAM主控模块(2)反馈的刷新允许信号后，SDRAM刷新控制模块(5)通过SDRAM主控模块(2)对SDRAM芯片(3)进行刷新。After the SDRAM refresh control module (5) receives the refresh permission signal fed back by the SDRAM main control module (2), the SDRAM refresh control module (5) refreshes the SDRAM chip (3) through the SDRAM main control module (2). 5.根据权利要求1或2所述的一种突发模式的SDRAM存取控制系统，其特征在于，5. the SDRAM access control system of a kind of burst mode according to claim 1 and 2 is characterized in that, SDRAM写入控制模块(1)、SDRAM主控模块(2)、SDRAM读出控制模块(4)和SDRAM刷新控制模块(5)均在下位机实现。The SDRAM write control module (1), the SDRAM main control module (2), the SDRAM readout control module (4) and the SDRAM refresh control module (5) are all implemented in the lower computer. 6.一种基于如权利要求2至5任意一项所述的一种突发模式的SDRAM存取控制系统的控制方法，其特征在于，包括以下步骤：6. a kind of control method based on the SDRAM access control system of a kind of burst mode as described in any one of claim 2 to 5, is characterized in that, comprises the following steps: 步骤一：SDRAM主控模块(2)不间断监测SDRAM刷新控制模块(5)是否发来刷新请求，若是，则SDRAM刷新控制模块(5)通过SDRAM主控模块(2)对SDRAM芯片(3)进行刷新，否则执行步骤二；Step 1: The SDRAM main control module (2) continuously monitors whether the SDRAM refresh control module (5) sends a refresh request. If so, the SDRAM refresh control module (5) communicates with the SDRAM chip (3) through the SDRAM main control module (2). Refresh, otherwise go to step 2; 步骤二：SDRAM主控模块(2)不间断监测写入缓存控制子模块(1-1)是否发来写数据请求和读出缓存控制子模块(4-1)是否发来读取数据请求，若监测到写入缓存控制子模块(1-1)和读出缓存控制子模块(4-1)中的任意一个发来请求，则执行步骤三，否则返回步骤一；Step 2: The SDRAM main control module (2) continuously monitors whether the write cache control sub-module (1-1) sends a write data request and the read cache control sub-module (4-1) sends a read data request, If it is detected that any one of the write cache control sub-module (1-1) and the read cache control sub-module (4-1) sends a request, step 3 is performed, otherwise, return to step 1; 步骤三：若SDRAM主控模块(2)仅监测到写入缓存控制子模块(1-1)发来写数据请求，则执行步骤四；若SDRAM主控模块(2)监测到读出缓存控制子模块(4-1)发来读取数据请求，则执行步骤五；Step 3: If the SDRAM main control module (2) only monitors the write data request sent by the write cache control sub-module (1-1), step 4 is performed; if the SDRAM main control module (2) monitors the read cache control If the sub-module (4-1) sends a data read request, step 5 is executed; 步骤四：写入缓存控制子模块(1-1)将数据源(6)传来的数据进行拼接并缓存于第一缓存子模块(1-2)，再将填充数据缓存于第一缓存子模块(1-2)，第一缓存子模块(1-2)将缓存的数据和填充数据以整页突发模式写入SDRAM芯片(3)中；Step 4: The write cache control sub-module (1-1) splices the data transmitted from the data source (6) and caches it in the first cache sub-module (1-2), and then caches the filled data in the first cache sub-module (1-2). The module (1-2), the first cache sub-module (1-2) writes the buffered data and the filling data into the SDRAM chip (3) in a full-page burst mode; 步骤五：读出缓存控制子模块(4-1)将数据以整页突发模式从SDRAM芯片(3)中读出，再将有效数据缓存于第二缓存子模块(4-2)，第二缓存子模块(4-2)将缓存有效数据输出至数据目的地(7)。Step 5: The read-out cache control sub-module (4-1) reads out the data from the SDRAM chip (3) in a full-page burst mode, and then caches the valid data in the second cache sub-module (4-2). The second cache sub-module (4-2) outputs the cached valid data to the data destination (7). 7.根据权利要求6所述的一种突发模式的SDRAM存取控制方法，其特征在于，7. the SDRAM access control method of a kind of burst mode according to claim 6, is characterized in that, 当SDRAM主控模块(2)监测到SDRAM刷新控制模块(5)发来的刷新请求为系统空闲刷新请求时，SDRAM刷新控制模块(5)通过SDRAM主控模块(2)对SDRAM芯片(3)进行单次刷新。When the SDRAM main control module (2) detects that the refresh request sent by the SDRAM refresh control module (5) is a system idle refresh request, the SDRAM refresh control module (5) updates the SDRAM chip (3) through the SDRAM main control module (2). Do a single refresh. 8.根据权利要求6或7所述的一种突发模式的SDRAM存取控制方法，其特征在于，8. the SDRAM access control method of a kind of burst mode according to claim 6 or 7, is characterized in that, 当SDRAM主控模块(2)监测到SDRAM刷新控制模块(5)发来的刷新请求为非系统空闲刷新请求时，SDRAM刷新控制模块(5)通过SDRAM主控模块(2)对SDRAM芯片(3)进行1024次刷新。When the SDRAM main control module (2) detects that the refresh request sent by the SDRAM refresh control module (5) is a non-system idle refresh request, the SDRAM refresh control module (5) updates the SDRAM chip (3) through the SDRAM main control module (2). ) for 1024 refreshes.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101308697A (en) * 2008-07-10 2008-11-19 哈尔滨工业大学 Large-capacity FIFO burst buffer and data storage method based on SDRAM
CN102025889A (en) * 2010-11-29 2011-04-20 大连捷成实业发展有限公司 A high-definition digital video frame synchronization system based on FPGA and SDRAM
CN102270444A (en) * 2011-09-07 2011-12-07 东莞中山大学研究院 Video processing chip data flow control and frame buffer device
US20140032697A1 (en) * 2012-03-23 2014-01-30 DSSD, Inc. Storage system with multicast dma and unified address space
CN104599227A (en) * 2013-10-30 2015-05-06 南京理工大学 DDR3 arbitration controller and method applied to high-speed CCD data storage
CN106547483A (en) * 2016-10-18 2017-03-29 广东高云半导体科技股份有限公司 A kind of SDR sdram controllers of Universal efficient and its method of work

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101308697A (en) * 2008-07-10 2008-11-19 哈尔滨工业大学 Large-capacity FIFO burst buffer and data storage method based on SDRAM
CN102025889A (en) * 2010-11-29 2011-04-20 大连捷成实业发展有限公司 A high-definition digital video frame synchronization system based on FPGA and SDRAM
CN102270444A (en) * 2011-09-07 2011-12-07 东莞中山大学研究院 Video processing chip data flow control and frame buffer device
US20140032697A1 (en) * 2012-03-23 2014-01-30 DSSD, Inc. Storage system with multicast dma and unified address space
CN104599227A (en) * 2013-10-30 2015-05-06 南京理工大学 DDR3 arbitration controller and method applied to high-speed CCD data storage
CN106547483A (en) * 2016-10-18 2017-03-29 广东高云半导体科技股份有限公司 A kind of SDR sdram controllers of Universal efficient and its method of work

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