CN102214609A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same, the method includes forming a first sidewall buffer layer on a first gate stack of an NMOS region after forming the gate stack; then forming a second side wall on the second gate stack in the PMOS region; the first side wall buffer layer is made of nitride or oxide materials, and the second side wall is made of low-k dielectric materials; and then carrying out high-temperature annealing in an oxygen environment, so that oxygen atoms in the oxygen environment are diffused into the high-k gate dielectric layer of the second gate stack through the second side wall, and the first side wall buffer layer blocks the oxygen atoms from being diffused into the first gate stack. Embodiments of the present invention may be used in CMOS device processes or related art semiconductor processes.

Description

A kind of semiconductor device and its manufacturing method

technical field

The present invention generally relates to a semiconductor device and a manufacturing method thereof, in particular to a device capable of reducing the PMOS threshold voltage of a high-k gate dielectric/metal gate device and a manufacturing method thereof.

Background technique

With the development of semiconductor technology, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space of each component, between components or each component itself also need to be further reduced. The application of the core technology of 32/22 nanometer process integrated circuits has become an inevitable trend in the development of integrated circuits, and it is also one of the topics that major international semiconductor companies and research organizations are competing to research and develop. CMOS device gate engineering research centered on "high-k gate dielectric/metal gate" technology is the most representative core process in 32/22 nanometer technology, and related materials, processes and structures have been extensively studied .

For devices that integrate high-k gate dielectric materials and metal gates, transistors with high-mobility channels are realized, but due to high-temperature processing in the integration, the properties of the interface between metal and high-k insulating materials change, Oxygen vacancies in high-k gate dielectric materials are caused, which increases the threshold voltage of PMOS and reduces the reliability of the device. How to effectively control the PMOS threshold voltage is the primary problem of "high-k gate dielectric/metal gate" devices. At present, one method to reduce the PMOS threshold voltage of "high-k gate dielectric/metal gate" devices is the method of oxygen diffusion (Symposium on VLSItechnology Digest of Technical Papers, 2009, P _42-43 ), which is to remove the sidewall, Oxygen is diffused from the sidewall of the high-k/metal gate into the high-k gate dielectric material, but this method needs to remove the sidewall, which is difficult to control in the process, and will affect the gate dielectric layer, gate electrode and source/ The substrate of the drain region will cause damage, which will affect the performance of the device.

Therefore, it is necessary to propose a method for manufacturing a semiconductor device and a device structure thereof that can reduce the threshold voltage of a PMOS device without causing damage to the device.

Contents of the invention

In view of the above problems, the present invention provides a method of manufacturing the semiconductor device, the method comprising: providing a semiconductor substrate having an NMOS region and a PMOS region isolated from each other; forming a first gate stack on the NMOS region, And forming a second gate stack on the PMOS region, wherein the first gate stack and the second gate stack include a high-k gate dielectric layer and a metal gate electrode; forming a first spacer on the sidewall of the first gate stack buffer layer, and form a first spacer on the sidewall of the first sidewall buffer layer, and form a second spacer on the sidewall of the second gate stack, wherein the second sidewall uses a low-k dielectric Material formation; after corresponding source/drain regions are respectively formed on the NMOS region and the PMOS region, the device is annealed in an oxygen environment, so that oxygen atoms in the oxygen environment diffuse to the In the high-k gate dielectric layer of the second gate stack.

On the basis of the above solution, preferably, the first spacer buffer layer is formed of nitride or oxide, and the low-k dielectric material forming the second spacer may include: SiCOH, SiO or SiCO.

The present invention also provides a device fabricated by the above method, the device comprising: a semiconductor substrate having an NMOS region and a PMOS region isolated from each other; a source/drain region formed in the NMOS region and the PMOS region; a source/drain region formed in the A first gate stack between the source/drain regions of the NMOS region, and a second gate stack formed between the source/drain regions of the PMOS region, wherein the first gate stack and the second gate stack comprise high-k a gate dielectric layer and a metal gate electrode; and a first sidewall buffer layer formed on the sidewall of the first gate stack, a first sidewall formed on the sidewall of the first sidewall buffer layer, formed on the The second sidewall of the sidewall of the second gate stack, wherein the second spacer is formed of a low-k dielectric material, and the second spacer serves as oxygen atoms diffused into the high-k gate dielectric layer of the second gate stack channel.

On the basis of the above solution, preferably, the first spacer buffer layer is formed of nitride or oxide, and the low-k dielectric material forming the second spacer may include: SiCOH, SiO or SiCO.

By adopting the device structure and manufacturing method described in the present invention, not only oxygen atoms can be diffused into the high-k gate dielectric layer where the PMOS is located, thereby reducing the threshold voltage of the PMOS device without affecting the threshold voltage of the NMOS device, but also Avoid damage to the gate and substrate when the traditional process removes the PMOS sidewall, thereby effectively improving the overall performance of the device.

Description of drawings

1 shows a flowchart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

2-7 show schematic structural diagrams of various manufacturing stages of a semiconductor device according to the first embodiment of the present invention;

Detailed ways

The present invention generally relates to semiconductor devices and methods of manufacturing the same. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. For example, such that the first and second features may not be in direct contact.

According to a first embodiment of the present invention, refer to FIG. 1 , which shows a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In step 101 , a semiconductor substrate 200 having an NMOS region 201 and a PMOS region 202 is provided, wherein the NMOS region 201 and the PMOS region 202 are isolated from each other, refer to FIG. 2 . In this embodiment, the substrate 200 includes a silicon substrate (such as a wafer) in a crystal structure, and may also include other basic semiconductors or compound semiconductors, such as Ge, GeSi, GaAs, InP, SiC, or diamond. The substrate 200 may include various doping configurations according to design requirements known in the art (eg, p-type substrate or n-type substrate). Furthermore, the substrate 200 may optionally include epitaxial layers, may be altered by stress to enhance performance, and may include a silicon-on-insulator (SOI) structure.

In step 102 , a first gate stack 300 is formed on the NMOS region 201 , and a second gate stack 400 is formed on the PMOS region, as shown in FIG. 2 . The first gate stack 300 and the second gate stack 400 may be any multi-layer gate stack structure including a high-k gate dielectric layer and a metal gate electrode. In this embodiment, HfO ₂ is sequentially deposited on the semiconductor substrate 200 as a high-k gate dielectric layer, TiN as a metal gate electrode, and a polysilicon layer, and then patterned by dry or wet etching techniques to form The first gate stack 300 of the NMOS region 201 including the high-k gate dielectric layer 204, the metal gate electrode 208 and the polysilicon layer 212, and the first gate stack 300 of the PMOS region 202 including the high-k gate dielectric layer 206, the metal gate electrode 210 and the polysilicon layer 214 The second gate stack 400, as shown in FIG. 2, is merely an example and is not limited thereto. The first gate stack 300 and the second gate stack 400 may also be other gate stacks including a high-k gate dielectric layer and a metal gate electrode. Multilayer gate stack structure. The high-k gate dielectric layers 204, 206 are high-k dielectric materials (for example, materials with a high dielectric constant compared with silicon oxide), examples of high-k dielectric materials include, for example, hafnium-based materials, such as HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, combinations thereof or other suitable materials. The material of the metal gate electrode may be, but not limited to, TiN, TaN, Ta ₂ C, HfN, HfC, TiC, Mo, Ru and combinations thereof. The gate stack may be deposited using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other suitable processes.

In step 103 , a first sidewall buffer layer 216 is formed on the sidewall of the first gate stack 300 , as shown in FIG. 6 .

Specifically, first deposit a nitride or oxide material 215 on the device, such as Si ₃ N ₄ , SiO _{2 ,} etc., as shown in FIG. 3 , and then use the method of RIE to pattern the nitride or oxide material 215 , forming a first sidewall buffer layer 216 belonging to the NMOS region 201 and a second sidewall buffer layer 218 belonging to the PMOS region 202 , as shown in FIG. 4 . In particular, after forming the first 216 and the second sidewall buffer layer 218, according to the desired transistor structure, the substrate 200 of the NMOS region 201 and the PMOS region 202 may also be implanted with p-type or n-type dopants or impurities. , and form source/drain extension regions and/or halo regions 220, 224, as shown in FIG. 5 . Then mask the NMOS region 201, remove the second sidewall buffer layer 218 of the PMOS region 202 by dry or wet etching, and then remove the mask on the NMOS region 201, thereby forming the first gate stack 300. The side wall buffer layer 216 is shown in FIG. 6 . Wherein the thickness of the first sidewall buffer layer 216 is about 2 to 10 nanometers. The first sidewall buffer layer 216 formed of nitride or oxide material has a relatively dense structure, so it can prevent oxygen atoms from diffusing into the first gate stack 300 of the NMOS region 201 in subsequent steps.

In step 104 , a first spacer 228 is formed on the sidewall of the first spacer buffer layer 216 , and a second spacer 230 is formed on the sidewall of the second gate stack 400 . A low-k dielectric material, such as SiCOH, is deposited on the device, and then the low-k dielectric material is patterned by RIE to form the first sidewall 228 and the second sidewall 230 , as shown in FIG. 7 . The relative permittivity of the low-k dielectric material is less than 3.5, and the low-k dielectric material may be SiCOH, SiO or SiCO, etc. The thickness of the first sidewall 228 and the second sidewall 230 may be 2 to 100 nanometers, preferably 5 to 100 nanometers. Deposition of the low-k material may be formed using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other suitable processes. The second spacer 230 formed of a low-k dielectric material has a loose structure, so it can become a channel for oxygen atoms to diffuse into the high-k gate dielectric layer 206 of the second gate stack 400 later.

In step 105 , corresponding source/drain regions 222 and 226 are respectively formed on the NMOS region 201 and the PMOS region 202 . The source/drain regions 222 and 226 can be formed by implanting p-type or n-type dopants or impurities into the substrate 200 of the NMOS region 201 and the PMOS region 202 according to the desired transistor structure, as shown in FIG. 7 . The source/drain regions 222, 226 may be formed by methods including photolithography, ion implantation, diffusion and/or other suitable processes, and then the source/drain regions 222, 226 are annealed to activate doping.

After the usual source/drain regions 222, 226 are formed, in step 106, the device is annealed in an oxygen environment, so that oxygen atoms in the oxygen environment diffuse to the second gate through the second spacer 230 In the high-k gate dielectric layer 206 of the stack 400 . The annealing temperature can be 300°C to 800°C, the annealing time can be 1 to 3000 seconds, and the annealing protective gas is O ₂ , since the second sidewall 230 is formed of a low-k dielectric material with a loose structure, oxygen atoms can be The channels of the two sidewalls 230 are diffused into the high-k gate dielectric layer 206 of the second gate stack 400 in the direction indicated by the arrow in FIG. Furthermore, the effect of lowering the threshold voltage of PMOS is achieved, and for the first gate stack 300 in the NMOS region, due to the protection of the first sidewall buffer layer 216 formed of relatively dense nitride, oxygen atoms will not diffuse into the first gate stack 300 .

Referring to the description of the above method, the present invention also provides a semiconductor device, as shown in FIG. The PMOS regions 202 are isolated from each other; the source/drain regions 222, 224 formed in the NMOS region 201 and the PMOS region 202; the first gate stack 300 formed between the source/drain regions 222 of the NMOS region 201, and The second gate stack 400 formed between the source/drain regions 226 of the PMOS region 202, wherein the first gate stack 300 and the second gate stack 400 may include high-k gate dielectric layers 204, 206 and metal gate Any multilayer gate stack structure of the electrodes 208, 210; and the first sidewall buffer layer 216 formed on the sidewall of the first gate stack 300, and the first sidewall buffer layer 216 formed on the sidewall of the first sidewall buffer layer 216 The first spacer 228, the second sidewall 230 formed on the sidewall of the second gate stack 400, wherein the second spacer 230 is formed of a low-k dielectric material, and the second sidewall 230 acts as an oxygen atom Diffused to the channel in the high-k gate dielectric layer 206 of the second gate stack 400 . Wherein the first sidewall buffer layer 216 is formed of nitride or oxide, and the thickness of the first sidewall buffer layer 216 is about 2 to 10 nanometers. The first sidewall 228 is preferably formed of a low-k dielectric material at the same time as the second sidewall 230, and the relative permittivity of the low-k dielectric material forming the first 228 and the second sidewall 230 is less than 3.5, forming the The low-k dielectric material of the first 228 and the second spacer 230 includes: SiCOH, SiO or SiCO, the thickness of the first 228 and the second sidewall 230 is about 2 to 100 nanometers, preferably 5 to 100 nanometers .

The present invention describes the method and device for forming the first spacer buffer layer 216 on the NMOS region 201 and performing annealing to replenish oxygen vacancies after the formation of the sidewall of the low-k dielectric material in the PMOS region. According to the method of the present invention, the first sidewall buffer layer 216 is only formed on the sidewall of the first gate stack 300 in the NMOS region 201, and the first sidewall buffer layer 216 is a relatively dense nitride or oxide material, such as _Si3 N ₄ etc., the sidewall of the second gate stack 400 in the PMOS region 202 is directly covered by the second spacer 230 , and the second sidewall 230 is a loose low-k material, such as SiCOH, SiO, SiCO. For a device with such a structure, after high-temperature annealing in an oxygen environment, oxygen atoms diffuse into the high-k gate dielectric layer 206 of the second gate stack 400 along the second spacer 230, thereby reducing the threshold voltage of the PMOS device and being affected by With the protection of the Si ₃ N ₄ first sidewall buffer layer 216, oxygen atoms will not diffuse to the NMOS device, and the threshold voltage of the NMOS device will not be affected, which effectively realizes the adjustment of the threshold voltage of the PMOS device and improves the overall performance of the device. In addition, the use of low-k materials to form sidewall structures also effectively reduces the parasitic capacitance of devices.

Although the example embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to these embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, those of ordinary skill in the art will readily understand that the order of process steps may be varied while remaining within the scope of the present invention.

In addition, the scope of application of the present invention is not limited to the process, mechanism, manufacture, material composition, means, method and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that for the processes, mechanisms, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, they are implemented in accordance with the present invention Corresponding embodiments described which function substantially the same or achieve substantially the same results may be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacture, material compositions, means, methods or steps within their protection scope.

Claims (14)

1. A method of manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate having mutually isolated NMOS regions and PMOS regions; forming a first gate stack on the NMOS region, and forming a second gate stack on the PMOS region, wherein the first gate stack and the second gate stack include a high-k gate dielectric layer and a metal gate electrode; A first spacer buffer layer is formed on the sidewall of the first gate stack, a first spacer is formed on the sidewall of the first sidewall buffer layer, and a second sidewall is formed on the sidewall of the second gate stack. a sidewall, wherein the second sidewall is formed of a low-k dielectric material; After corresponding source/drain regions are respectively formed on the NMOS region and the PMOS region, the device is annealed in an oxygen environment, so that oxygen atoms in the oxygen environment diffuse to the second side wall through the second sidewall. In the high-k gate dielectric layer of the gate stack. 2. The method of claim 1, wherein the first sidewall buffer layer is formed of nitride or oxide. 3. The method according to claim 1, wherein the first sidewall buffer layer has a thickness of 2 to 10 nanometers. 4. The method according to claim 1, wherein the first spacer is formed of a low-k dielectric material. 5. The method according to claim 1 or 4, wherein the relative permittivity of the low-k dielectric material forming the first and second spacers is less than 3.5. 6. The method according to claim 1 or 4, wherein the low-k dielectric material forming the first and second spacers comprises: SiCOH, SiO or SiCO. 7. The method of any one of claims 1 to 4, wherein the first and second sidewalls have a thickness of 2 to 100 nanometers. 8. A semiconductor device, said device comprising: a semiconductor substrate having mutually isolated NMOS regions and PMOS regions; source/drain regions formed in the NMOS region and the PMOS region; A first gate stack formed between the source/drain regions of the NMOS region, and a second gate stack formed between the source/drain regions of the PMOS region, wherein the first gate stack and the second gate stack the stack includes a high-k gate dielectric layer and a metal gate electrode; and The first sidewall buffer layer formed on the sidewall of the first gate stack, the first sidewall formed on the sidewall of the first sidewall buffer layer, the first sidewall formed on the sidewall of the second gate stack The second sidewall, wherein the second sidewall is formed of a low-k dielectric material, and the second sidewall serves as a channel for oxygen atoms to diffuse into the high-k gate dielectric layer of the second gate stack. 9. The device of claim 8, wherein the first sidewall buffer layer is formed of nitride or oxide. 10. The device according to claim 8, wherein the first sidewall buffer layer has a thickness of 2 to 10 nanometers. 11. The device according to claim 8, wherein the first spacer is formed of a low-k dielectric material. 12. The device according to claim 8 or 11, wherein the relative permittivity of the low-k dielectric material forming the first and second spacers is less than 3.5. 13. The device according to claim 8 or 11, wherein the low-k dielectric material forming the first and second spacers comprises: SiCOH, SiO or SiCO. 14. The device of any one of claims 8 to 11, wherein the first and second sidewalls have a thickness of about 2 to 100 nanometers.

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