CN102299155A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a structure of a semiconductor device, comprising: a semiconductor substrate; a gate structure formed on a semiconductor substrate, wherein the gate structure comprises: the gate structure comprises an interface layer on a semiconductor substrate, a first high-k gate dielectric layer on the interface layer, a second high-k gate dielectric layer on the first high-k gate dielectric layer, a third high-k gate dielectric layer on the second high-k gate dielectric layer, and a metal gate layer on the third high-k gate dielectric layer, wherein the dielectric constant of the second high-k gate dielectric layer is higher than that of the first and third high-k gate dielectric layers. According to the invention, the second high-k gate dielectric layer is inserted into the first high-k gate dielectric layer and the third high-k gate dielectric layer of the MOS device, and the second high-k gate dielectric layer is used as a higher-k dielectric, so that the thickness of an equivalent oxide layer can be effectively reduced. Meanwhile, because the interface dipoles existing at the interfaces among the first, second and third high-k gate dielectric layers are optimized, the structure can also effectively adjust the threshold voltage of the MOS device.

Description

A kind of semiconductor device and its manufacturing method

technical field

The present invention generally relates to a semiconductor device structure and a manufacturing method thereof, in particular to a semiconductor device structure and a manufacturing method thereof which reduce the thickness of the gate equivalent oxide layer.

Background technique

As the core of microelectronic technology, CMOS technology has become the supporting force in modern electronic products. With the continuous reduction of the feature size of CMOS devices, the physical thickness of SiO ₂ as the gate dielectric material of CMOS devices has gradually approached the limit. The use of high-k gate dielectric materials and metal gate electrode materials marks a breakthrough in transistor technology since the introduction of polysilicon gate MOS transistors, which is a milestone. The introduction of high-k gate dielectric material can ensure that the physical thickness of the gate dielectric can be effectively increased under the same equivalent oxide thickness (EOT), so that the tunneling current can be effectively suppressed; the introduction of metal gate electrode material not only eliminates the The depletion effect of the polysilicon gate electrode and the diffusion of dopant atoms can effectively reduce the resistance of the gate electrode and solve the incompatibility between the high-k gate dielectric material and the polysilicon gate.

At present, research on high-k gate dielectric materials has made some progress. Through interface control and film formation process optimization, ultra-thin (EOT: 0.5nm, physical thickness: 2.4nm), low leakage current (J _g : 10A/cm ² ) HfO ₂ high-k gate dielectric insulating film can be obtained. However, through device performance tests, it is found that with the extreme reduction of EOT (~0.5nm), the flat-band voltage (V _fb ) shifts very obviously to the vicinity of the middle value of the band gap of silicon. This is mainly caused by the compatibility and thermal stability of the high-k gate dielectric and the metal gate electrode, and will greatly increase the power consumption of the device. In addition, the abnormal shifting phenomenon of V _fb is caused by the special interface characteristics between the gate electrode and the high-k gate dielectric, for example, the Fermi level pinning effect caused by the formation of Si-Hf bonds at the interface of polysilicon gate and _HfO2 , the Fermi level pinning effect caused by the formation of dipoles at the interface between the metal gate and the high-k gate dielectric and the interface between the high-k gate dielectric and SiO ₂ , etc. Obviously, the research on the threshold voltage control technology of CMOS devices with metal gate and high-k gate dielectric structure is not only related to the work function of the metal gate material itself, but to study the metal gate and high-k gate dielectric structure as a whole. It is required that the threshold voltages of the NMOS and PMOS devices should be reduced as much as possible on the premise of keeping the absolute values approximately equal. It is the most direct, feasible and effective method to adjust the effective work function by using suitable materials and structures to reduce the threshold voltage of devices.

Contents of the invention

The object of the present invention is to provide a semiconductor device structure and its manufacturing method which can effectively adjust the threshold voltage and reduce the equivalent oxide thickness (EOT) by utilizing the method of dipole cancellation. The semiconductor device structure of the present invention comprises: a semiconductor substrate; a gate structure formed on the semiconductor substrate, wherein the gate structure comprises: an interface layer on the semiconductor substrate, an interface layer on the interface layer the first high-k gate dielectric layer on the first high-k gate dielectric layer, the second high-k gate dielectric layer on the first high-k gate dielectric layer, the third high-k gate dielectric layer on the second high-k gate dielectric layer, The metal gate layer on the third high-k gate dielectric layer, wherein the dielectric constant of the second high-k gate dielectric layer is higher than the dielectric constants of the first and third high-k gate dielectric layers.

The present invention also provides a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate; forming an interface layer on the semiconductor substrate; forming a first high-k gate dielectric layer on the interface layer; Forming a second high-k gate dielectric layer on the first high-k gate dielectric layer; forming a third high-k gate dielectric layer on the second high-k gate dielectric layer; forming a third high-k gate dielectric layer on the third high-k gate dielectric layer Metal gate layer; processing the device to form a gate structure; wherein the dielectric constant of the second high-k gate dielectric layer is higher than the dielectric constant of the first and third high-k gate dielectric layers .

The present invention also provides another semiconductor device, comprising: a semiconductor substrate having a first region and a second region, wherein the first region is an NMOS device region, and the second region is a PMOS device region; formed on the A first gate structure on the first region and a second gate structure formed on the second region, wherein the first gate structure includes: an interface layer on the semiconductor substrate, an The first high-k gate dielectric layer on the interface layer, the second high-k gate dielectric layer on the first high-k gate dielectric layer, and the third high-k gate dielectric layer on the second high-k gate dielectric layer A gate dielectric layer, a metal gate layer on the third high-k gate dielectric layer, wherein the dielectric constant of the second high-k gate dielectric layer is higher than that of the first and third high-k gate dielectric layers electrical constant; the second gate structure includes: an interface layer on the semiconductor substrate, a fourth high-k gate dielectric layer on the interface layer, and a fourth high-k gate dielectric layer on the fourth high-k gate dielectric layer The fifth high-k gate dielectric layer, the sixth high-k gate dielectric layer on the fifth high-k gate dielectric layer, and the metal gate layer on the sixth high-k gate dielectric layer, wherein the fifth high-k gate dielectric layer The dielectric constant of the k-gate dielectric layer is higher than that of the fourth and sixth high-k gate dielectric layers.

The present invention also provides another method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate having a first region and a second region, wherein the first region is an NMOS device region, and the second region is a PMOS device region; forming an interface layer on the semiconductor substrate; forming a first high-k gate dielectric layer, a second high-k gate dielectric layer and a third high-k gate dielectric layer successively on the interface layer, wherein the The dielectric constant of the second high-k gate dielectric layer is higher than the dielectric constant of the first and third high-k gate dielectric layers; respectively removing the third high-k gate dielectric layer, the third high-k gate dielectric layer on the second region of the semiconductor substrate, The second high-k gate dielectric layer, the first high-k gate dielectric layer; the fourth high-k gate dielectric layer, the fifth high-k gate dielectric layer and the sixth high-k gate dielectric layer are successively formed on the device, wherein the The dielectric constant of the fifth high-k gate dielectric layer is higher than the dielectric constant of the fourth and sixth high-k gate dielectric layers; respectively remove the sixth high-k gate dielectric layer on the first region of the semiconductor substrate , the fifth high-k gate dielectric layer, and the fourth high-k gate dielectric layer; forming a metal gate layer on the device; processing the device to respectively form a first gate structure belonging to the first region and a gate structure belonging to the first region The second gate structure of the two regions.

The present invention inserts a layer of higher-k dielectric inside the high-k gate dielectric layer of the MOS device, and the higher-k dielectric serves as the main high-k dielectric to effectively reduce the thickness of the equivalent oxide layer; using the higher-k dielectric and the upper and lower high The k-gate dielectric layer forms reverse dipoles, which cancel each other out, and obtain a smaller equivalent oxide thickness (EOT) under the condition of effectively adjusting the threshold voltage.

Description of drawings

1 shows a flowchart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

2-7 show schematic diagrams of various manufacturing stages of a semiconductor device according to a first embodiment of the present invention;

8 shows a flowchart of a method of manufacturing a semiconductor device according to a second embodiment of the present invention; and

9-19 show schematic diagrams of various manufacturing stages of a semiconductor device according to a second embodiment of the present invention.

Detailed ways

The present invention generally relates to a manufacturing method of a semiconductor device, in particular to a method for adjusting threshold voltage characteristics. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. For example, such that the first and second features may not be in direct contact.

first embodiment

Referring to FIG. 1 , FIG. 1 shows a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method may be involved in the formation of integrated circuits or portions thereof, which may include static random access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors and inductors, and active components such as P-channel field Effect Transistor (PFET), N-Channel Field Effect Transistor (NFET), Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Complementary Metal Oxide Semiconductor (CMOS) Transistor, Bipolar Transistor, High Voltage Transistor, High Frequency Transistor, Other Memory Units , combinations thereof and/or other semiconductor devices.

In step 301, a semiconductor substrate 402 (eg, a wafer) is provided. Refer to Figure 2. In an embodiment, substrate 402 includes a silicon substrate in a crystalline structure. As known in the art, the substrate may include various doping configurations (eg, p-type substrate or n-type substrate) according to design requirements. Other examples of substrates include other elemental semiconductors such as germanium and diamond. Alternatively, the substrate may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, for enhanced performance, the substrate may optionally include an epitaxial layer (epi layer), and/or a silicon-on-insulator (SOI) structure. Still further, the substrate may include various features formed thereon, including active regions, source and drain regions within the active regions, isolation regions (e.g., shallow trench isolation (STI)), and/or For other features known in the art, the semiconductor substrate may be provided through pre-process treatment, for example, after a cleaning process. The cleaning solution includes H ₂ SO ₄ acid, HCl acid, H ₂ O ₂ , NH ₄ OH, HF acid etc.

Step 302 , forming an interface layer 408 on the semiconductor substrate 402 . As shown in FIG. 2 , an insulating interfacial layer 408 is grown on the semiconductor substrate 402 . In this embodiment, the insulating interfacial layer 408 is SiO ₂ , and other materials can also be used, such as silicon nitride or silicon oxynitride materials.

Step 303 , forming a first high-k gate dielectric layer 410 on the interface layer 408 . As shown in FIG. 3 , a first high-k gate dielectric layer 410 is deposited on the insulating interfacial layer 408 . Wherein, the first high-k gate dielectric layer 410 may include a high-k material. For NMOS devices, the dielectric constant of the first high-k gate dielectric layer 410 ranges from 12 to 25. Examples of high-k materials include, for example, HfLaO _x , HfLaON, HfSiO _x , HfSiON, La ₂ O ₃ , Y ₂ O ₃ , MgO, Dy ₂ O ₃ , Gd ₂ O ₃ or other suitable materials; for PMOS devices, the dielectric constant of the first high-k gate dielectric layer 410 is in the range of 8-25, and examples of high-k materials include, for example _HfAlOx , HfAlON, _Al2O3 , _TiO2 , _ZrO2 or combinations _thereof or other suitable materials. The first high-k gate dielectric layer 410 can be formed by thermal oxidation, chemical vapor deposition, or atomic layer deposition (ALD). This is just an example and not limited thereto.

Step 304 , forming a second high-k gate dielectric layer 412 on the first high-k gate dielectric layer 410 . As shown in FIG. 4 , a second high-k gate dielectric layer 412 is deposited on the first high-k gate dielectric layer 410 . Wherein, the second high-k gate dielectric layer 412 may include a high-k material with a higher dielectric constant than the first high-k gate dielectric layer 410 . The material may be HfO ₂ , La ₂ O ₃ , HfTiO _x , HfLaO _x , TiO ₂ , Ta ₂ O ₅ , silicide or a combination thereof, and the like. For NMOS and PMOS devices, the dielectric constant of the second high-k gate dielectric layer 412 is in the range of 16-80, which is higher than the dielectric constant of the first high-k gate dielectric layer 410 . The second high-k gate dielectric layer 412 can be formed by thermal oxidation, chemical vapor deposition, or atomic layer deposition (ALD). This is just an example and not limited thereto.

Step 305 , forming a third high-k gate dielectric layer 414 on the second high-k gate dielectric layer 412 . As shown in FIG. 5 , a third high-k gate dielectric layer 414 is deposited on the second high-k gate dielectric layer 412 . Wherein, the third high-k gate dielectric layer 414 may include a high-k material, for example, a material having a higher dielectric constant than silicon oxide. For NMOS devices, the dielectric constant of the third high-k gate dielectric layer 414 ranges from 12 to 25. Examples of high-k materials include, for example, HfLaO _x , HfLaON, HfSiO _x , HfSiON, La ₂ O ₃ , Y ₂ O ₃ , MgO, Dy ₂ O ₃ , Gd ₂ O ₃ or other suitable materials; for PMOS devices, the dielectric constant of the third high-k gate dielectric layer 414 is in the range of 8-25, and examples of high-k materials include, for example _HfAlOx , HfAlON, _Al2O3 , _TiO2 , _ZrO2 or combinations _thereof or other suitable materials. Wherein, the dielectric constant of the third high-k gate dielectric layer 414 is lower than that of the second high-k gate dielectric layer 412 . In particular, the third high-k gate dielectric layer 214 and the first high-k gate dielectric layer 210 may be made of the same material or different materials. The third high-k gate dielectric layer 414 can be formed by thermal oxidation, chemical vapor deposition, or atomic layer deposition (ALD). This is just an example and not limited thereto.

Step 306 , forming a metal gate layer 422 on the third high-k gate dielectric layer 414 . As shown in FIG. 6, a metal gate layer 422 is deposited on the third high-k gate dielectric layer 414, wherein the metal gate layer 422 is formed by selecting elements from the group comprising the following elements: TiN, TaN, MoN, HfN, TaAlN, TiAlN , MoAlN, HfAlN, TaYbN, TaErN, TaTbN, TaC, HfC, TaSiC, HfSiC, Pt, Ru, Ir, W, Mo, Re, RuO _x , RuTax, _HfRux , polysilicon, metal silicide or _a combination of the above materials . In this embodiment, the metal gate layer 422 can use atomic layer deposition, chemical vapor deposition (CVD), high density plasma CVD, sputtering or other suitable methods. The above is merely an example and not limited thereto.

Step 307, processing the device to form a gate structure. As shown in FIG. 7, the device is patterned to form gate structures. The device can be patterned using dry etching or wet etching techniques. This is just an example, and the present invention is not limited thereto.

In the MOS device of this embodiment, a layer of higher-k dielectric, that is, a second high-k gate dielectric layer is inserted in the first and third high-k gate dielectric layers. The second high-k gate dielectric layer is used as the main high-k dielectric layer, which can effectively reduce the thickness of the equivalent oxide layer; using the higher-k gate dielectric layer to form a reverse dipole with the first and third high-k gate dielectric layers, cancel each other out, and obtain a smaller equivalent oxide layer thickness under the condition of effectively adjusting the threshold voltage.

second embodiment

Only the aspects of the second embodiment that differs from the first embodiment will be described below. Parts not described should be considered to be performed by the same steps, methods or processes as those in the first embodiment, and thus will not be described again.

Referring to FIG. 8 , FIG. 8 shows a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Step 101 , providing a semiconductor substrate 202 (eg, a wafer) having a first region 204 and a second region 206 . Refer to Figure 8. In an embodiment, substrate 202 includes a silicon substrate in a crystalline structure. As is known in the art, the substrate may include various doping configurations (eg, p-type substrate or n-type substrate) according to design requirements, wherein the first region 204 has a different doping profile than the second region 206 type; for example, the first region 204 is the region of the NMOS device; the second region is the region of the PMOS device, or vice versa. Other examples of substrates include other elemental semiconductors such as germanium and diamond. Alternatively, the substrate may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, for enhanced performance, the substrate may optionally include an epitaxial layer (epi layer), and/or a silicon-on-insulator (SOI) structure. Still further, the substrate may include various features formed thereon, including active regions, source and drain regions within the active regions, isolation regions (e.g., shallow trench isolation (STI)), and/or For other features known in the art, the semiconductor substrate may be provided through pre-process treatment, for example, after a cleaning process. The cleaning solution includes H ₂ SO ₄ acid, HCl acid, H ₂ O ₂ , NH ₄ OH, HF acid etc. Referring to the example of FIG. 8 , a semiconductor substrate 202 including a first region 204 and a second region 206 is provided.

Step 102 , forming an interface layer 208 on the semiconductor substrate 202 . As shown in FIG. 9 , an insulating interfacial layer 208 is grown on the semiconductor substrate 202 . In this embodiment, the insulating interfacial layer 208 is SiO ₂ , and other materials can also be used, such as silicon nitride or silicon oxynitride materials.

Step 103, forming the gate stack of the NMOS device in the first region, specifically: forming the first high-k gate dielectric layer 210, the second high-k gate dielectric layer 212, and the third high-k gate dielectric layer on the interface layer 208 successively 214. As shown in FIG. 10 , firstly, a first high-k gate dielectric layer 210 is deposited on the insulating interfacial layer 208 . Then, as shown in FIG. 11 , a second high-k gate dielectric layer 212 is deposited on the first high-k gate dielectric layer 210 . After that, as shown in FIG. 12 , a third high-k gate dielectric layer 214 is deposited on the second high-k gate dielectric layer 212 . Wherein, the first high-k gate dielectric layer 210 and the third high-k gate dielectric layer 214 may include a high-k material, such as a material having a higher dielectric constant than silicon oxide. For the first region as an NMOS device, the dielectric constant of the first high-k gate dielectric layer 210 and the third high-k gate dielectric layer 214 ranges from 12 to 25, and examples of high-k materials include, for example, HfLaO _x , HfLaON, HfSiO _x , HfSiON, La ₂ O ₃ , Y ₂ O ₃ , MgO, Dy ₂ O ₃ , Gd ₂ O ₃ or combinations thereof or other suitable materials. In particular, the first high-k gate dielectric layer 210 and the third high-k gate dielectric layer 214 may be made of the same material or different materials. The dielectric constant of the second high-k gate dielectric layer 212 is higher than that of the first high-k gate dielectric layer 210 and the third high-k gate dielectric layer 214 . For example, the dielectric constant of the second high-k gate dielectric layer 212 may range from 16-80. The material can be HfO ₂ , La ₂ O ₃ , HfTiO _x , HfLaO _x , TiO ₂ , Ta ₂ O ₅ , silicide, or a combination thereof. The first high-k gate dielectric layer 210 , the second high-k gate dielectric layer 212 and the third high-k gate dielectric layer 214 can be formed by thermal oxidation, chemical vapor deposition, or atomic layer deposition (ALD). This is just an example and not limited thereto.

Step 104 , respectively removing the third high-k gate dielectric layer 214 , the second high-k gate dielectric layer 212 , and the first high-k gate dielectric layer 210 on the second region 206 of the semiconductor substrate 202 . Firstly, a mask layer is covered on the third high-k gate dielectric layer 214 on the first region 204, and then the third high-k gate dielectric layer 214 on the second region 206 not covered by the mask layer is etched. , and then, etching the second high-k gate dielectric layer 212 , and then etching the first high-k gate dielectric layer 210 . Then, the mask layer on the third high-k gate dielectric layer 214 on the first region 204 is removed to form the device structure as shown in FIG. 13 .

Step 105, forming the gate stack of the PMOS device in the second region, specifically: successively forming the fourth high-k gate dielectric layer 216, the fifth high-k gate dielectric layer 218, and the sixth high-k gate dielectric layer on the device 220. As shown in FIG. 14 , firstly, a fourth high-k gate dielectric layer 216 is deposited on the device as shown in FIG. 13 . Then, as shown in FIG. 15 , a fifth high-k gate dielectric layer 218 is deposited on the fourth high-k gate dielectric layer 216 . Afterwards, as shown in FIG. 16 , a sixth high-k gate dielectric layer 220 is deposited on the fifth high-k gate dielectric layer 218 . Wherein, the fourth high-k gate dielectric layer 216 and the sixth high-k gate dielectric layer 220 may include a high-k material, such as a material having a higher dielectric constant than silicon oxide. For the second region as a PMOS device, the dielectric constant of the fourth high-k gate dielectric layer 216 and the sixth high-k gate dielectric layer 220 ranges from 8 to 25, and examples of high-k materials include, for example, HfAlO _x , HfAlON, Al ₂ O ₃ , TiO ₂ , ZrO ₂ or combinations thereof or other suitable materials. In particular, the fourth high-k gate dielectric layer 216 and the sixth high-k gate dielectric layer 220 may be made of the same material or different materials. The dielectric constant of the fifth high-k gate dielectric layer 218 is higher than that of the fourth high-k gate dielectric layer 216 and the sixth high-k gate dielectric layer 220 . For example, the dielectric constant of the fifth high-k gate dielectric layer 218 is in the range of 16-80. The material may be HfO ₂ , La ₂ O ₃ , HfTiO _x , HfLaO _x , TiO ₂ , Ta ₂ O ₅ , silicide or a combination thereof, and the like. The fourth high-k gate dielectric layer 216 , the fifth high-k gate dielectric layer 218 and the sixth high-k gate dielectric layer 220 can be formed by thermal oxidation, chemical vapor deposition, or atomic layer deposition (ALD). This is just an example and not limited thereto.

Step 106 , respectively removing the sixth high-k gate dielectric layer 220 , the fifth high-k gate dielectric layer 218 , and the fourth high-k gate dielectric layer 216 on the first region 204 of the semiconductor substrate 202 . Chemical mechanical polishing is performed on the sixth high-k gate dielectric layer 220 , the fifth high-k gate dielectric layer 218 and the fourth high-k gate dielectric layer 216 on the first region 204 to form the device structure shown in FIG. 17 .

Step 107, forming a metal gate layer 222 on the device. As shown in FIG. 18, a metal gate layer 222 is deposited on the device as shown in FIG. 17, wherein the metal gate layer 222 is formed by selecting from the group comprising the following metals: TiN, TaN, MoN, HfN, TaAlN, TiAlN, MoAlN , HfAlN, TaYbN, TaErN, TaTbN, TaC, HfC, TaSiC, HfSiC, Pt, Ru, Ir, W, Mo, Re, RuO _x , _RuTax , _HfRux , polysilicon, metal silicide or a combination of the above materials. In this embodiment, the metal gate layer 222 can use atomic layer deposition, chemical vapor deposition (CVD), high density plasma CVD, sputtering or other suitable methods. The above is merely an example and not limited thereto.

Step 108 , processing the device to form a first gate structure belonging to the first region 204 and a second gate structure belonging to the second region 206 , thereby forming an NMOS device and a PMOS device. As shown in FIG. 19 , the first region 204 and the second region 206 are patterned to form a first gate structure and a second gate structure. The first region and the second region can be patterned by using dry etching or wet etching technology. This is just an example, and the present invention is not limited thereto.

The present invention inserts a layer of higher-k dielectric inside the high-k gate dielectric layer of the MOS device, and the higher-k dielectric serves as the main high-k dielectric to effectively reduce the thickness of the equivalent oxide layer; using the higher-k dielectric and the upper and lower high The k-gate dielectric layer forms reverse dipoles, which cancel each other out, and obtain a smaller equivalent oxide thickness (EOT) under the condition of effectively adjusting the threshold voltage.

Although the example embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to these embodiments without departing from the spirit of the invention and the scope of protection as defined by the appended claims. For other examples, those of ordinary skill in the art will readily understand that the order of process steps may be varied while remaining within the scope of the present invention.

In addition, the scope of application of the present invention is not limited to the process, mechanism, manufacture, material composition, means, method and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that for the processes, mechanisms, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, they are implemented in accordance with the present invention Corresponding embodiments described which function substantially the same or achieve substantially the same results may be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacture, material compositions, means, methods or steps within their protection scope.

Claims (24)

1. semiconductor device comprises:

Semiconductor substrate;

Be formed at the grid structure on the described Semiconductor substrate,

Wherein, described grid structure comprises: at the boundary layer on the described Semiconductor substrate, at the first high-k gate dielectric layer on the described boundary layer, at the second high-k gate dielectric layer on the described first high-k gate dielectric layer, at the 3rd high-k gate dielectric layer on the described second high-k gate dielectric layer, metal gate layer on described the 3rd high-k gate dielectric layer, the dielectric constant of the wherein said second high-k gate dielectric layer is higher than described first and the dielectric constant of the 3rd high-k gate dielectric layer.

2. device according to claim 1, wherein for nmos device, the dielectric constant of described the first, the 3rd high-k gate dielectric layer is 12-25; For the PMOS device, the dielectric constant of described the first, the 3rd high-k gate dielectric layer is 8-25.

3. device according to claim 2 wherein for nmos device, selects unit usually to form the group of described the first, the 3rd high-k gate dielectric layer column element under comprising: HfLaO _x, HfLaON, HfSiO _x, HfSiON, La ₂O ₃, Y ₂O ₃, MgO, Dy ₂O ₃, Gd ₂O ₃Or its combination; For the PMOS device, select unit usually to form the group of described the first, the 3rd high-k gate dielectric layer column element under comprising: HfAlO _x, HfAlON, Al ₂O ₃, TiO ₂, ZrO ₂Or its combination.

4. device according to claim 1, the dielectric constant of the wherein said second high-k gate dielectric layer are 16-80.

5. device according to claim 4 selects unit usually to form the group of wherein said second high-k gate dielectric layer column element under comprising: HfO ₂, La ₂O ₃, HfTiO _x, HfLaO _x, TiO ₂, Ta ₂O ₅, silicide or its combination.

6. device according to claim 1 selects unit usually to form the group of wherein said metal gate layer column element under comprising: TiN, TaN, MoN, HfN, TaAlN, TiAlN, MoAlN, HfAlN, TaYbN, TaErN, TaTbN, TaC, HfC, TaSiC, HfSiC, Pt, Ru, Ir, W, Mo, Re, RuO _x, RuTa _x, HfRu _x, polysilicon, metal silicide or its combination.

7. the manufacture method of a semiconductor device comprises:

Semiconductor substrate is provided;

On described Semiconductor substrate, form boundary layer;

On described boundary layer, form the first high-k gate dielectric layer;

On the described first high-k gate dielectric layer, form the second high-k gate dielectric layer;

On the described second high-k gate dielectric layer, form the 3rd high-k gate dielectric layer;

On described the 3rd high-k gate dielectric layer, form the metal gate layer;

Described device is processed, to form grid structure;

Wherein, the dielectric constant of the described second high-k gate dielectric layer is higher than described first and the dielectric constant of the 3rd high-k gate dielectric layer.

8. method according to claim 7, wherein for nmos device, the dielectric constant of described the first, the 3rd high-k gate dielectric layer is 12-25; For the PMOS device, the dielectric constant of described the first, the 3rd high-k gate dielectric layer is 8-25.

9. method according to claim 8 wherein for nmos device, selects unit usually to form the group of described the first, the 3rd high-k gate dielectric layer column element under comprising: HfLaO _x, HfLaON, HfSiO _x, HfSiON, La ₂O ₃, Y ₂O ₃, MgO, Dy ₂O ₃, Gd ₂O ₃Or its combination; For the PMOS device, select unit usually to form the group of described the first, the 3rd high-k gate dielectric layer column element under comprising: HfAlO _x, HfAlON, Al ₂O ₃, TiO ₂, ZrO ₂Or its combination.

10. method according to claim 7, the dielectric constant of the wherein said second high-k gate dielectric layer are 16-80.

11. method according to claim 10 selects unit usually to form the group of wherein said second high-k gate dielectric layer column element under comprising: HfO ₂, La ₂O ₃, HfTiO _x, HfLaO _x, TiO ₂, Ta ₂O ₅, silicide or its combination.

12. method according to claim 7 selects unit usually to form the group of wherein said metal gate layer column element under comprising: TiN, TaN, MoN, HfN, TaAlN, TiAlN, MoAlN, HfAlN, TaYbN, TaErN, TaTbN, TaC, HfC, TaSiC, HfSiC, Pt, Ru, Ir, W, Mo, Re, RuO _x, RuTa _x, HfRu _x, polysilicon, metal silicide or its combination.

13. a semiconductor device comprises:

Semiconductor substrate with first area and second area, wherein said first area are the nmos device zone, and described second area is the PMOS device area;

Be formed at first grid structure and the second grid structure that is formed on the described second area on the described first area,

Wherein, described first grid structure comprises: at the boundary layer on the described Semiconductor substrate, at the first high-k gate dielectric layer on the described boundary layer, at the second high-k gate dielectric layer on the described first high-k gate dielectric layer, at the 3rd high-k gate dielectric layer on the described second high-k gate dielectric layer, metal gate layer on described the 3rd high-k gate dielectric layer, the dielectric constant of the wherein said second high-k gate dielectric layer is higher than described first and the dielectric constant of the 3rd high-k gate dielectric layer;

Described second grid structure comprises: at the boundary layer on the described Semiconductor substrate, at the 4th high-k gate dielectric layer on the described boundary layer, at the 5th high-k gate dielectric layer on described the 4th high-k gate dielectric layer, at the 6th high-k gate dielectric layer on described the 5th high-k gate dielectric layer, metal gate layer on described the 6th high-k gate dielectric layer, the dielectric constant of wherein said the 5th high-k gate dielectric layer is higher than the described the 4th and the dielectric constant of the 6th high-k gate dielectric layer.

14. device according to claim 13, wherein for described first grid structure, the dielectric constant of described the first, the 3rd high-k gate dielectric layer is 12-25; For described second grid structure, the dielectric constant of described the 4th, the 6th high-k gate dielectric layer is 8-25.

15. device according to claim 14 wherein for described first grid structure, selects unit usually to form the group of described the first, the 3rd high-k gate dielectric layer column element under comprising: HfLaO _x, HfLaON, HfSO _x, HfSiON, La ₂O ₃, Y ₂O ₃, MgO, Dy ₂O ₃, Gd ₂O ₃Or its combination; For described second grid structure, select unit usually to form the group of described the 4th, the 6th high-k gate dielectric layer column element under comprising: HfAlO _x, HfAlON, Al ₂O ₃, TiO ₂, ZrO ₂Or its combination.

16. device according to claim 13, the dielectric constant of wherein said the second, the 5th high-k gate dielectric layer are 16-80.

17. device according to claim 16 selects unit usually to form the group of wherein said the second, the 5th high-k gate dielectric layer column element under comprising: HfO ₂, La ₂O ₃, HfTiO _x, HfLaO _x, TiO ₂, Ta ₂0 ₅, silicide or its combination.

18. device according to claim 13 selects unit usually to form the group of wherein said metal gate layer column element under comprising: TiN, TaN, MoN, HfN, TaAlN, TiAlN, MoAlN, HfAlN, TaYbN, TaErN, TaTbN, TaC, HfC, TaSiC, HfSiC, Pt, Ru, Ir, W, Mo, Re, RuO _x, RuTa _x, HfRu _x, polysilicon, metal silicide or above-mentioned material combination.

19. the manufacture method of a semiconductor device, described method comprises:

Semiconductor substrate with first area and second area is provided, and wherein said first area is the nmos device zone, and described second area is the PMOS device area;

On described Semiconductor substrate, form boundary layer;

Successively form the first high-k gate dielectric layer, the second high-k gate dielectric layer and the 3rd high-k gate dielectric layer on described boundary layer, wherein, the dielectric constant of the described second high-k gate dielectric layer is higher than described first and the dielectric constant of the 3rd high-k gate dielectric layer;

Remove the 3rd high-k gate dielectric layer, the second high-k gate dielectric layer, the first high-k gate dielectric layer on the described Semiconductor substrate second area respectively;

Successively form the 4th high-k gate dielectric layer, the 5th high-k gate dielectric layer and the 6th high-k gate dielectric layer on described device, wherein, the dielectric constant of described the 5th high-k gate dielectric layer is higher than described the 4th, the 6th high-k gate dielectric layer;

Remove the 6th high-k gate dielectric layer, the 5th high-k gate dielectric layer, the 4th high-k gate dielectric layer on the described Semiconductor substrate first area respectively;

On described device, form the metal gate layer;

Described device is processed, to form first grid structure that belongs to the first area and the second grid structure that belongs to second area respectively.

20. method according to claim 19, wherein for described first grid structure, the dielectric constant of described the first, the 3rd high-k gate dielectric layer is 12-25; For described second grid structure, the dielectric constant of the 4th, the 6th high-k gate dielectric layer is 8-25.

21. method according to claim 20 wherein for described first grid structure, selects unit usually to form the group of described the first, the 3rd high-k gate dielectric layer column element under comprising: HfLaO _x, HfLaON, HfSiO _x, HfSiON, La ₂O ₃, Y ₂O ₃, MgO, Dy ₂O ₃, Gd ₂O ₃Or its combination; For described second grid structure, select unit usually to form the group of described the 4th, the 6th high-k gate dielectric layer column element under comprising: HfAlO _x, HfAlON, Al ₂O ₃, TiO ₂, ZrO ₂Or its combination.

22. method according to claim 19, the dielectric constant of wherein said the second, the 5th high-k gate dielectric layer are 16-80.

23. method according to claim 22 selects unit usually to form the group of wherein said the second, the 5th high-k gate dielectric layer column element under comprising: HfO ₂, La ₂O ₃, HfFiO _x, HfLaO _x, TiO ₂, Ta ₂O ₅, silicide or its combination.

24. method according to claim 19 selects unit usually to form the group of wherein said metal gate layer column element under comprising: TiN, TaN, MoN, HfN, TaAlN, TiAlN, MoAlN, HfAlN, TaYbN, TaErN, TaTbN, TaC, HfC, TaSiC, HfSiC, Pt, Ru, Ir, W, Mo, Re, RuO _x, RuTa _x, HfRu _x, polysilicon, metal silicide or above-mentioned material combination.

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