CN102184944B - Junction terminal structure of lateral power device - Google Patents

Abstract

The invention discloses a junction terminal structure of a lateral power device. The structure at least comprises three semiconductor doping regions, a side wall oxidation zone and a side wall field plate region, which are sequentially connected, wherein the side wall field plate region is positioned at the two ends of the device; the doping region positioned at one end is a first kind of conducting type and forms a channel region (or the anode) of the device; the doping region positioned at the other end is a second kind of conducting type and forms a drain electrode region (or the cathode) of the device; the semiconductor doping region positioned in the middle is the second kind of conducting type and forms a drift region of the device; the lower part of the drift region is connected with an epitaxial layer; the upper part of the drift region is connected with a field oxide layer; the side of the drift region is connected with an oxidation zone; polysilicon is etched and deposited in the side wall oxidation zones of a source area and a drain area to form a slope-shaped or multi-step shaped three-dimensional (3D) field plate; the field plate is in electric contact with a grid electrode and a drain electrode respectively; and the side wall field plate is required to extend into the surface of a substrate to enter the substrate. When a PN diode, a lateral diffused metal oxide semiconductor (LDMOS) or a lateral insulated gate bipolar transistor (LIGBT) is manufactured through the structure, the structure has the advantages of high breakdown voltage, low on resistance, simple process, low cost and the like.

Description

A Junction Termination Structure for Lateral Power Devices

technical field

The invention belongs to the field of semiconductor power device technology and semiconductor technology, and particularly relates to the junction terminal technology of lateral power devices for high-power and high-voltage applications, such as lateral diffusion field effect transistor LDMOS, lateral high-voltage diode, lateral insulated gate bipolar transistor LIGBT and the like.

Background technique

As we all know, in the design process of lateral power devices, the interaction of factors such as breakdown voltage, on-resistance, process complexity, and reliability must be considered comprehensively to achieve a reasonable compromise. Usually, the improvement of one aspect of performance often leads to the degradation of other aspects of performance, and there is such a contradictory relationship between breakdown voltage and on-resistance. How to keep the on-resistance constant or minimize the on-resistance while increasing the breakdown voltage has always been a research hotspot.

For conventional lateral power devices, due to the junction edge curvature effect, the breakdown voltage will be greatly reduced compared with the theoretical value, especially in the case of shallow junction diffusion and small curvature. In order to solve this problem, A.S.Grove et al. published in March 1967 in the article "The Effect of Surface Electric Field on the Breakdown Voltage of Planar PN Junction" (IEEE TransElectron Devices, vol.ED-14, pp.157-162) first The field plate technology was proposed. At first it was used to reduce the peak value of the PN junction electric field. Because of its simple structure, fully compatible process and integrated circuit process, and obvious effect, it was quickly used in high-voltage discrete junction devices, power MOS devices, and high-voltage power integrated circuits. has been widely applied. The basic structure of the field plate is shown in FIG. 1 . The semiconductor substrate 100 is doped twice to form a semiconductor region 102 of the first conductivity type and a semiconductor region 104 of the second conductivity type, that is, a PN junction is formed. A layer of metal layer 110 is covered on the silicon dioxide layer 120 above the junction. We call this metal layer a metal field plate. If an appropriate voltage is biased on the field plate, interface charges will be induced on the upper surface of the silicon, and these interface charges will generate The electric field can greatly weaken the peak electric field of the PN junction, thereby increasing the breakdown voltage.

US Patent 6468837 applies the field plate technology to RESURF (reduced surface field) devices, and provides the implementation steps in the process. Its structure is shown in Figure 2. It mainly consists of a lightly doped semiconductor region 100 of the first conductivity type epitaxial layer, a semiconductor region 102 of the first conductivity type, a heavily doped semiconductor region 101 of the first conductivity type, and a semiconductor region of the second conductivity type. 103, 105, lightly doped second-type conductivity type semiconductor region 104 (Resurf implanted region), field oxygen region 120 covering the semiconductor region 104, gate field plate 110 extending over half the length of the field oxygen, etc. composition. The difference between this structure and ordinary Resurf LDMOS devices is that the gate extends a field plate, which suppresses the peak field on the junction edge surface, thereby increasing the breakdown voltage. However, for this common planar field plate, a prominent problem is that a high electric field peak will be formed at the boundary of the field plate, which limits the further improvement of the breakdown voltage.

In order to solve the problem of high electric field peaks at the edge of the field plate, K.Brieger et al. published the article "An Analytical Approximation of the Optimal Field Plate Profile" in May 1988 (IEEE TransElectron Devices, Vol.35, pp.684-688 ) first showed through theoretical calculation that when the thickness of the oxide layer under the field plate increases continuously with a certain gradient, the peak value of the electric field under the field plate can be completely eliminated, so the concept of the inclined field plate was proposed. However, although the slanted field plate can achieve a completely uniform surface electric field, it is difficult to manufacture, especially not compatible with the integrated circuit process. US Patent No. 753930 provides an LDMOS structure with a multi-step field plate structure, as shown in FIG. 3 . Different from the conventional LDMOS, a stepped oxide layer 120 and a polysilicon field plate 110 are added near the drain end, and the field plate of the lowest order is electrically connected to the source end. The electric field distribution in the drift region of the lower surface of the structure is more uniform, and the withstand voltage characteristics are improved to a certain extent. However, the disadvantage of this method is that multiple additional reticles and multi-step additional processes are required to manufacture the multi-step field plate, which increases the complexity of the process and increases the cost.

US Patent 7230313 proposes a segmented field plate lateral power device structure, as shown in FIG. 4 . The salient feature of this structure is that there are multiple field plates 110 , 112 , 114 , 116 separated by a certain distance on the surface oxide layer 120 . Each field plate is biased with different voltages through a voltage divider network composed of multi-resistor connections, which can make the peak value of the electric field at the edge of each field plate tend to be the same, that is, the critical breakdown electric field, thereby increasing the breakdown voltage. But for the horizontal power device with this structure, the voltage divider network is complicated and not easy to adjust.

The various structures mentioned above all prepare field plates on the surface of power devices to adjust the surface electric field, but the preparation process of multi-step and inclined field plates on the surface is very complicated, and the effect is not very ideal.

Contents of the invention

Technical problem: The purpose of the present invention is to provide another junction termination structure in a lateral power device. With this structure, not only can a multi-step field plate of any geometric size and any number of steps be realized on the sidewall, but also a slope field plate of any shape can be realized. preparation, so as to give full play to the field drop effect of the field plate, improve the breakdown characteristics to the greatest extent, and at the same time suppress the electric field in the body, so that the optimal value of the concentration in the drift region can be improved, thereby reducing the on-resistance and increasing the working current. In addition, the structure manufacturing process only needs to add a mask to realize the preparation of multi-step field plates and slope field plates, which are difficult to achieve in conventional planar field plates. The process is basically fully compatible with the standard CMOS process, thereby reducing manufacturing costs. .

Technical solution: The junction terminal structure of the lateral power device of the present invention includes a substrate region, a semiconductor region with the first type of conductivity, and a semiconductor region with the second type of conductivity with high doping concentration. A semiconductor region of the second conductivity type with a low doping concentration is separated from a sidewall oxide layer juxtaposed side by side. The semiconductor region constitutes the drift region of the power device, and the sidewall oxide layer is photolithographically deposited near both ends. A slope-shaped polysilicon field plate and a second slope-shaped polysilicon field plate are electrically connected to the gate and the drain respectively.

The semiconductor region serves as a semiconductor region of the second conductivity type with a low doping concentration in the drift region, and its concentration is uniform.

The side wall oxide layer is located on the side of the semiconductor region as the drift region, and its vertical depth exceeds the thickness of the drift region and enters into the substrate region.

The vertical depth of the first slope-shaped polysilicon field plate and the second slope-shaped polysilicon field plate needs to exceed the thickness of the semiconductor region serving as the drift region and enter the substrate region.

The substrate region is a semiconductor material, or a silicon dioxide oxide layer SOI.

The first slope-shaped polysilicon field plate and the second slope-shaped polysilicon field plate can also be multi-stepped or multi-segmented segmented field plates, and the segmented field plates are floating or biased to different voltages by the voltage divider network .

The sidewall oxide is silicon dioxide.

The specific form of the lateral power device is a lateral diffusion field effect transistor LDMOS, a lateral PN diode, a lateral insulated gate bipolar transistor LIGBT, or a lateral thyristor.

Beneficial effects: the side wall field plate structure of the present invention can be prepared by the following process. First, etch and fill the sidewall oxide layer. This step can be completed by using the dielectric isolation process without any additional mask and additional process. Secondly, the photolithography field plate pattern, the shape of the pattern is determined by the results of numerical simulation, and its depth should be Slightly larger than the thickness of the top layer of silicon, and then deposited polysilicon to form a field plate, and then the processing of LDMOS can be completed according to the standard CMOS process. It can be seen that this process is a process scheme that is fully compatible with the standard CMOS process. It only needs to add one photolithography, and by adjusting the pattern of the mask plate, it can complete the inclined field plate of any shape in the side direction, the stepped field plate of any step or each Fabrication of various types of floating field plates. The device prepared by this method can not only adjust the surface electric field, but also adjust the internal electric field to achieve the effect of greatly improving the breakdown voltage, and the concentration value of the drift region has also been greatly improved, and the I-V characteristics are better.

Description of drawings

Figure 1 is a schematic diagram of the structure of a planar PN junction field plate.

Figure 2 is a schematic diagram of the RESURF LDMOS planar field plate structure.

FIG. 3 is a schematic diagram of a planar multi-step field plate structure LDMOS.

Fig. 4 is a structural schematic diagram of an improved segmented field plate structure lateral power device.

FIG. 5 is a three-dimensional view of an LDMOS structure with a sidewall slanted field plate structure according to the present invention. The semiconductor region 101 of the first conductivity type with a high doping concentration forms the channel region of the LDMOS, and the semiconductor region 103 of the second conductivity type with a high doping concentration forms the drain terminal of the LDMOS, between the source terminal and the drain terminal The semiconductor region 102 of the second conductivity type with a lighter doping concentration is connected in parallel with the sidewall oxide layer 120, the semiconductor region 102 is used as a drift region, and the inside of the sidewall oxide layer 120 is photolithographically close to the two ends of the source electrode and the drain electrode. The slope-shaped field plates 110 and 112 are formed by depositing polysilicon. The field plate 110 is electrically connected to the gate 131 , and the field plate 112 is electrically connected to the drain 132 .

Fig. 6a is a top view of the LDMOS with a sidewall slant field plate structure according to the present invention.

FIG. 6b is a cross-sectional view of the LDMOS with a sidewall slanted field plate structure along the line AB in FIG. 6a according to the present invention.

FIG. 6c is a cross-sectional view of the LDMOS with a sidewall slanted field plate structure along the line CD in FIG. 6a according to the present invention.

Fig. 7a is a top view of a lateral PN junction with a sidewall slanted field plate structure according to the present invention.

Fig. 7b is a cross-sectional view of a transverse PN junction with a sidewall slanted field plate structure along line AB in Fig. 7a according to the present invention.

Fig. 8a is a top view of the LDMOS with sidewall multi-step field plate structure of the present invention. The difference from FIG. 6 is that the side wall field plates at both ends are respectively made into symmetrical multi-step shapes.

FIG. 8b is a cross-sectional view of the LDMOS with sidewall multi-step field plate structure according to the present invention along the line AB in FIG. 8a.

Fig. 9a is a form of the LDMOS with sidewall floating field plate structure according to the present invention. The difference from Figure 6 is that the sidewall field plates are made into segments in a floating shape, and the distance between the field plates gradually decreases from the source end to the middle of the drift region, and then gradually increases toward the drain end to form a symmetrical shape. Same length and width.

Fig. 9b is a cross-sectional view along line AB of Fig. 9a.

Fig. 10a is another form of the LDMOS with sidewall floating field plate structure of the present invention. As in Figure 9, the side field plates are made into segmented floating shapes, but the width of each segment field plate gradually decreases from the source end to the middle of the drift region, and then gradually increases toward the drain end to form a symmetrical shape. The plate spacing does not change.

Fig. 10b is a cross-sectional view along line AB of Fig. 10a.

Fig. 11a is a top view of a LIGBT with a sidewall slanted field plate structure according to the present invention.

Fig. 11b is a cross-sectional view along line AB of Fig. 11a.

Fig. 12 is a comparison diagram of equipotential line distribution, longitudinal electric field distribution and breakdown voltage of a conventional Resurf structure and a sidewall slanted field plate Resurf structure of the present invention.

Fig. 13 is a graph showing I-V output characteristic curves of a lateral power device with a conventional Resurf structure and a sidewall slanted field plate Resurf structure of the present invention.

Detailed ways

The invention provides a junction termination structure in a lateral power device. Fig. 5 is a 3D view of the structure, Fig. 6a is a top view of the structure, Fig. 6b is a cross-sectional view of the structure along line AB in Fig. 6a, and Fig. 6c is a cross-sectional view of the structure along line CD in Fig. 6a. It can be seen that in the silicon base on the substrate region 100 of the first conductivity type, the semiconductor region 101 of the first conductivity type with a high doping concentration is formed by twice high doping, and the high doping concentration The semiconductor region 103 of the second conductivity type, the two are connected by the semiconductor region 102 of the second conductivity type with a light doping concentration, the semiconductor region 102 is used as a drift region, and the sidewall of the semiconductor region 102 is filled with field oxygen to form a connection with it The sidewall oxide layer 120 is juxtaposed, and the sidewall oxide layer 120 extends vertically into the substrate region 100 . Photolithographically deposit polysilicon on both ends of the sidewall oxide layer 120 to form a first slope-shaped polysilicon field plate 110 and a second slope-shaped polysilicon field plate 112, the first slope-shaped polysilicon field plate 110 is electrically connected to the gate 131, and the second slope-shaped polysilicon field plate 110 is electrically connected The second slope-shaped polysilicon field plate 112 is electrically connected to the drain 132, and the first slope-shaped polysilicon field plate 110 and the second slope-shaped polysilicon field plate 112 also vertically extend beyond the upper surface of the substrate region 100 into the substrate region 100 .

The junction termination structure of a lateral power device includes a substrate region 100, a semiconductor region 101 with a first conductivity type, a semiconductor region 103 with a second conductivity type with a high doping concentration, and a semiconductor region 103 with a low conductivity type between the two. The semiconductor region 102 of the second conductivity type with doping concentration is separated from a sidewall oxide layer 120 juxtaposed on one side, the semiconductor region 102 constitutes the drift region of the power device, and the sidewall oxide layer 120 is photolithographically deposited near both ends The first slope-shaped polysilicon field plate 110 and the second slope-shaped polysilicon field plate 112 are electrically connected to the gate 131 and the drain 132 respectively.

It should be noted

(1) The concentration distribution of the semiconductor region 102 of the second conductivity type with low doping concentration is uniform.

(2) The material of the sidewall oxide layer 120 is silicon dioxide.

(3) The sidewall oxide layer 120, the first slope-shaped polysilicon field plate 110, and the second slope-shaped polysilicon field plate (112) all need to extend vertically into the interior of the substrate region 100 to suppress the electric field in the body .

(4) The substrate region 100 may be a lightly doped semiconductor (bulk silicon), or a silicon dioxide oxide layer (SOI).

(5) The side wall field plate region, that is, the first slope-shaped polysilicon field plate 110 and the second slope-shaped polysilicon field plate 112 can be made into a slope-shaped side wall, or can be made into a multi-step shape of the side wall (as shown in FIG. 8) It can also be made into various types of sidewall segmented field plates (as shown in Figures 9 and 10). The segmented field plates can be floating or biased with different voltages.

(6) The sidewall field plate structure described above can be used in combination with ordinary planar field plates to achieve a better field drop effect.

(7) The field plate structure described in (7) can also be used in power devices such as lateral PN diodes (as shown in FIG. 7 ), LIGBTs (as shown in FIG. 11 ), lateral thyristors, etc., to simultaneously improve the breakdown characteristics and conduction characteristics of the devices.

Working principle of the present invention:

Figure 12 is a comparison diagram of the equipotential line distribution, longitudinal electric field distribution and breakdown voltage between the conventional RESURF structure and the sidewall 3D slope field plate Resurf structure based on the preliminary simulation results. The structural parameters are the same for both structures, while the concentration profile in the drift region is optimized. It can be seen from Figure 12a that for the conventional RESURF structure, the surface equipotential lines at both ends of the drift region are dense and sparse in the middle, resulting in very high electric field peaks at both ends and reducing the breakdown voltage. For the 3D slanted field plate structure in Figure 12b, the distribution of equipotential lines in the drift region is almost uniform, and the surface electric field is approximately constant, so that the breakdown voltage is greatly improved. Figure 12c shows the longitudinal electric field distribution under the drain terminal under the same applied bias conditions. It can be seen that due to the shielding effect of the field plate, the longitudinal electric field distribution of the 3D oblique field plate is also more uniform than that of the conventional RESURF structure. The top silicon/ The peak electric field on the interface of the buried oxide layer is also lower, which shows that the 3D field plate also has the effect of improving the vertical withstand voltage. It can be seen from Figure 12d that the breakdown voltage of the 3D inclined field plate structure is greatly improved compared with the conventional RESURF structure, and the concentration of merit in the drift region is also higher.

Figure 13 compares the IV characteristic curves of the above two structures. It can be seen that the linear region resistance of the 3D oblique field plate structure is much smaller than that of the conventional RESURF structure, and its saturation current is also much higher than that of the conventional RESURF structure. The reason can be attributed to the fact that the optimal drift region concentration of the 3D field plate structure is greatly improved compared with the conventional RESURF structure.

According to the lateral power device structure provided by the present invention, lateral power devices with sidewall inclined field plates, multi-step field plates, and segmented field plate structures with excellent characteristics can be manufactured, examples are as follows:

1) LDMOS with sidewall slope field plate, as shown in Figure 5 and Figure 6. It includes a substrate region 100 of the first conductivity type, a semiconductor region 101 of the first conductivity type with a high doping concentration formed by twice high doping, a semiconductor region 103 of the second conductivity type of a high doping concentration, as the source and drain regions, respectively. The two are connected by a semiconductor region 102 of the second conductivity type with a light doping concentration. The semiconductor region 102 is used as a drift region, and its concentration distribution is uniform. At the same time, the sides of the semiconductor region 102 are filled with field oxygen to form parallel The sidewall oxide layer 120 is connected to the semiconductor regions 101 and 103 and extends vertically into the substrate region 100 . Photolithographically deposit polysilicon on both sides of the sidewall oxide layer 120 to form a first slope-shaped polysilicon field plate 110 and a second slope-shaped polysilicon field plate 112. The first slope-shaped polysilicon field plate 110 is electrically connected to the gate 131, and the second The sloped polysilicon field plate 112 is electrically connected to the drain 132 , and the first sloped polysilicon field plate 110 and the second sloped polysilicon field plate 112 also extend beyond the upper surface of the substrate region 100 into the substrate region 100 .

2) LDMOS with sidewall multi-step field plates, as shown in FIG. 8 . It includes a substrate region 100 of the first conductivity type, a semiconductor region 101 of the first conductivity type with a high doping concentration formed by twice high doping, a semiconductor region 103 of the second conductivity type of a high doping concentration, as source and drain respectively. The two are connected by a semiconductor region 102 of the second conductivity type with a light doping concentration. The semiconductor region 102 is used as a drift region, and its concentration distribution is uniform. At the same time, the sides of the semiconductor region 102 are filled with field oxygen to form parallel The sidewall oxide layer 120 is connected to the semiconductor regions 101 and 103 and extends vertically into the semiconductor region 100 . Photolithographically deposit polysilicon on both sides of the sidewall oxide layer 120 to form a back-to-back multi-stepped first stepped polysilicon field plate 110, a second stepped polysilicon field plate 112, the first stepped polysilicon field plate 110 and the gate 131 is electrically connected, the second ladder-shaped polysilicon field plate 112 is electrically connected to the drain 132, and the first ladder-shaped polysilicon field plate 110 and the second ladder-shaped polysilicon field plate 112 also extend beyond the upper surface of the substrate region 100 into the substrate In the bottom area 100.

3) LDMOS with sidewall segmented field plates, as shown in FIG. 9 . It includes a substrate region 100 of the first conductivity type, a semiconductor region 101 of the first conductivity type with a high doping concentration formed by twice high doping, a semiconductor region 103 of the second conductivity type of a high doping concentration, as source and drain respectively. The two are connected by a semiconductor region 102 of the second conductivity type with a light doping concentration. The semiconductor region 102 is used as a drift region, and its concentration distribution is uniform. At the same time, the sides of the semiconductor region 102 are filled with field oxygen to form parallel The sidewall oxide layer 120 is connected to the semiconductor region 101 of the first conductivity type and the semiconductor region 103 of the second conductivity type, and extends vertically into the semiconductor region 100 . The first rectangular polysilicon field plate 110, the second rectangular polysilicon field plate 112, the third rectangular polysilicon field plate 114, and the fourth rectangular polysilicon field plate 116 are photolithographically deposited on the sidewall oxide layer 120 from the source end to the drain end. , the fifth rectangular polysilicon field plate 118, the sixth rectangular polysilicon field plate 117, the seventh rectangular polysilicon field plate 115, the eighth rectangular polysilicon field plate 113, and the ninth rectangular polysilicon field plate 111, and the distribution of segmented field plates is symmetrical, The distance between the field plates gradually decreases from the source end to the middle of the sidewall oxide layer 120 , and then gradually increases toward the drain end. The first rectangular polysilicon field plate 110 is electrically connected to the gate 131, the ninth rectangular polysilicon field plate 111 is electrically connected to the drain 132, and each section of the field plate must extend vertically beyond the upper surface of the substrate region 100 and enter the substrate region 100. Inside.

4) LDMOS with another type of sidewall segmented field plate, as shown in FIG. 10 . It includes a substrate region 100 of the first conductivity type, a semiconductor region 101 of the first conductivity type with a high doping concentration formed by twice high doping, a semiconductor region 103 of the second conductivity type of a high doping concentration, as source and drain respectively. The two are connected by a semiconductor region 102 of the second conductivity type with a light doping concentration. The semiconductor region 102 is used as a drift region, and its concentration distribution is uniform. At the same time, the sides of the semiconductor region 102 are filled with field oxygen to form parallel The sidewall oxide layer 120 is connected to the semiconductor regions 101 and 103 and extends vertically into the semiconductor region 100 . A first rectangular polysilicon field plate 110 , a second rectangular polysilicon field plate 112 , a third rectangular polysilicon field plate 114 , and a fourth rectangular polysilicon field plate 116 are photolithographically deposited in the sidewall oxide layer 120 from the source end to the drain end. , the fifth rectangular polysilicon field plate 115, the sixth rectangular polysilicon field plate 113, and the seventh rectangular polysilicon field plate 111, the segmented field plates are distributed symmetrically, the distance between the field plates remains constant, and the width of the field plate itself gradually shrinks from the source end to the middle of the sidewall oxide layer 120, and then gradually increases toward the drain end. The first rectangular polysilicon field plate 110 is electrically connected to the gate 131, the seventh rectangular polysilicon field plate 111 is electrically connected to the drain 132, and each segment of the field plate must extend vertically beyond the upper surface of the substrate region 100 and enter the substrate region 100 Inside.

It should be noted that the lateral power transistor structure proposed by the present invention can not only be applied to the above LDMOS devices, but also can be used for lateral diffusion PN junctions, lateral thyristors and other lateral power devices not listed, and the type of side wall field plate can be determined according to In fact, it needs to be adjusted, or used in conjunction with a flat field plate to achieve a better electric field modulation effect.

Claims (8)

1. A junction termination structure of a lateral power device, characterized in that it comprises a substrate region (100), a semiconductor region (101) with a first type of conductivity, a second type of conductivity with a high doping concentration type semiconductor region (103), separated by a second conductivity type semiconductor region (102) with a low doping concentration and a sidewall oxide layer (120), the second conductivity type semiconductor region The region (102) constitutes the drift region of the power device, and the sidewall oxide layer (120) is photolithographically deposited on both ends of the first slope-shaped polysilicon field plate (110) and the second slope-shaped polysilicon field plate (112). The slope-shaped polysilicon field plate is electrically connected to the grid (131) and the drain (132) respectively. 2. The junction termination structure of a lateral power device according to claim 1, characterized in that: the semiconductor region of the second conductivity type (102) as a drift region has a low doping concentration of the semiconductor region of the second conductivity type , its concentration is uniform. 3. The junction termination structure of a lateral power device according to claim 1, characterized in that: the sidewall oxide layer (120) is located on the side of the semiconductor region (102) of the second conductivity type as the drift region, and its vertical depth Beyond the thickness of the drift region, into the interior of the substrate region (100). 4. The junction termination structure of a lateral power device according to claim 1 or 2, characterized in that: the vertical depths of the first slope-shaped polysilicon field plate (110) and the second slope-shaped polysilicon field plate (112) need to exceed as The thickness of the semiconductor region (102) of the second conductivity type in the drift region enters the interior of the substrate region (100). 5. The lateral power device according to claim 4, characterized in that: the substrate region (100) is a semiconductor material, or a silicon dioxide oxide layer (SOI). 6. The junction termination structure of a lateral power device according to claim 4, characterized in that: the first slope-shaped polysilicon field plate (110) and the second slope-shaped polysilicon field plate (112) can also be multi-step or multi-segment Separate segmented field plates, the segmented field plates are floating or biased to different voltages by a voltage divider network. 7. The junction termination structure of a lateral power device according to claim 1, characterized in that: the sidewall oxide layer (120) is silicon dioxide. 8. The junction terminal structure of a lateral power device according to claim 1, characterized in that: the specific form of the lateral power device is a lateral diffusion field effect transistor LDMOS, a lateral PN diode, and a lateral insulated gate bipolar transistor LIGBT , or a lateral thyristor.

Images