CN102170291B - Multi-channel analog-to-digital conversion circuit and its analog-to-digital conversion method - Google Patents

Abstract

The invention relates to a multi-channel analog-digital conversion circuit and an analog-digital conversion method thereof, wherein the multi-channel analog-digital conversion circuit comprises: a plurality of sampling circuits for sampling and registering a plurality of groups of analog input signals; a single output circuit coupled to the sampling circuits and shared by the sampling circuits; and a single analog-to-digital conversion core coupled to the output circuit and shared by the sampling circuits.

Description

Multi-channel analog-to-digital conversion circuit and its analog-to-digital conversion method

technical field

The present invention relates to a multi-channel analog-to-digital conversion circuit (Analog Digital Conversion Circuit) and its analog-to-digital conversion method, and in particular to a multi-channel analog-to-digital conversion circuit sharing an analog-digital conversion core (AnalogDigital Conversion Core) and its analog-to-digital conversion method.

Background technique

Analog-to-digital conversion circuits are widely used. Analog-to-digital conversion circuits can be applied to multi-channel/multiple-input/multiple-output situations. However, in terms of current analog-to-digital conversion circuits, if there are N (N is a positive integer) channels, then N analog-to-digital conversion circuits are required. In this way, the area of the circuit will be increased, and the cost of the circuit will be increased.

Therefore, there is a need for a new analog-to-digital conversion circuit architecture, even if it is applied to multi-channel/multiple-input/multiple-output situations, its circuit area will not be greatly increased, and the circuit cost will not be greatly increased.

Contents of the invention

The object of the present invention is to provide an analog-to-digital conversion circuit and its method. When applied to multi-channel/multiple-input/multiple-output, the analog-to-digital conversion core and output circuit at the back end can be shared by multiple front-end sampling circuits to Reduce circuit area and circuit cost.

According to one aspect of the present invention, a multi-channel analog-to-digital conversion circuit is proposed, including: a plurality of sampling circuits, sampling and registering multiple sets of analog input signals; a single output circuit, coupled to these sampling circuits, shared by these sampling circuits; and A single analog-to-digital conversion core, coupled to the output circuit, is shared by the sampling circuits.

According to another aspect of the present invention, a multi-channel analog-to-digital conversion circuit is provided, which is characterized in that it includes: a plurality of sampling circuits, sampling and storing multiple groups of analog input signals; a single output circuit, coupled to these sampling circuits, by These sampling circuits are shared; and a single analog-to-digital conversion core, coupled to the output circuit, is shared by these sampling circuits; wherein, these sampling circuits sequentially send the sampled groups of analog input signals to the output circuit, the The output circuit sequentially sends these groups of analog input signals to the analog-to-digital conversion core, and the analog-to-digital conversion core sequentially converts these groups of analog input signals into a plurality of digital output signals.

According to another aspect of the present invention, an analog-to-digital conversion method is proposed, which is applied to a multi-channel analog-to-digital conversion circuit. The analog-to-digital conversion method includes: simultaneously sampling and storing multiple groups of analog input signals; Analog-to-digital conversion of input signals to sequentially output a plurality of digital output signals; avoiding affecting individual sets of analog input signals that have not been converted; and enabling a common voltage to be coupled to individual sets of analog input signals that have been converted.

The beneficial technical effects of the present invention are: when the present invention is applied to multi-channels, since the back-end output circuit and the analog-to-digital conversion core can be shared, the circuit area is small, the circuit cost is saved, and the product is more competitive. Moreover, the analog-to-digital conversion circuit can have high resolution with low side effects.

Description of drawings

In order to make the above content of the present invention more obvious and understandable, preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1 shows a schematic diagram of an analog-to-digital conversion circuit according to a first embodiment of the present invention.

FIG. 2 shows operation waveforms of the analog-to-digital conversion circuit according to the first embodiment of the present invention.

FIG. 3 shows a structural diagram of an analog-to-digital conversion circuit according to a second embodiment of the present invention.

FIG. 4 shows operation waveforms of the analog-to-digital conversion circuit according to the second embodiment of the present invention.

FIG. 5 shows a structural diagram of an analog-to-digital conversion circuit according to a third embodiment of the present invention.

FIG. 6 shows operation waveforms of an analog-to-digital conversion circuit according to a third embodiment of the present invention.

Detailed ways

In the architecture of the analog-to-digital conversion circuit according to the embodiment of the present invention, when applied to multi-channel/multiple-input/multiple-output, the back-end analog-to-digital conversion core and output circuit can be shared by multiple front-end sampling circuits to reduce circuit area and circuit cost.

Several embodiments are listed below to illustrate the architecture and operating principles of the analog-to-digital conversion circuits of several embodiments of the present invention applied to 2 channels, 3 channels and 4 channels.

First embodiment: 2 channels

FIG. 1 shows a schematic diagram of an analog-to-digital conversion circuit according to a first embodiment of the present invention. FIG. 2 shows operation waveforms of the analog-to-digital conversion circuit according to the first embodiment of the present invention. The analog-to-digital conversion circuit of the first embodiment of the present invention can be applied to 2 channels, that is, the analog-to-digital conversion circuit of the first embodiment of the present invention can receive 2 sets of analog input signals and convert them into 2 sets of digital output signals . In this manual, 1 channel means receiving 1 set of analog input signals and converting them into 1 digital output signal.

As shown in FIG. 1 , the analog-to-digital conversion circuit 100 according to the first embodiment of the present invention includes: a sample/hold circuit 110 and an analog-to-digital conversion core 50 . The analog-to-digital conversion core 50 converts an analog signal into a digital signal. The sample/hold circuit 110 includes a plurality of sampling circuits 120A and 120B, and an output circuit 130 . The number of sampling circuits basically corresponds (same) to the number of channels.

The sampling circuit 120A includes: buffer circuits (BF) 121A˜121D, a plurality of switches F1 , a plurality of switches F2 , a plurality of switches F3 and a plurality of capacitors C1 . The buffer circuits 121A and 121C buffer the analog input signals Vinp1 and Vinn1 respectively. Both the buffer circuits 121B and 121D buffer the common voltage Vcom.

The first of these switches F1 is coupled between the buffer circuit 121A and the capacitor C1 (above); that is, the on/off of the first of these switches F1 determines whether the analog input signal Vinp1 buffered in the buffer circuit 121A can No Coupled to Capacitor C1 (Above). The second of these switches F1 is coupled between the buffer circuit 121C and the capacitor C1 (below); that is, the on/off of the second of these switches F1 determines whether the analog input signal Vinn1 buffered in the buffer circuit 121C can No Coupled to capacitor C1 (below). The third of these switches F1 is coupled between the capacitor C1 (above) and the common voltage Vcom; that is, the on/off of the third of these switches F1 determines whether the common voltage Vcom can be coupled to the capacitor C1 (above) . The fourth of these switches F1 is coupled between the capacitor C1 (below) and the common voltage Vcom; that is, the turn-on/off of the fourth of these switches F1 determines whether the common voltage Vcom can be coupled to the capacitor C1 (below) .

The first of the switches F2 is coupled between the two capacitors C1; that is, the on/off of the first of the switches F2 determines whether the charge sharing between the two capacitors C1 will occur. The second of these switches F2 is coupled between the capacitor C1 (above) and the output circuit 130; that is, the on/off of the second of these switches F2 determines whether the charge stored in the capacitor C1 (above) is sent to the output circuit 130. The third of these switches F2 is coupled between the capacitor C1 (below) and the output circuit 130; that is, the on/off of the third of these switches F2 determines whether the charge stored in the capacitor C1 (below) is sent to the output circuit 130.

The first of these switches F3 is coupled between the snubber circuit 121B and the capacitor C1 (above); that is, the on/off of the first of these switches F3 determines whether the common voltage Vcom buffered in the snubber circuit 121B can be Couple to Capacitor C1 (Above). The second of these switches F3 is coupled between the snubber circuit 121D and the capacitor C1 (below); that is, the on/off of the second of these switches F3 determines whether the common voltage Vcom buffered in the snubber circuit 121D can be Couple to capacitor C1 (below).

Sampling circuit 120B: buffer circuits 121E˜121H, multiple switches F1 , multiple switches F4 , multiple switches F5 and multiple capacitors C2 . Since the coupling relationship of the internal components of the sampling circuit 120B is similar to the coupling relationship of the internal components of the sampling circuit 120A, the details thereof are omitted here.

The output circuit 130 includes: an operational amplifier (OP) 131 , a plurality of switches FZ and a plurality of capacitors CF. A first one of the plurality of switches FZ is coupled between the common voltage Vcom and a first input terminal of the operational amplifier; that is, the on/off of the first one of the switches FZ determines whether the common voltage Vcom is coupled to the operational amplifier. the first input of the amplifier. The second of the plurality of switches FZ is coupled between the common voltage Vcom and a second input terminal of the operational amplifier; that is, the on/off of the second of the switches FZ determines whether the common voltage Vcom is coupled to the operational amplifier. the second input of the amplifier. The third of the plurality of switches FZ is coupled between the two output terminals of the operational amplifier; that is, the on/off of the third of these switches FZ determines whether the voltages (Voutp and Voutn) of the two output terminals of the operational amplifier are equal .

Please refer to FIG. 1 and FIG. 2 together to illustrate the operation principle of the first embodiment of the present invention. The operating clock 2*CLK is input to all buffer circuits 121A˜ 121H in the analog-to-digital conversion circuit 100 , the operational amplifier 131 of the output circuit 130 and the analog-to-digital conversion core 50 . The control signals SF1 , SF2 , SF3 , SF4 , SF5 and SFZ in FIG. 2 control the switches F1 , F2 , F3 , F4 , F5 and FZ respectively. In this embodiment, when the control signal is logic high, the switch is turned on; otherwise, when the control signal is logic low, the switch is turned off. The control signal can be generated by a controller (not shown) according to the operating clock 2*CLK.

During the period of sampling (marked as S in FIG. 2 ), the switch F1 is turned on, so that the two groups of analog input signals buffered in the buffer circuits 121A, 121C, 121E and 121G are respectively charged to the capacitor C1 and the capacitor C2; At this time, the switch FZ is also turned on, so that the voltages of the two output terminals (Voutp and Voutn) of the operational amplifier are equal to each other.

During the first data holding period (marked as H1 in FIG. 2 ), the switches F1 and FZ are both non-conducting, but the switch F2 is conducting, so that the data stored in the capacitor C1 (that is, the first group of analog input signals Vinp1 and Vinn1) are output to the two output terminals of the operational amplifier 131 through the capacitor CF, so as to be sent to the analog-to-digital conversion core 50 at the rear end, and at this time, the switch at the rear-end of the analog-to-digital conversion core 50 will switch to send the digital output of the first channel Signal DOUT1. In addition, at this time, the switch F5 must be turned on, so that the data stored in the capacitor C2 (that is, the second set of analog input signals Vinp2 and Vinn2 ) will not be affected. That is to say, after the first data holding period, the analog-to-digital conversion circuit converts the first set of analog input signals Vinp1 and Vinn1 into a digital output signal DOUT1 .

During the second data holding period (marked as H2 in FIG. 2 ), the switches F1 and FZ are both non-conducting, but the switch F4 is conducting, so that the data stored in the capacitor C2 (that is, the second group of analog input signal Vinp2 and Vinn2) are output to the two output terminals of the operational amplifier 131 through the capacitor CF to be sent to the analog-to-digital conversion core 50 at the rear end; and at this time, the switch at the rear-end of the analog-to-digital conversion core 50 will switch to send the digital output of the second channel Signal DOUT2. In addition, at this time, the switch F3 must be turned on, so that the common voltage Vcom can be coupled into the capacitor C1. That is to say, after the second data holding period, the analog-to-digital conversion circuit converts the second set of analog input signals Vinp2 and Vinn2 into digital output signals DOUT2.

Repeat the above operations (S˜H2) to sequentially send the analog input signals to the analog-to-digital conversion core 50, convert them into digital output signals, and output them sequentially.

Second embodiment: 3 channels

FIG. 3 shows a structural diagram of an analog-to-digital conversion circuit according to a second embodiment of the present invention. FIG. 4 shows operation waveforms of the analog-to-digital conversion circuit according to the second embodiment of the present invention. The analog-to-digital conversion circuit of the second embodiment of the present invention can be applied to 3 channels, that is, the analog-to-digital conversion circuit of the second embodiment of the present invention can receive 3 sets of analog input signals and convert them into 3 sets of digital output signals .

As shown in FIG. 3 , the analog-to-digital conversion circuit 300 according to the second embodiment of the present invention includes: a sample/hold circuit 310 and an analog-to-digital conversion core 50 . The sample/hold circuit 310 includes a plurality of sampling circuits 320A, 320B and 320C, and an output circuit 130 .

The sampling circuit 320A includes: buffer circuits 321A˜ 321D, a plurality of switches F1 , a plurality of switches F2 , a plurality of switches F3 and a plurality of capacitors C1 . The sampling circuit 320B includes: buffer circuits 321E˜ 321H, a plurality of switches F1 , a plurality of switches F4 , a plurality of switches F5 and a plurality of capacitors C2 . The sampling circuit 320C includes: buffer circuits 321I˜321L, a plurality of switches F1 , a plurality of switches F6 , a plurality of switches F7 and a plurality of capacitors C3 . In the second embodiment, the structures of the sampling circuits 320A- 320C are the same or similar to the sampling circuits 120A and 120B in the first embodiment, so the details thereof are omitted here.

Please refer to FIG. 3 and FIG. 4 together to illustrate the operation principle of the second embodiment of the present invention. The operating clock 3*CLK is input to all buffer circuits 321A˜ 321L in the analog-to-digital conversion circuit 300 , the operational amplifier 131 of the output circuit 130 and the analog-to-digital conversion core 50 . The control signals S F1, SF2, SF3, SF4, SF5, SF6, SF7 and SFZ in Fig. 4 respectively control the switches F1, F2, F3, F4, F5, F6, F7 and FZ.

During the sample period (marked as S in FIG. 4 ), the switch F1 is turned on, so that the three groups of analog input signals buffered in the buffer circuits 321A, 321C, 321E, 321G, 321I and 321K are respectively charged to the capacitor C1 , the capacitor C2 and the capacitor C3; at this time, the switch FZ is also turned on, so that the voltages (Voutp and Voutn) of the two output terminals of the operational amplifier are equal to each other.

During the first data holding period (marked as H1 in FIG. 4 ), the switches F1 and FZ are both non-conducting, but the switch F2 is conducting, so that the data stored in the capacitor C1 (that is, the first group of analog input signals Vinp1 and Vinn1) are output to the two output terminals of the operational amplifier 131 through the capacitor CF, so as to be sent to the analog-to-digital conversion core 50 at the rear end; and at this time, the switch at the rear end of the analog-to-digital conversion core 50 will switch to send the digital output of the first channel Signal DOUT1. In addition, at this time, the switches F5 and F7 must be turned on, so that the data stored in the capacitors C2 and C3 (that is, the second group of analog input signals Vinp2 and Vinn2, and the third group of analog input signals Vinp3 and Vinn3) are not will be affected. That is to say, after the first data holding period, the analog-to-digital conversion circuit converts the first set of analog input signals Vinp1 and Vinn1 into a digital output signal DOUT1 .

During the second data holding period (marked as H2 in FIG. 4 ), the switches F1 and FZ are both non-conducting, but the switch F4 is conducting, so that the data stored in the capacitor C2 (that is, the second group of analog input signal Vinp2 and Vinn2) are output to the two output terminals of the operational amplifier 131 through the capacitor CF to be sent to the analog-to-digital conversion core 50 at the rear end; and at this time, the switch at the rear-end of the analog-to-digital conversion core 50 will switch to send the digital output of the second channel Signal DOUT2. In addition, at this time, the switch F3 must be turned on so that the common voltage Vcom can be coupled into the capacitor C1; and the switch F7 must be turned on so that the data stored in the capacitor C3 (that is, the third group of analog input signal Vinp3 and Vinn3) are not affected. That is to say, after the second data holding period, the analog-to-digital conversion circuit converts the second set of analog input signals Vinp2 and Vinn2 into digital output signals DOUT2.

During the third data retention period (marked as H3 in FIG. 4 ), the switches F1 and FZ are both non-conductive, but the switch F6 is conductive, so that the data stored in the capacitor C3 (that is, the third group of analog input signal Vinp3 and Vinn3) are output to the two output terminals of the operational amplifier 131 through the capacitor CF, so as to be sent to the analog-to-digital conversion core 50 at the back end; and at this time, the switch at the rear end of the analog-to-digital conversion core 50 will switch to send the digital output of the third channel Signal DOUT3. In addition, at this time, the switches F3 and F5 must be turned on, so that the common voltage Vcom can be coupled into the capacitors C1 and C2. That is to say, after the third data holding period, the analog-to-digital conversion circuit converts the third group of analog input signals Vinp3 and Vinn3 into a digital output signal DOUT3.

Repeat the above operations (S˜H3) to sequentially send the analog input signals to the analog-to-digital conversion core 50, convert them into digital output signals, and output them sequentially.

Third embodiment: 4 channels

FIG. 5 shows a structural diagram of an analog-to-digital conversion circuit according to a third embodiment of the present invention. FIG. 6 shows operation waveforms of an analog-to-digital conversion circuit according to a third embodiment of the present invention. The analog-to-digital conversion circuit of the third embodiment of the present invention can be applied to 4 channels, that is, the analog-to-digital conversion circuit of the second embodiment of the present invention can receive 4 sets of analog input signals and convert them into 4 sets of digital output signals .

As shown in FIG. 5 , the analog-to-digital conversion circuit 500 according to the third embodiment of the present invention includes: a sample/hold circuit 510 and an analog-to-digital conversion core 50 . The sample/hold circuit 510 includes a plurality of sampling circuits 520A, 520B, 520C and 520D, and an output circuit 130 .

The sampling circuit 520A includes: buffer circuits 521A˜521D, a plurality of switches F1 , a plurality of switches F2 , a plurality of switches F3 and a plurality of capacitors C1 . The sampling circuit 520B includes: buffer circuits 521E˜521H, a plurality of switches F1 , a plurality of switches F4 , a plurality of switches F5 and a plurality of capacitors C2 . The sampling circuit 520C includes: buffer circuits 521I˜521L, a plurality of switches F1 , a plurality of switches F6 , a plurality of switches F7 and a plurality of capacitors C3 . The sampling circuit 520D includes: buffer circuits 521M˜521P, a plurality of switches F1 , a plurality of switches F8 , a plurality of switches F9 and a plurality of capacitors C4 . In the third embodiment, the structures of the sampling circuits 520A-520D are the same or similar to the sampling circuits 120A-120B in the first embodiment, so the details thereof are omitted here.

Please refer to FIG. 5 and FIG. 6 together to illustrate the operation principle of the third embodiment of the present invention. The operating clock 4*CLK is input to all buffer circuits 521A˜ 521P in the analog-to-digital conversion circuit 500 , the operational amplifier 131 of the output circuit 130 and the analog-to-digital conversion core 50 . The control signals SF1, SF2, SF3, SF4, SF5, SF6, SF7, SF8, SF9 and SFZ in FIG. 6 respectively control the switches F1, F2, F3, F4, F5, F6, F7, F8, F9 and FZ.

During the sampling period (marked as S in FIG. 6 ), the switch F1 is turned on, so that the four groups of analog input signals buffered in the buffer circuits 521A, 521C, 521E, 521G, 521I, 521K, 521M and 521O are respectively charged to the capacitors C1 , capacitor C2 , capacitor C3 and capacitor C4 ; at this time, the switch FZ is also turned on, so that the voltages (Voutp and Voutn) of the two output terminals of the operational amplifier are equal to each other.

During the first data retention period (marked as H1 in FIG. 6 ), the switches F1 and FZ are both non-conducting, but the switch F2 is conducting, so that the data stored in the capacitor C1 (that is, the first group of analog input signals Vin p1 and Vinn1) are output to the two output terminals of the operational amplifier 131 through the capacitor CF, so as to be sent to the analog-to-digital conversion core 50 at the back end; and at this time, the switch at the rear end of the analog-to-digital conversion core 50 will switch to send out the digital value of the first channel Output signal DOUT1. In addition, at this time, the switches F5, F7 and F9 must be turned on, so that the data stored in the capacitor C2, capacitor C3 and capacitor C4 (that is, the second group of analog input signals Vinp2 and Vinn2, the third group of analog input signal Vinp3 and Vinn3, and the fourth set of analog input signals Vinp4 and Vinn4) will not be affected. That is to say, after the first data holding period, the analog-to-digital conversion circuit converts the first set of analog input signals Vinp1 and Vinn1 into a digital output signal DOUT1 .

During the second data holding period (marked as H2 in FIG. 6 ), the switches F1 and FZ are both non-conducting, but the switch F4 is conducting, so that the data stored in the capacitor C2 (that is, the second group of analog input signal Vinp2 and Vinn2) are output to the two output terminals of the operational amplifier 131 through the capacitor CF to be sent to the analog-to-digital conversion core 50 at the rear end; and at this time, the switch at the rear-end of the analog-to-digital conversion core 50 will switch to send the digital output of the second channel Signal DOUT2. In addition, at this time, the switch F3 must be turned on so that the common voltage Vcom can be coupled into the capacitor C1; and the switches F7 and F9 must be turned on so that the data stored in the capacitor C3 and the capacitor C4 (that is, the third The group of analog input signals Vinp3 and Vinn3, and the fourth group of analog input signals Vinp4 and Vinn4) will not be affected. That is to say, after the second data holding period, the analog-to-digital conversion circuit converts the second set of analog input signals Vinp2 and Vinn2 into digital output signals DOUT2.

During the third data holding period (marked as H3 in FIG. 6 ), the switches F1 and FZ are both non-conducting, but the switch F6 is conducting, so that the data stored in the capacitor C3 (that is, the third group of analog input signal Vinp3 and Vinn3) are output to the two output terminals of the operational amplifier 131 through the capacitor CF, so as to be sent to the analog-to-digital conversion core 50 at the back end; and at this time, the switch at the rear end of the analog-to-digital conversion core 50 will switch to send the digital output of the third channel Signal DOUT3. In addition, at this time, the switches F3 and F5 must be turned on so that the common voltage Vcom can be coupled to the capacitors C1 and C2; and the switch F9 must be turned on so that the data stored in the capacitor C4 (that is, the fourth The set of analog input signals Vinp4 and Vinn4) will not be affected. That is to say, after the third data holding period, the analog-to-digital conversion circuit converts the third group of analog input signals Vinp3 and Vinn3 into a digital output signal DOUT3.

In the fourth data holding period (marked as H4 in FIG. 6 ), both switches F1 and FZ are non-conducting, but switch F8 is conducting, so that the data stored in the capacitor C4 (that is, the fourth group of analog input signal Vinp4 and Vinn4) are output to the two output terminals of the operational amplifier 131 through the capacitor CF, so as to be sent to the analog-to-digital conversion core 50 at the back end; and at this time, the switch at the rear end of the analog-to-digital conversion core 50 will switch to send the digital output of the fourth channel Signal DOUT4. In addition, at this time, the switches F3 , F5 and F7 must be turned on so that the common voltage Vcom can be coupled to the capacitor C1 , capacitor C2 and capacitor C3 . That is to say, after the fourth data holding period, the analog-to-digital conversion circuit converts the fourth set of analog input signals Vinp4 and Vinn4 into digital output signals DOUT4 .

Repeat the above operations (S˜H4) to sequentially send the analog input signals to the analog-to-digital conversion core 50, convert them into digital output signals, and output them sequentially.

Those skilled in the art will know from the above description that the present invention can also be applied to other possible embodiments of more channels, which are all within the scope of the present invention. For example, when the operating clock speed is faster, the analog-to-digital conversion circuit according to the above or other embodiments of the present invention can be applied to more channels.

Therefore, in the embodiment of the present invention, when applied to multiple channels, since the back-end output circuit and the analog-to-digital conversion core can be shared, the circuit area of the embodiment of the present invention is small, which saves the circuit cost and makes the product more competitive force. For example, when applied to N channels, the circuit area of the analog-to-digital conversion circuit according to the above or other embodiments of the present invention may be only 1/N of the circuit area of a conventional analog-to-digital conversion circuit.

Moreover, as long as the operating clock N*CLK is fast enough, the analog-to-digital conversion circuit according to the above or other embodiments of the present invention can have high resolution and low side effects.

To sum up, although the present invention has been disclosed by the above embodiments, they are not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various equivalent changes or substitutions without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims of the application.

Claims (6)

1. a multichannel analog digital conversion circuit, is characterized in that, comprising:

A plurality of sample circuits, sample and deposit many group analog input signals;

Single output circuit, is coupled to these sample circuits, by these sample circuits, is shared; And

Single simulation digital translation core, is coupled to this output circuit, by these sample circuits, is shared;

Wherein, these sample circuits at least comprise one first sample circuit and one second sample circuit,

This first sample circuit comprises one first buffer input signal circuit group, one first common voltage buffer circuit group, one first switches set and one first capacitance group, one first group of analog input signal of this first buffer input signal circuit group buffering, this the first common voltage buffer circuit group cushions a common voltage, and this first sample circuit samples and deposit this first group of analog input signal; And

This second sample circuit comprises one second buffer input signal circuit group, one second common voltage buffer circuit group, a second switch group and one second capacitance group, one second group of analog input signal of this second buffer input signal circuit group buffering, this the second common voltage buffer circuit group cushions this common voltage, and this second sample circuit samples and deposit this second group of analog input signal; And

This output circuit comprises an operational amplifier, an output switch group and an output capacitance group;

In a Proper Sampling Period,

According to a conducting of this first switches set and this second switch group/close situation, by be buffered in this first with this second buffer input signal circuit group in this first group with this second group of analog input signal be stored to respectively this first with this second capacitance group; And

According to a conducting of this output switch group of this output circuit/close situation, two output voltages of two outputs of this operational amplifier are equated;

In the retention period of first data,

By this output capacitance group, export this first group of analog input signal being stored in this first capacitance group this two output of this operational amplifier to, to be sent to this analog digital conversion core; And

Control this conducting of this second switch group/close situation, this second group of analog input signal that makes to be stored in this second capacitance group is unaffected; And

In the retention period of second data,

By this output capacitance group, export this second group of analog input signal being stored in this second capacitance group this two output of this operational amplifier to, to be sent to this analog digital conversion core; And

Control this conducting of this first switches set/close situation, make this common voltage coupling to this first capacitance group.

2. analog-to-digital conversion circuit according to claim 1, it is characterized in that, these sample circuits also comprise one the 3rd sample circuit, the 3rd sample circuit comprises one the 3rd buffer input signal circuit group, one the 3rd common voltage buffer circuit group, one the 3rd switches set and one the 3rd capacitance group, one the 3rd group of analog input signal of the 3rd buffer input signal circuit group buffering, the 3rd common voltage buffer circuit group cushions this common voltage, and the 3rd sample circuit samples and deposit the 3rd group of analog input signal.

3. analog-to-digital conversion circuit according to claim 2, is characterized in that:

In this Proper Sampling Period,

Also comprise and a conducting according to the 3rd switches set/close situation the 3rd group of analog input signal being buffered in the 3rd buffer input signal circuit group is stored to the 3rd capacitance group; And

In the retention period of these first data,

Also comprise and control this conducting of the 3rd switches set/close situation, the 3rd group of analog input signal that makes to be stored in the 3rd capacitance group is unaffected; And

In the retention period of these second data,

Also comprise and control this conducting of the 3rd switches set/close situation, the 3rd group of analog input signal that makes to be stored in the 3rd capacitance group is unaffected; And

In the retention period of the 3rd data,

By this output capacitance group, export the 3rd group of analog input signal being stored in the 3rd capacitance group this two output of this operational amplifier to, to be sent to this analog digital conversion core; And

Control this first with this conducting of this second switch group/close situation, make this common voltage coupling to this first with this second capacitance group.

4. analog-to-digital conversion circuit according to claim 2, it is characterized in that, these sample circuits also comprise one the 4th sample circuit, the 4th sample circuit comprises one the 4th buffer input signal circuit group, one the 4th common voltage buffer circuit group, one the 4th switches set and one the 4th capacitance group, one the 4th group of analog input signal of the 4th buffer input signal circuit group buffering, the 4th common voltage buffer circuit group cushions this common voltage, and the 4th sample circuit samples and deposit the 4th group of analog input signal.

5. analog-to-digital conversion circuit according to claim 4, is characterized in that:

In this Proper Sampling Period,

Also comprise and a conducting according to the 4th switches set/close situation the 4th group of analog input signal being buffered in the 4th buffer input signal circuit group is stored to the 4th capacitance group; And

In the retention period of these first data,

Also comprise and control this conducting of the 4th switches set/close situation, the 4th group of analog input signal that makes to be stored in the 4th capacitance group is unaffected; And

In the retention period of these second data,

Also comprise and control this conducting of the 4th switches set/close situation, the 4th group of analog input signal that makes to be stored in the 4th capacitance group is unaffected; And

In the retention period of the 3rd data,

Also comprise and control this conducting of the 4th switches set/close situation, the 4th group of analog input signal that makes to be stored in the 4th capacitance group is unaffected; And

In the retention period of the 4th data,

By this output capacitance group, export the 4th group of analog input signal being stored in the 4th capacitance group this two output of this operational amplifier to, to be sent to this analog digital conversion core; And

Control this first, this second with this conducting of the 3rd switches set/close situation, make this common voltage coupling to this first, this second with the 3rd capacitance group.

6. an analog-digital conversion method, is applied to a multichannel analog digital conversion circuit, it is characterized in that, this analog-digital conversion method comprises:

With a plurality of sample circuits, sample simultaneously and deposit many group analog input signals;

Sequentially these sampled group analog input signals are carried out to analog digital conversion, sequentially to export a plurality of digital output signals;

Indivedual groups of analog input signals avoiding impact to be not yet converted; And

Indivedual groups of analog input signals that one common voltage are coupled to be converted;

Wherein, these sample circuits at least comprise one first sample circuit and one second sample circuit,

This first sample circuit comprises one first buffer input signal circuit group, one first common voltage buffer circuit group, one first switches set and one first capacitance group, one first group of analog input signal of this first buffer input signal circuit group buffering, this the first common voltage buffer circuit group cushions a common voltage, and this first sample circuit samples and deposit first group of analog input signal; And

This second sample circuit comprises one second buffer input signal circuit group, one second common voltage buffer circuit group, a second switch group and one second capacitance group, one second group of analog input signal of this second buffer input signal circuit group buffering, this the second common voltage buffer circuit group cushions this common voltage, and this second sample circuit samples and deposit this second group of analog input signal; And

Output circuit comprises an operational amplifier, an output switch group and an output capacitance group;

In a Proper Sampling Period,

According to a conducting of this first switches set and this second switch group/close situation, by be buffered in this first with this second buffer input signal circuit group in this first group with this second group of analog input signal be stored to respectively this first with this second capacitance group; And

According to a conducting of this output switch group of this output circuit/close situation, two output voltages of two outputs of this operational amplifier are equated;

In the retention period of first data,

By this output capacitance group, export this first group of analog input signal being stored in this first capacitance group this two output of this operational amplifier to, to be sent to analog digital conversion core; And

Control this conducting of this second switch group/close situation, this second group of analog input signal that makes to be stored in this second capacitance group is unaffected; And

In the retention period of second data,

By this output capacitance group, export this second group of analog input signal being stored in this second capacitance group this two output of this operational amplifier to, to be sent to this analog digital conversion core; And

Control this conducting of this first switches set/close situation, make this common voltage coupling to this first capacitance group.