Summary of the invention
The objective of the invention is to have proposed a kind of adaptive power regulating circuit and method in order to solve the too high problem of switching power supply system power dissipation under the existing PWM mode.
Detailed technology scheme of the present invention: a kind of adaptive power regulating circuit, comprise and drive and drive logical block, time-to-digit converter and control logic unit, wherein, the PWM input of the input of time-to-digit converter and driving and driving logical block is used to import outside PWM ripple, the output of time-to-digit converter is connected with the input of control logic unit, the output of control logic unit is connected with the power tube control code input of driving and driving logical block, and the output that drives and drive logical block is the output of adaptive power regulating circuit and is used for the power controlling pipe.
Wherein, described control logic unit is used for power output pipe control code, after described adaptive power regulating circuit resets, the maximum N=Nmax of power output pipe control code, wherein Nmax is the value that the control logic unit presets, and the register initial value of setting described time-to-digit converter is M, is output as K, the power tube control code is from subtracting N=N-1; Time-to-digit converter is used to detect PWM ripple pulsewidth, output K, if K<M, the power tube control code continues to subtract certainly, and N=N-1, M=K, time-to-digit converter detect and are used for PWM ripple pulsewidth; If K>M, the power tube control code is from adding, and N=N+1, time-to-digit converter detect and be used for PWM ripple pulsewidth.
Further, described control logic unit is realized with the ASIC application-specific integrated circuit (ASIC) by hardware description language.
Further, described driving and driving logical block comprise driver element and drive logical block, wherein, drive logical block and comprise decoder and P NAND gate, and wherein, P is the power tube number, and P is no more than 2
Nmax, the output of decoder links to each other with an input of P NAND gate respectively, and another input of P NAND gate is as the PWM input that drives and drive logical block.
Adaptive power control method based on above-mentioned adaptive power regulating circuit comprises the steps:
After step 1. adaptive power regulating circuit resets, the maximum N=Nmax of control logic unit power output pipe control code, wherein Nmax is the fixed value of control logic unit internal preset, the register initial value of setting described time-to-digit converter is M, be output as K, the power tube control code is from subtracting N=N-1;
Step 2. time-to-digit converter detects PWM ripple pulsewidth, output K;
Step 3. is as if K<M, and the power tube control code continues to subtract certainly, N=N-1, and M=K returns step 2; If K>M, the power tube control code is from adding, and N=N+1 returns step 2.
Beneficial effect of the present invention: the adaptive power regulating circuit and the method that the invention provides a kind of DC-DC of being used for converter, by time-to-digit converter and control logic unit, the pulsewidth that compares the PWM ripple, compared the system power dissipation under the different capacity pipe control code indirectly, output PWM ripple pulsewidth minimal power pipe control code, and then find the number of best power tube conducting, under the constant situation of power output, reduce input power, reduce system power dissipation, improve system effectiveness, and the circuit among the present invention is digital circuit, oneself power consumption is low, and chip occupying area is little.
Embodiment
The invention will be further elaborated below in conjunction with accompanying drawing and specific embodiment.
As shown in Figure 1, a kind of adaptive power regulating circuit, comprise and drive and drive logical block, time-to-digit converter and control logic unit, wherein, the PWM input of the input of time-to-digit converter and driving and driving logical block is used to import outside PWM ripple, the output of time-to-digit converter is connected with the input of control logic unit, the output of control logic unit is connected with the power tube control code input of driving and driving logical block, and the output that drives and drive logical block is the output of adaptive power regulating circuit and is used for the power controlling pipe.
Wherein, described control logic unit is used for power output pipe control code, after described adaptive power regulating circuit resets, the maximum N=Nmax of power output pipe control code, wherein Nmax is the value that the control logic unit presets, and the register initial value of setting described time-to-digit converter is M, is output as K, the power tube control code is from subtracting N=N-1; Time-to-digit converter is used to detect PWM ripple pulsewidth, output K, if K<M, the power tube control code continues to subtract certainly, and N=N-1, M=K, time-to-digit converter detect and are used for PWM ripple pulsewidth; If K>M, the power tube control code is from adding, and N=N+1, time-to-digit converter are used to detect PWM ripple pulsewidth.Here power tube control code N has determined the number of power tube conducting.
Here by regulating power management and control system sign indicating number N, PWM ripple duty ratio changes, and time-to-digit converter detects PWM wave height level width and also carries out logical operation, makes the power tube control code produce corresponding the variation, seeks to allow duty ratio minimal power pipe control code.
Here, the control logic unit can be realized with ASIC (Application Specific Integrated Circuit) application-specific integrated circuit (ASIC) by hardware description language.
In Fig. 1, VIN is the input voltage of Buck circuit, is connected to the source electrode of P type power tube PMOS, and PMOS and diode DIODE, inductance L, capacitor C have constituted simple Buck circuit together.The output voltage VO of Buck circuit produces corresponding PWM ripple by compensation and PWM generation unit.Drive and drive the power tube control code of logical block input PWM ripple and the output of control logic unit, the drive signal that output is corresponding, the corresponding power tube number of conducting, time-to-digit converter detects the PWM ripple simultaneously, detection power Guan Zaiyi the ON time that switch periods is interior, power tube in this cycle turn-offs period, gives the control logic unit with the output valve of time-to-digit converter.
Time-to-digit converter TDC structural representation is connected to form ring oscillator before and after the individual reverser of W (odd number) as shown in Figure 2, and ph1 to phW is respectively the output clock of W reverser.Two bit counters is W-1 two digit counters, and input clock ph1 to phW-1 is that Gao Shigao counts at the PWM ripple.Counter is a W digit counter, and input clock phW is that height is counted at the PWM ripple, and all Two bit counters output low two with Counter output are compared, and obtains comparison value, again all comparison value additions is obtained Y.The Counter output valve be multiply by W obtain Z.At last with the K that obtains of Y and Z addition.
Here, drive and drive logical block and comprise driver element and drive logical block, wherein, drive logical block and comprise decoder and P NAND gate, wherein, P is the power tube number, and P is no more than 2
Nmax, the output of decoder links to each other with an input of P NAND gate respectively, and another input of P NAND gate is as the PWM input that drives and drive logical block.
With three power tube control codes is that example describes driving and drives logical unit structure, as shown in Figure 3.Decoder is received the power tube control code S2 of control logic module output, S1, and S0, the output of process decoder is connected on a drive circuit with the PWM ripple through a NAND gate separately, drives a power tube.Always have 1 decoder, 7 NAND gate, 7 drive circuits and 7 power tubes.
Adaptive power control method based on above-mentioned adaptive power regulating circuit comprises the steps:
Fig. 4 is the schematic flow sheet of the adaptive power control method of adaptive power regulating circuit.Specifically be unfolded as follows:
After step 1. adaptive power regulating circuit resets, the maximum N=Nmax of control logic unit power output pipe control code, the value that presets for the control logic unit of Nmax wherein, the register initial value of setting described time-to-digit converter is M, be output as K, the power tube control code is from subtracting N=N-1;
Step 2. time-to-digit converter detects PWM ripple pulsewidth, output K;
Step 3. is as if K<M, and the power tube control code continues to subtract certainly, N=N-1, and M=K returns step 2; If K>M, the power tube control code is from adding, and N=N+1 returns step 2.
Inductive current and power tube current waveform schematic diagram when Fig. 5 stablizes for output.T is a switch periods, and d is a duty ratio.t
0Be the starting point of a switch periods, this moment, power tube current and inductive current were i
0At t
0To t
0+ dT during this period of time in, the power tube conducting, inductive current and power tube current are all pressed slope
Rise.At t
0+ dT is to t
0+ T during this period of time, power tube turn-offs, inductive current is pressed slope
Descend, power tube current is 0.
Introduce concrete operation principle of the present invention below in conjunction with Fig. 5.When the adaptive power regulating circuit was stablized, output power of circuit was constant, if the power tube ON time reduces, then input power reduces, and circuit efficiency improves.t
0Constantly, power tube begins conducting, and power tube current equals inductive current i
0, electric current is pressed slope
Rise, wherein L is the inductance value of inductance L, and duty ratio is d, and switch periods is T.At t
0In+dT the moment, inductive current and power tube current are i
1=i
0+ m
1DT, this moment loop stability, under the constant situation of load, the output energy constant of establishing each switch periods is E
o, the intake in each switch periods is:
As can be seen, d reduces along with duty ratio, intake E
iReduce efficient
Increase.The present invention is exactly under stable case, the ON time when counting by detecting conducting different capacity pipe, and promptly duty ratio selects duty ratio corresponding minimal power pipe number to carry out conducting.
The loss of power tube is from two parts: conduction loss and switching loss.When the conducting power tube the most for a long time, switching loss maximum, conduction loss minimum; When the conducting power tube is minimum be switching loss minimum, conduction loss maximum.There is a power tube conducting number between, makes switching loss and conduction loss sum minimum.Can detect duty ratio by the structure of Fig. 1 proposition, obtain optimal value.
Detecting duty ratio realizes by time-to-digit converter.Be connected to form ring oscillator before and after the individual reverser of W (odd number), ph1 to phW is respectively the output clock of W reverser.Two bit counters is W-1 two digit counters, and input clock ph1 to phW-1 is that Gao Shigao counts at the PWM ripple, and Counter is a W digit counter, and input clock phW is that height is counted at the PWM ripple.Low two with all Two bit counters outputs and Counter output compare, and obtain comparison value, again all comparison value additions are obtained Y, the Counter output valve be multiply by W obtain Z, with the K that obtains of Y and Z addition, are PWM ripple pulsewidth at last.
After time-to-digit converter detected and finishes, with the register value of output valve and time-to-digit converter, promptly current minimum value compared, and determines next power tube control code.
The power tube control code is delivered to and is driven and the driving logical block, and by decoder, output is passed through power tube of a drive unit drives after being connected on a NAND gate with the PWM ripple respectively.Because power tube is PMOS, has only when PWM ripple when being high the just possible conducting of power tube like this.
As can be seen, adaptive power regulating circuit of the present invention and method are by comparing the pulsewidth of PWM ripple, compared the system power dissipation under the different capacity pipe control code indirectly, output PWM ripple pulsewidth minimal power pipe control code finds the number of best power tube conducting, under the constant situation of power output, reduce input power, reduce system power dissipation, improve system effectiveness, and the circuit among the present invention is digital circuit, oneself power consumption is low, and chip occupying area is little.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that the protection range of inventing is not limited to such special statement and embodiment.Everyly make various possible being equal to according to foregoing description and replace or change, all be considered to belong to the protection range of claim of the present invention.