CN101931323A

CN101931323A - A Method of Improving Light Load Efficiency of Integrated Switching DC-DC Converter with Non-uniform Variation of Gate Width

Info

Publication number: CN101931323A
Application number: CN 201010246249
Authority: CN
Inventors: 高源�; 耿莉; 王轲; 范世全; 王胜磊; 李世杰
Original assignee: Xian Jiaotong University
Current assignee: Shaanxi Beidou Star Technology Development Co Ltd
Priority date: 2010-08-05
Filing date: 2010-08-05
Publication date: 2010-12-29
Anticipated expiration: 2030-08-05
Also published as: CN101931323B

Abstract

The invention discloses a method for improving the light-load efficiency of an integrated switch DC-DC converter by non-uniformly changing grid width. The Buck-Boost converter in the invention adopts the CSMC 0.5μm CMOS process library design to realize the removal of passive filter devices The external whole circuit is integrated, the external filter inductor is 2.2μH, and the filter capacitor is 1μF. According to the requirements for input and output voltages, the converter can work in three modes: Buck (step-down), Buck-Boost (boost-boost), and Boost (boost). The input voltage range is 2.5V-4.2V, and the output voltage range is 1.5V-5V, working frequency 5MHz. The non-uniform gate width modulation method is adopted in the whole load current range of 10mA-650mA. When the converter works at a high frequency of 5MHz, the efficiency of medium load and heavy load is always above 90%, while the efficiency of light load (10mA) reaches above 80%. Because only the grid width of the switch tube is changed, and no additional control link of the working frequency of the switch tube is adopted, the adverse consequences brought by the frequency conversion control are fundamentally eliminated.

Description

A Method of Improving Light Load Efficiency of Integrated Switching DC-DC Converter with Non-uniform Variation of Gate Width

技术领域：Technical field:

本发明属于DC-DC变换器领域，涉及一种一种提高集成开关DC-DC变换器轻载效率非均匀变化栅宽的方法The invention belongs to the field of DC-DC converters, and relates to a method for improving the light-load efficiency of integrated switch DC-DC converters by non-uniformly varying grid width

背景技术：Background technique:

随着便携式电子产品的不断进步，电源管理芯片市场发展迅速。由于便携式设备不断小型化的要求，开关电源产品集成化趋势越来越明显。提高开关频率能够有效减小电感、电容元件的尺寸，然而高频限制了开关电源的转换效率，尤其是轻负载处的效率。一般的便携式设备大部分时间工作在“待机”状态下，变换器的轻载效率的提升对于待机时间的延长至关重要。With the continuous advancement of portable electronic products, the power management chip market is developing rapidly. Due to the continuous miniaturization of portable equipment, the trend of integration of switching power supply products is becoming more and more obvious. Increasing the switching frequency can effectively reduce the size of inductors and capacitors, but high frequency limits the conversion efficiency of switching power supplies, especially the efficiency at light loads. General portable devices work in the "standby" state most of the time, and the improvement of the light-load efficiency of the converter is very important to prolong the standby time.

开关DC-DC变换器理论效率可达100％，但实际电路中由于非理想因素存在损耗。可以将开关DC-DC变换器的总损耗写成如下形式：The theoretical efficiency of the switching DC-DC converter can reach 100%, but there are losses due to non-ideal factors in the actual circuit. The total loss of a switching DC-DC converter can be written as:

${P P}_{loss loss} = = {k k}_{11} \frac{{I I}_{L L,, rms rms}^{22}}{W W} + + {k k}_{22} W W {f f}_{s the s} - - - - - - ((11))$

其中，W是开关MOS管栅宽，I_L，rms是通过开关管的均方根电流，f_s是开关频率，k₁和k₂是与栅宽W和频率f_s无关的系数。表达式中可以看出总损耗大致可以分为两项：第一项为导通损耗，是开关MOS管导通时电流通过开关MOS管的寄生电阻传输造成的损耗，其值与栅宽W成反比关系；第二项为开关损耗，主要是由于开关MOS管的导通关断对其本身及其驱动电路的寄生电容充放电造成的损耗，其值与栅宽W和开关频率f_s正比。Among them, W is the grid width of the switch MOS tube, I _{L, rms} is the root mean square current through the switch tube, f _s is the switching frequency, k ₁ and k ₂ are coefficients independent of the grid width W and frequency f _s . It can be seen from the expression that the total loss can be roughly divided into two items: the first item is conduction loss, which is the loss caused by the current passing through the parasitic resistance of the switch MOS tube when the switch MOS tube is turned on, and its value is proportional to the gate width W Inversely proportional relationship; the second item is the switching loss, which is mainly due to the loss caused by the on-off of the switching MOS tube and the parasitic capacitance charging and discharging of the driving circuit itself, and its value is proportional to the gate width W and the switching frequency f _s .

由于功率开关管的开关损耗不随变换器输出负载减小而降低，却与开关频率成正比。因此，栅驱动损耗和开关损耗成为高频率开关变换器轻载效率恶化的主导因素。Because the switching loss of the power switch tube does not decrease with the decrease of the output load of the converter, but is directly proportional to the switching frequency. Therefore, gate drive loss and switching loss become the dominant factors for the light-load efficiency deterioration of high-frequency switching converters.

对于轻载处的效率问题，市场上主流产品的解决方案是引入脉冲频率调制(PFM)模式，轻载时将变换器从脉冲宽度调制(PWM)转换到PFM控制模式下。此时，开关频率随着负载电流降低而降低，从而缓解了轻载情况下效率的恶化。例如文献：“双模式PWM/PFM控制的高效率直流-直流降压转换器，”(陈东坡，何乐年，严晓浪，第29卷第8期2008年8月，半导体学报)采用了PWM/PFM的双模式控制，使输出负载在20mA时依旧保持在55％以上。然而两种调制方式过渡时可能会造成不必要的尖锋电流。此外，由于PFM控制开关频率连续变化，而体现在开关变换器的输出电压中就变成了宽频谱范围的谐波噪声，会对系统造成电磁干扰，因此这种需要变频的变换器很难应用在对噪声敏感的系统中。For the efficiency problem at light load, the solution of mainstream products on the market is to introduce pulse frequency modulation (PFM) mode, and convert the converter from pulse width modulation (PWM) to PFM control mode at light load. At this time, the switching frequency decreases as the load current decreases, thereby alleviating the deterioration of efficiency under light load conditions. For example, the literature: "High Efficiency DC-DC Step-Down Converter Controlled by Dual Mode PWM/PFM," (Chen Dongpo, He Lenian, Yan Xiaolang, Volume 29, Issue 8, August 2008, Journal of Semiconductors) adopts PWM/PFM The dual-mode control keeps the output load above 55% at 20mA. However, the transition between the two modulation modes may cause unnecessary sharp currents. In addition, since the PFM controls the switching frequency to change continuously, the output voltage of the switching converter becomes harmonic noise with a wide spectrum range, which will cause electromagnetic interference to the system. Therefore, it is difficult to apply such a converter that requires frequency conversion. in noise-sensitive systems.

固定频率的解决方案也被提出，如文献“A Constant Frequency Method for ImprovingLight-Load Efficiency in Synchronous Buck Converters，”(M.D.Mulligan.B.Broach，and T.H.Lee，IEEE Power Electronics Letters，VOL.3，NO.1，MARCH 2005.S.)提出了开关管动态栅压摆幅的方法，在输出电流较小时采用降低开关MOS管上的充放电电压来减少其开关损耗。Fixed-frequency solutions have also been proposed, such as the literature "A Constant Frequency Method for Improving Light-Load Efficiency in Synchronous Buck Converters," (M.D.Mulligan.B.Broach, and T.H.Lee, IEEE Power Electronics Letters, VOL.3, NO. 1, MARCH 2005.S.) proposed a method of dynamic gate voltage swing of the switching tube, and reduced the charging and discharging voltage on the switching MOS tube to reduce its switching loss when the output current is small.

另一种固定频率的解决办法为开关MOS管动态栅宽调整的方法。如式(1)所示，变换器的两种损耗分别与开关MOS管栅宽成正比和反比，因此可以找到一个最优栅宽值使变换器的损耗达到最低。式(1)对栅宽W求导可以得到最佳栅宽使损耗达到最小，而此时的最优栅宽表达式如下：Another fixed-frequency solution is a method for adjusting the dynamic gate width of the switching MOS transistor. As shown in Equation (1), the two losses of the converter are directly proportional and inversely proportional to the gate width of the switching MOS transistor, so an optimal gate width value can be found to minimize the loss of the converter. Equation (1) deriving the gate width W can obtain the optimal gate width to minimize the loss, and the expression of the optimal gate width at this time is as follows:

${W W}_{opt opt} = = \sqrt{\frac{{k k}_{11}}{{k k}_{22} {f f}_{s the s}}} {I I}_{L L,, rms rms} - - - - - - ((22))$

由于均方根电流近似等于负载电流，所以从式(2)可以看出，最优栅宽随着负载电流减少而减小。为了实现宽负载范围内的高效率，须采用随负载电流变化的开关管栅宽。如图1示，在不同的电流范围采用不同的栅宽(W1，W2，W3)，可以使变换器在宽负载电流范围内保持较高的转换效率。文献“Improvement of Light-Load Efficiency UsingWidth-Switching Scheme for CMOS Transistors，”(Musunuri，and P.L.Chapman，IEEEPower Electronics Letters，VOL.3，NO.3，SEPTEMBER 2005)首先提出了这种提高效率的方法。文献″Dithering Skip Modulation，Width and Dead Time Controllers in Highly EfficientDC-DC Converters for System-On-Chip Applications，″(Hong-Wei，H.，C.Ke-Horng，IEEEJournal of Solid-State Circuits，42(11)：2451-2465，2007)的结构中也有相同的设计思想。Since the root mean square current is approximately equal to the load current, it can be seen from formula (2) that the optimal gate width decreases as the load current decreases. In order to achieve high efficiency over a wide load range, it is necessary to use a switch gate width that varies with the load current. As shown in Figure 1, using different gate widths (W1, W2, W3) in different current ranges can make the converter maintain a high conversion efficiency in a wide range of load currents. The document "Improvement of Light-Load Efficiency Using Width-Switching Scheme for CMOS Transistors," (Musunuri, and P.L.Chapman, IEEE Power Electronics Letters, VOL.3, NO.3, SEPTEMBER 2005) first proposed this method of improving efficiency. Literature "Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications," (Hong-Wei, H., C. Ke-Horng, IEEE Journal of Solid-State Circuits, 42(11 ): 2451-2465, 2007) also has the same design idea in the structure.

由于开关MOS管的栅宽并不能连续的变化，因此只能采用在一定负载电流范围内对应一个固定的栅宽。其具体实现办法是将若干开关MOS管并联在一起，变换器工作时可以根据负载电流的不同使部分的并联MOS管完全关断，而剩余的MOS管正常工作，达到动态调节开关管总栅宽的效果。以上的文献中动态栅宽方案都采用的是尺寸完全相同的MOS管并联在一起形成总的MOS管，因此栅宽无论在重负载还是在轻负载情况下，每次栅宽的变化值ΔW都是固定的。但是，研究表明，重负载和轻负载工作时，对栅宽变化值ΔW的要求是不同的，因此，如何确定不同负载情况时，开关管的最优变化尺寸成为进一步减小功耗，简化电路设计的关键。Since the grid width of the switching MOS transistor cannot be changed continuously, only a fixed grid width corresponding to a certain load current range can be used. The specific implementation method is to connect several switch MOS tubes in parallel. When the converter is working, part of the parallel MOS tubes can be completely turned off according to the difference in load current, while the remaining MOS tubes work normally, so as to dynamically adjust the total grid width of the switch tubes. Effect. The dynamic gate width schemes in the above documents all use MOS tubes of the same size to be connected in parallel to form a total MOS tube. Therefore, whether the gate width is under heavy load or light load, the change value ΔW of each gate width is the same. It is fixed. However, studies have shown that the requirements for the gate width change value ΔW are different when the load is heavy and light load. Therefore, how to determine the optimal change size of the switch tube under different load conditions is to further reduce power consumption and simplify the circuit. key to design.

发明内容：Invention content:

DC-DC变换器的效率表达式如下：The efficiency expression of the DC-DC converter is as follows:

$η η = = \frac{{P P}_{out out}}{{P P}_{out out} + + {P P}_{loss loss}} - - - - - - ((33))$

P_out为有效传输到负载上的功率，假设在某负载电流I_out处，使变换器效率达到最优的开关MOS管尺寸为W_opt，其满足表达式(2)，而此时对应的最优损耗(P_loss)_opt和最优效率η_opt的表达式如下：P _out is the power effectively transmitted to the load. Assume that at a certain load current I _out , the size of the switch MOS tube to achieve the optimum efficiency of the converter is W _opt , which satisfies the expression (2), and at this time the corresponding optimum The expressions of optimal loss (P _loss ) _opt and optimal efficiency η _opt are as follows:

${(({P P}_{loss loss}))}_{opt opt} = = 22 \sqrt{{k k}_{11} {k k}_{22} fs fs} {I I}_{L L,, rms rms} - - - - - - ((44))$

${η η}_{opt opt} = = \frac{{P P}_{out out}}{{P P}_{out out} + + {(({P P}_{loss loss}))}_{opt opt}} - - - - - - ((55))$

如果开关管的栅宽W并不在其最优值W_opt处，计算变换器效率保持在最优效率95％以上的开关管栅宽W的取值范围，从而确定并联的一组开关MOS管尺寸的大小。If the grid width W of the switch tube is not at its optimal value _Wopt , calculate the value range of the grid width W of the switch tube in which the efficiency of the converter remains above 95% of the optimal efficiency, so as to determine the size of a group of switch MOS tubes connected in parallel the size of.

η＞η_opt×95％ (6)η>η _opt ×95% (6)

为了使计算简单，可令To make the calculation simple, let

P_out＝n×(P_loss)_opt (7)P _out ＝n×(P _loss ) _opt (7)

其中，n为比例系数，在输出电压和负载电流确定时为一个确定值。将(5)和(7)式代入(6)式中，得到如下结果，Among them, n is a proportional coefficient, which is a definite value when the output voltage and load current are determined. Substituting equations (5) and (7) into equation (6), the following results are obtained,

$0.475 0.475 \times \times \frac{{W W}_{opt opt}}{W W} + + 0.475 0.475 \times \times \frac{W W}{{W W}_{opt opt}} < < 0.05 0.05 \times \times n no + + 11 - - - - - - ((88))$

根据经验，效率在重负载处的值一般大于90％，则在合理范围内可以取n＝10，得到W的取值范围如式(9)，According to experience, the value of efficiency at heavy load is generally greater than 90%, then n=10 can be taken within a reasonable range, and the value range of W can be obtained as formula (9),

0.357×W_opt＜W＜2.8×W_opt (9)0.357× _Wopt ＜W＜2.8× _Wopt (9)

从式(9)可以看出如果开关管的栅宽在一个大于0.357倍最优栅宽尺寸，小于2.4倍最优栅宽尺寸之间变化，都能保证95％η_opt的转换效率。但是，W_opt与负载电流成正比关系，大负载电流时，对应的可变化尺寸范围大，而随着负载电流的减小，这个保证高转换效率的栅宽尺寸范围也相应缩小，此时，负载电流较小的改变就可能使开关MOS管的实际栅宽超出此范围，造成转换效率的迅速下降。It can be seen from formula (9) that if the gate width of the switch tube changes between a size greater than 0.357 times the optimal gate width and less than 2.4 times the optimal gate width, the conversion efficiency of 95% η _opt can be guaranteed. However, W _opt is proportional to the load current. When the load current is large, the corresponding variable size range is large. As the load current decreases, the gate width size range that ensures high conversion efficiency is also reduced. At this time, A small change in the load current may cause the actual gate width of the switching MOS transistor to exceed this range, resulting in a rapid drop in conversion efficiency.

针对上述问题，本发明提出了栅宽调整变化值ΔW随负载电流改变的非均匀栅宽调整方法，并给予电路实现。本发明可以应用于不同类型(Buck、Buck-Boost及Boost变换器，但不限于此三类)的DC-DC变换器中。非均匀栅宽调整法主要针对重载和轻载工作是对栅宽变化的要求不同的提出的，变换器工作在固定高频下，也能通过此方法有效地提高轻载效率，避免通常的轻载效率解决方案常见的PFM调制带来的诸多问题。In view of the above problems, the present invention proposes a non-uniform gate width adjustment method in which the gate width adjustment variation value ΔW changes with the load current, and implements it in a circuit. The present invention can be applied to DC-DC converters of different types (Buck, Buck-Boost and Boost converters, but not limited to these three types). The non-uniform grid width adjustment method is mainly proposed for the heavy load and light load work, which have different requirements for the grid width change. The converter works at a fixed high frequency, and this method can also effectively improve the light load efficiency and avoid the usual Light-load efficiency solution to many problems caused by common PFM modulation.

变换器工作在大负载电流时，研究表明，保持开关MOS管总栅宽不变，效率曲线在一个较大的负载电流的变化范围内，变化不是很明显。因此，在此负载区间，不需要频繁地改变开关管的尺寸，本发明设计的栅宽调整技术，在重载范围，采用较大的栅宽变化值ΔW。实际上，重负载时采用大的ΔW值也会减少频繁调整栅宽尺寸造成的能量损失。而变换器工作在小负载电流时，效率曲线随负载电流的减小恶化非常明显，则需要选择更小的栅宽变化值ΔW。设计时，在整个负载范围内，栅宽变化值ΔW与负载电流成正比例变化，从而可以充分地利用栅宽调制的方法，使变换器的转化效率整体保持在较高的水平。When the converter works at a large load current, the research shows that keeping the total gate width of the switching MOS tube constant, the efficiency curve is within a large load current range, and the change is not obvious. Therefore, in this load range, there is no need to frequently change the size of the switch tube. The gate width adjustment technology designed in the present invention adopts a larger gate width change value ΔW in the heavy load range. In fact, using a large ΔW value for heavy loads will also reduce the energy loss caused by frequent adjustments to the gate width. However, when the converter operates at a small load current, the efficiency curve deteriorates significantly with the decrease of the load current, so a smaller gate width change value ΔW needs to be selected. During design, the gate width variation value ΔW changes in direct proportion to the load current within the entire load range, so that the grid width modulation method can be fully utilized to keep the overall conversion efficiency of the converter at a relatively high level.

本发明针对高频开关DC-DC变换器轻载效率低的问题，提出了一种利用非均匀变化栅宽，实现固定频率、宽负载范围内、高效率的解决方法，并将其应用于四开关型Buck-Boost开关DC-DC变换器中。Aiming at the problem of low light-load efficiency of high-frequency switching DC-DC converters, the present invention proposes a solution to realize fixed frequency, wide load range, and high efficiency by using non-uniform variation of grid width, and applies it to four Switching Buck-Boost switching DC-DC converter.

为达到以上目的，本发明采取如下技术方案予以实现：本发明的目的在于克服上述现有技术的缺点，提供一种提高开关DC-DC变换器轻载效率非均匀变化栅宽的方法，其实现方案包括功率MOS管栅宽可调开关DC-DC变换器电路结构和非均匀栅宽优化方法两部分。In order to achieve the above object, the present invention takes the following technical solutions to achieve: the purpose of the present invention is to overcome the above-mentioned shortcoming of the prior art, and to provide a method for improving the light-load efficiency of the switching DC-DC converter to change the grid width non-uniformly, and it realizes The scheme includes two parts: the circuit structure of the power MOS tube gate width adjustable switch DC-DC converter and the optimization method of the non-uniform gate width.

一种功率MOS管栅宽可调DC-DC变换器，该宽负载电流范围高效DC-DC变换器包括：功率级主电路及其驱动模块，PWM控制模块，模式选择模块，片内电流检测模块，延迟线ADC模块，开关管栅宽控制模块和死区时间控制模块。A DC-DC converter with adjustable grid width of power MOS transistors. The high-efficiency DC-DC converter with a wide load current range includes: a power stage main circuit and its drive module, a PWM control module, a mode selection module, and an on-chip current detection module , a delay line ADC module, a switching tube grid width control module and a dead time control module.

所述功率级主电路及其驱动模块，V_in端口与电源输入端相连接，V_out端口与变换器电压输出端口相连，GND端口与外接地线相连；V_x端和V_y端与外接电感L两端连接，V_x端同时与电流检测模块相连，为其提供检测信号；功率级主电路及其驱动模块与开关管栅宽控制模块通过栅宽数字选择码D₀～D_m-1，D_extra连接，栅宽数字选择码用于调整功率开关管尺寸；功率级主电路及其驱动模块与死区时间控制模块通过四路PWM信号(PWM_P1，PWM_N1，PWM_P2，PWM_N2)连接，PWM信号为功率级主电路中的4个可调栅宽开关管的控制信号。The main circuit of the power stage and its drive module, the V _in port is connected to the power input terminal, the V _out port is connected to the converter voltage output port, the GND port is connected to the external ground wire; the V _x terminal and the V _y terminal are connected to the external inductor The two ends of L are connected, and the V _x terminal is connected to the current detection module at the same time to provide detection signals; the main circuit of the power stage and its drive module and the switching tube grid width control module pass the grid width digital selection code D ₀ ~ D _m-1 , D _extra connection, the gate width digital selection code is used to adjust the size of the power switch tube; the main circuit of the power stage and its drive module and the dead time control module are connected through four PWM signals (PWM_P1, PWM_N1, PWM_P2, PWM_N2), and the PWM signal is The control signals of the four adjustable gate width switch tubes in the main circuit of the power stage.

所述PWM控制模块，其输入端与输出反馈信号b·V_out相连接，信号b·V_out由变换器输出电压通过电阻R_b1，R_b2分压获得；其输出端产生的PWM_C信号与死区时间控制模块相连接。In the PWM control module, its input terminal is connected to the output feedback signal b·V _out , and the signal b·V _out is obtained by dividing the output voltage of the converter through resistors R _b1 and R _b2 ; Zone time control module is connected.

所述模式选择模块，V_in端口与电源输入端相连接，V_out端口与变换器电压输出端相连。模式选择模块通过比较输入电压与输出电压的大小，获得模式选择信号S_Mode，用于确定变换器的工作模式，并通过S_Mode信号分别与死区时间控制模块和开关管栅宽控制模块相连接。In the mode selection module, the V _in port is connected to the power supply input end, and the V _out port is connected to the converter voltage output end. The mode selection module obtains the mode selection signal S _Mode by comparing the input voltage and the output voltage, which is used to determine the working mode of the converter, and is connected to the dead time control module and the switch gate width control module respectively through the S _Mode signal .

所述片内电流检测模块，V_in端口与电源输入端相连接，V_x端口与功率级主电路及其驱动模块相连接；输出端口产生与电感电流成正比例的检测电压信号V_sense，并通过V_sense信号与延迟线ADC模块和死区时间控制模块相连接。In the on-chip current detection module, the V _in port is connected to the input terminal of the power supply, and the V _x port is connected to the main circuit of the power stage and its drive module; the output port generates a detection voltage signal V _sense proportional to the inductor current, and passes The V _sense signal is connected with the delay line ADC module and the dead time control module.

所述延迟线ADC模块，输入端口通过V_sense信号与片内电流检测模块连接。延迟线ADC模块将模拟电压信号V_sense转换成m位温度数字码Q₀～Q_m-1，并通过数字码与开关管栅宽控制模块相连接。The input port of the delay line ADC module is connected to the on-chip current detection module through the V _sense signal. The delay line ADC module converts the analog voltage signal V _sense into m-bit temperature digital codes Q ₀ ˜Q _m-1 , and connects the digital codes with the switch gate width control module.

所述开关管栅宽控制模块，通过数字码Q₀～Q_m-1与开关管栅宽控制模块相连接，通过模式选择信号S_Mode与模式选择模块相连接，通过栅宽数字选择码D₀～D_m-1，D_extra与功率级主电路及其驱动模块相连接。The switching tube grid width control module is connected to the switching tube grid width control module through digital codes Q ₀ to Q _m-1 , connected to the mode selection module through the mode selection signal S _Mode , and connected to the switching tube grid width control module through the grid width digital selection code D ₀ ～D _m-1 , D _extra is connected with the main circuit of the power stage and its driving module.

所述死区时间控制模块，通过模式选择信号S_Mode与模式选择模块相连接，通过PWM_C信号与PWM控制模块相连接，通过V_sense信号与片内电流检测模块相连接，通过四路PWM信号(PWM_P1，PWM_N1，PWM_P2，PWM_N2)与功率级主电路及其驱动模块相连接。死区时间控制模块参考不同的工作模式通过对PWM_C信号加入一定的死区时间获得四路PWM信号(PWM_P1，PWM_N1，PWM_P2，PWM_N2)，并参考工作模式和电流检测获得电压调整死区时间大小。The dead time control module is connected with the mode selection module by the mode selection signal S _Mode , is connected with the PWM control module by the PWM_C signal, is connected with the on-chip current detection module by the V _sense signal, and is connected by the four-way PWM signal ( PWM_P1, PWM_N1, PWM_P2, PWM_N2) are connected to the power stage main circuit and its driving module. The dead time control module refers to different working modes to obtain four PWM signals (PWM_P1, PWM_N1, PWM_P2, PWM_N2) by adding a certain dead time to the PWM_C signal, and obtains the voltage adjustment dead time by referring to the working mode and current detection.

上述技术方案中，功率级主电路及其驱动模块通过不同尺寸的开关管并联实现M_N1、M_P1、M_N2和M_P2四个开关MOS管非均匀调整。对于负载电流变化范围为(I_min，I_max)的四开关Buck-Boost变换器，通过非均匀栅宽优化方法将四个开关管M_N1、M_P1、M_N2和M_P2的尺寸进行分成不等长的m+1段。其中，组成M_P1管的每段并联MOS管的源漏分别接在V_in和V_x端口，组成M_N1管的每段并联MOS管的源漏分别接在GND和V_x端口，组成M_P2管的每段并联MOS管的源漏分别接在V_out和V_y端口，组成M_N2管的每段并联MOS管的源漏分别接在GND和V_y端口。任何一段并联MOS管都有独立的与其尺寸相适应的驱动电路与其栅极相连接，驱动开关管正常导通和关断。组成四个开关管M_N1、M_P1、M_N2和M_P2并联开关管的驱动电路输入端分别与上述死区时间控制模块输出信号PWM_N1，PWM_P1，PWM_N2，PWM_P2相连接。同时，每段并联MOS管的驱动电路都有使能端口，分别与栅宽数字选择码D₀～D_m-1，D_extra相连接。以开关管M_P1为例，它由M_P1(0)到M_P1(m)共m+1个不等长的MOS管并联而成，其中，一个MOS管M_P1(m)始终保持可工作状态，而其它MOS管M_P1(0)-M_P1(m-1)分别由所对应的数字码D₀-D_m-1控制，数字码通过驱动使能来控制单个并联MOS管处在工作或关断状态。开关管M_N1、M_N2控制和实现栅宽选择方式与M_P1管相同。而为保证各个模式下变换器的正常工作，开关管M_P2的除了上述m+1段并联MOS管，还需要附加仅用于工作在Buck模式的一个附加管M_P2(extra)，其连接方式与M_P2其它段并联管一样，驱动使能端与D_extra相连接。In the above technical solution, the main circuit of the power stage and its driving module realize non-uniform adjustment of the four switch MOS transistors M _N1 , _MP1 , M _N2 and _MP2 through parallel connection of switch tubes of different sizes. For a four-switch Buck-Boost converter with a load current variation range of (I _min , I _max ), the sizes of the four switch tubes M _N1 , _MP1 , M _N2 and _MP2 are divided into different sizes by using the non-uniform gate width optimization method. m+1 segments of equal length. Among them, the source and drain of each parallel MOS transistor forming M _P1 tube are respectively connected to V _in and V _x ports, and the source and drain of each parallel MOS tube forming M _N1 tube are respectively connected to GND and V _x ports to form _MP2 The source and drain of each parallel MOS tube of the tube are respectively connected to the V _out and V _y ports, and the source and drain of each parallel MOS tube forming the _MN2 tube are respectively connected to the GND and V _y ports. Any section of parallel MOS transistors has an independent drive circuit that is suitable for its size and is connected to its gate to drive the switch tube to turn on and off normally. The input terminals of the drive circuit forming the four switching tubes M _N1 , _MP1 , M _N2 and _MP2 connected in parallel are respectively connected to the output signals PWM_N1 , PWM_P1 , PWM_N2 and PWM_P2 of the dead time control module. At the same time, the driving circuit of each parallel MOS transistor has an enabling port, which is respectively connected to the gate width digital selection codes D ₀ -D _m-1 and D _extra . Taking the switching tube M _P1 as an example, it is composed of m+1 MOS tubes of different lengths from M _P1 (0) to M _P1 (m) connected in parallel, and one MOS tube M _P1 (m) is always operable state, while the other MOS tubes M _P1 (0)-M _P1 (m-1) are controlled by the corresponding digital codes D ₀ -D _m-1 respectively, and the digital codes control a single parallel MOS tube to work through the drive enable or shutdown state. The switching tubes M _N1 and M _N2 are controlled and realized in the same way as the M _P1 tube for gate width selection. In order to ensure the normal operation of the converter in each mode, in addition to the above-mentioned m+1 parallel MOS transistors of the switch tube M _P2 , an additional tube M _P2 (extra) that is only used to work in the Buck mode needs to be added. The connection method Like other parallel tubes of _MP2 , the drive enable end is connected to D _extra .

一种前述的非均匀栅宽优化方法，基于上述四开关Buck-Boost变换器系统获得组成功率开关管M_N1、M_P1、M_N2和M_P2的并联开关管的数目m+1和各自尺寸W_M(0)-W_M(m)。由于M_N1、M_P1、M_N2和M_P2四个开关管尺寸设计方法完全一样，方便起见，采用M管代替。设M管的总栅宽大小为W_total，由m+1个不等长的并联MOS管M(0)-M(m)组成，对应尺寸分别为W_M(0)-W_M(m)。控制M管调整栅宽调整的是数字码，从M(0)到M(m)随着负载电流减小依次关断，可以依次实现W_opt(0)到W_opt(m)共m+1种栅宽尺寸。设I_out(0)到I_out(m)为分别对应W_opt(0)到W_opt(m)不同尺寸达到最高效率的最优负载电流。A method for optimizing the aforementioned non-uniform gate width, based on the above-mentioned four-switch Buck- _Boost converter system _to obtain the number m+ ₁ and _the respective sizes W _M (0)-W _M (m). Since M _N1 , M _P1 , M _N2 and M _P2 are designed in exactly the same size, M tubes are used instead for convenience. Let the total gate width of the M tube be W _total , which is composed of m+1 parallel MOS tubes M(0)-M(m) with different lengths, and the corresponding dimensions are W _M (0)-W _M (m) . The digital code is used to control the M tube to adjust the gate width. From M(0) to M(m), it is turned off sequentially as the load current decreases, and a total of m+1 from W _opt (0) to W _opt (m) can be realized sequentially. Kind of grid width size. Let I _out (0) to I _out (m) be the optimal load currents corresponding to different sizes of W _opt (0) to W _opt (m) respectively to achieve the highest efficiency.

如前所述的实现提高集成开关DC-DC变换器轻载效率非均匀变化栅宽的方法，按照如下步骤：As mentioned above, the method for improving the light-load efficiency of the integrated switching DC-DC converter with non-uniform variation of the gate width follows the following steps:

(a)按照上述连接方式搭建四开关Buck-Boost变换器系统；(a) Build a four-switch Buck-Boost converter system according to the above connection method;

(b)根据所需最大负载电流I_max确定功率开关管M_N1、M_P1、M_N2和M_P2总尺寸；确定I_out(0)≈0.6×I_max时对应的最优尺寸W_opt(0)，也就是开关MOS管的总尺寸W_total；(c)根据总尺寸W_total和所需最小负载电流I_min，采用栅宽变化值ΔW＝0.5×W_opt确定M(0)-M(m)的尺寸，实现非均匀可变栅宽调整。确定开关管M(0)的尺寸的同时确定除去M(0)管外剩余的开关管的尺寸W_opt(1)，(b) Determine the total size of the power switch tubes M _N1 , M _P1 , M _N2 and M _P2 according to the required maximum load current I _max ; determine the corresponding optimal size W _opt (0 when I _out (0)≈0.6×I _max ), that is, the total size W _total of the switch MOS transistor; (c) according to the total size W _total and the required minimum load current I _min , _determine M(0)-M(m ) size to achieve non-uniform variable gate width adjustment. Determine the size W _opt (1) of the remaining switch tube outside the M (0) tube while determining the size of the switch tube M (0),

${W W}_{M m} ((00)) = = {W W}_{opt opt} ((11)) = = \frac{{W W}_{opt opt} ((00))}{22} - - - - - - ((1111))$

W_opt(1)达到其效率达到最优值时的负载电流I_out(1)，W _opt (1) is the load current I _out (1) at which its efficiency reaches its optimum value,

${I I}_{out out} ((11)) = = \frac{{I I}_{out out} ((00))}{22} - - - - - - ((1212))$

依次按照上述的方法推导可以得到所需的并联各管的尺寸M(i-1)，i＝1，2，3，…，直到满足i＝m，使得I_out(m+1)＜I_min，确定并联开关管的个数m+1；Derivation according to the above-mentioned method in turn can obtain the required size M(i-1) of each parallel pipe, i=1, 2, 3, ..., until satisfying i=m, so that I _out (m+1)<I _min , to determine the number m+1 of parallel switch tubes;

${W W}_{M m} ((i i - - 11)) = = {W W}_{opt opt} ((i i)) = = \frac{{W W}_{opt opt} ((i i - - 11))}{22} = = \frac{{W W}_{opt opt} ((00))}{22^{i i}},, i i = = 1,2,3 1,2,3,, \cdot &Center Dot;,, m m - - - - - - ((1313))$

而剩余的部分即是最后一个开关管M(m)的尺寸，And the remaining part is the size of the last switch tube M(m),

${W W}_{M m} ((m m)) = = {W W}_{opt opt} ((m m)) = = {W W}_{opt opt} ((00)) - - {Σ Σ}_{i i = = 11}^{m m - - 11} {W W}_{M m} ((i i)) = = \frac{{W W}_{opt opt} ((00))}{22^{m m}} - - - - - - ((1414))$

W_opt(0)到W_opt(m)为变换器中可通过数字码实现的不同的栅宽尺寸，它们各自效率达到最优时，对应的负载电流I_out(0)到I_out(m)如下：W _opt (0) to W _opt (m) are the different grid width sizes that can be realized by digital codes in the converter. When their respective efficiency reaches the optimum, the corresponding load current I _out (0) to I _out (m) as follows:

${I I}_{out out} ((n no)) = = \frac{{I I}_{out out} ((n no - - 11))}{22} = = \frac{{I I}_{out out} ((00))}{22^{m m}} - - - - - - ((1515));;$

(d)设计各个并联开关管的尺寸，确定非均匀变化的各个栅宽值对应的负载电流范围以使变换器的转换效率保持最优；关断延迟线ADC的功能，向开关管栅宽控制模块直接加入不同的数字码对应不同的栅宽，获得随负载电流变化的效率曲线；对于所有负载电流范围内，选取达到效率最高时的数字码，确定各个栅宽值对应的负载电流范围；(d) Design the size of each parallel switch tube, determine the load current range corresponding to each grid width value of non-uniform change so that the conversion efficiency of the converter can be kept optimal; turn off the function of the delay line ADC, and control the grid width of the switch tube The module directly adds different digital codes corresponding to different grid widths, and obtains the efficiency curve that changes with the load current; for all load current ranges, select the digital code that reaches the highest efficiency to determine the load current range corresponding to each grid width value;

(e)调节延迟线ADC输出数字码Q₀～Q_m-1与上述检测电压V_sense的变化关系，使得ADC输出数字码Q₀～Q_m-1与步骤(d)中计算得到的负载电流范围对应；(e) Adjust the relationship between the delay line ADC output digital code Q ₀ ~Q _m-1 and the above detection voltage V _sense , so that the ADC output digital code Q ₀ ~Q _m-1 and the load current calculated in step (d) range correspondence;

(f)实现栅宽随负载电流非均匀变化的自适应调整。(f) Realize the self-adaptive adjustment of the gate width with the non-uniform change of the load current.

本发明采用本发明设计的高频非均匀栅宽变化方法的Buck-Boost变换器，采用CSMC0.5μm CMOS工艺库设计，实现除无源滤波器件外的全电路集成，外接滤波电感为2.2μH，滤波电容为1μF。根据对输入输出电压的要求，变换器可以工作在Buck、Buck-Boost、Boost三种模式下，输入电压范围2.5V-4.2V，输出电压范围1.5V-5V，工作频率5MHz。在整个负载电流范围10mA-650mA内采用非均匀的栅宽调制方法，变换器在开关频率等于5MHz的高频下工作时，其中等负载及重负载效率始终保持在90％以上，而轻载效率得到了大幅度的提高，对于Buck变换模式和Boost变换模式，负载电流为10mA时效率分别可达到80％和84％。The present invention adopts the Buck-Boost converter of the high-frequency non-uniform gate width variation method designed by the present invention, adopts the CSMC0.5μm CMOS process library design, realizes the whole circuit integration except the passive filter device, and the external filter inductance is 2.2μH, The filter capacitor is 1μF. According to the requirements for input and output voltage, the converter can work in three modes: Buck, Buck-Boost, and Boost, with an input voltage range of 2.5V-4.2V, an output voltage range of 1.5V-5V, and an operating frequency of 5MHz. In the entire load current range of 10mA-650mA, the non-uniform grid width modulation method is adopted. When the converter operates at a high frequency with a switching frequency equal to 5MHz, the efficiency of the medium load and heavy load is always above 90%, while the efficiency of light load is always above 90%. It has been greatly improved. For Buck conversion mode and Boost conversion mode, the efficiency can reach 80% and 84% respectively when the load current is 10mA.

此发明通过对高频开关变换器的功耗分析，得出不同负载条件下，开关管栅宽调制的规律和方法，从而制定出完整的解决方案。实现了对轻载效率的显著提高。由于只是改变了开关管的栅宽，并不采取额外开关管工作频率的控制环节，从根本上消除了变频控制带来的不良后果。By analyzing the power consumption of the high-frequency switching converter, the invention obtains the law and method of the grid width modulation of the switching tube under different load conditions, and thus formulates a complete solution. A significant increase in light load efficiency is achieved. Because only the grid width of the switch tube is changed, and no additional control link of the working frequency of the switch tube is adopted, the adverse consequences brought by the frequency conversion control are fundamentally eliminated.

附图说明：Description of drawings:

图1为开关管栅宽调制的基本原理和依据。Figure 1 shows the basic principle and basis of the gate width modulation of the switching tube.

图2为本发明设计的非均匀变化栅宽调制电路在Buck-Boost DC-DC变换器中的具体电路实现方案。Fig. 2 is a specific circuit implementation scheme of the non-uniform variable grid width modulation circuit designed in the present invention in the Buck-Boost DC-DC converter.

图3为图2中非均匀变化栅宽开关管设计及其驱动电路。其中图3(a)为功率开关管M_P1及其驱动电路；图3(b)为功率开关管M_N1及其驱动电路；图3(c)为功率开关管M_P2及其驱动电路；图3(d)为功率开关管M_N2及其驱动电路。Fig. 3 shows the design and driving circuit of the non-uniform variable gate width switch tube in Fig. 2 . Wherein Fig. 3 (a) is the power switch M _P1 and its drive circuit; Fig. 3 (b) is the power switch M _N1 and its drive circuit; Fig. 3 (c) is the power switch M _P2 and its drive circuit; Fig. 3(d) is the power switch tube M _N2 and its driving circuit.

图4为采用本发明获得的DC-DC变换器转换效率随负载电流变化的模拟结果图。其中图4(a)为Buck模式下转换效率随负载电流变化模拟结果图；图4(b)为Boost模式下转换效率随负载电流变化模拟结果图。Fig. 4 is a graph showing the simulation results of the DC-DC converter conversion efficiency changing with the load current obtained by the present invention. Among them, Figure 4(a) is the simulation result diagram of conversion efficiency changing with load current in Buck mode; Figure 4(b) is the simulation result diagram of conversion efficiency changing with load current in Boost mode.

具体实施方式：Detailed ways:

下面结合附图对本发明做进一步详细描述：The present invention is described in further detail below in conjunction with accompanying drawing:

本发明具体实现的非均匀栅宽调整Buck-Boost开关DC-DC变换器整体电路结构如图2所示，包括功率级主电路及其驱动模块，PWM控制模块，模式选择模块，片内电流检测模块，延迟线ADC模块，开关管栅宽控制模块和死区时间控制模块。图2中的电感L、电容C为外接的分立器件，R_L为负载；图2中各个框图为实现某一特定功能的模块，而所有的模块均为IC内部电路。The overall circuit structure of the non-uniform gate width adjustment Buck-Boost switch DC-DC converter realized in the present invention is shown in Figure 2, including the power stage main circuit and its drive module, PWM control module, mode selection module, and on-chip current detection module, a delay line ADC module, a switching tube gate width control module and a dead time control module. The inductor L and capacitor C in Figure 2 are external discrete devices, and _RL is the load; each block diagram in Figure 2 is a module that realizes a certain function, and all modules are IC internal circuits.

如图2所示，功率级主电路及其驱动模块实现Buck，Boost和Buck-Boost不同电压变换类型的功率传输功能。所述功率级主电路及其驱动模块与其它模块连接方式如下：V_in与电源输入端连接，V_out与电源输出端连接，GND与外接地相连；V_x和V_y与外接电感L两端连接，V_x端同时与电流检测模块相连；通过栅宽数字选择码D₀～D_m-1，D_extra与开关管栅宽控制模块连接；通过四路PWM信号(PWM_P1，PWM_N1，PWM_P2，PWM_N2)与死区时间控制模块连接。其内部M_N1、M_N2、M_P1、M_P2四个采用栅宽可调开关MOS管的基本连接方式如下：M_P1管源漏分别接在V_in和V_x端口，M_N1源漏分别接在GND和V_x端口，M_P2管源漏分别接在V_out和V_y端口，M_N2管源漏分别接在GND和V_y端口。其中M_N1和M_N2是NMOS，M_P1和M_P2是PMOS，其基本控制模式分为以下三种：若开关M_N2保持关断，M_P2保持导通，由PWM控制M_N1和M_P1，变换器工作于Buck模式；若开关M_N1保持关断，M_P1保持导通，M_N2和M_P2由PWM控制，变换器工作于Boost模式；若4个开关MOS管同时由PWM信号控制，则工作于Buck-Boost模式。由于功率开关MOS管尺寸很大，每个开关管都需要逐级放大的反相器链作为驱动。如图2所示，PWM控制模块与其它模块连接方式如下：输入端与输出反馈信号b·V_out相连接，信号b·V_out由变换器输出电压通过电阻R_b1，R_b2分压获得；输出端通过PWM_C信号与死区时间控制模块相连接。其主要功能是是根据输出反馈信号b·V_out获得固定频率可调占空比的PWM控制信号用于控制功率开关MOS管。As shown in Figure 2, the main circuit of the power stage and its drive module realize the power transmission functions of different voltage conversion types of Buck, Boost and Buck-Boost. The main circuit of the power stage and its drive module are connected to other modules in the following manner: V _in is connected to the input terminal of the power supply, V _out is connected to the output terminal of the power supply, GND is connected to the external ground; V _x and V _y are connected to both ends of the external inductor L The V _x terminal is connected to the current detection module at the same time; through the gate width digital selection code D ₀ ~D _m-1 , D _extra is connected to the switch gate width control module; through four PWM signals (PWM_P1, PWM_N1, PWM_P2, PWM_N2 ) is connected with the dead time control module. The basic connection methods of the four internal M _N1 , M _N2 , _MP1 , and _MP2 adopt adjustable gate width switch MOS tubes are as follows: the source and drain of M _P1 tube are respectively connected to the Vin _and V _x ports, and the source and drain of M _N1 are respectively connected to At the GND and V _x ports, the source and drain of the M _{P2 tube} are respectively connected to the V _out and V _y ports, and the source and drain of the M _N2 tube are respectively connected to the GND and V _y ports. Among them, M _N1 and M _N2 are NMOS, _MP1 and _MP2 are PMOS, and their basic control modes are divided into the following three types: if the switch M _N2 is kept off, _MP2 is kept on, and M _N1 and M _P1 are controlled by PWM, The converter works in Buck mode; if the switch M _N1 keeps off, _MP1 keeps on, M _N2 and _MP2 are controlled by PWM, and the converter works in Boost mode; if the four switch MOS tubes are controlled by PWM signal at the same time, then Work in Buck-Boost mode. Due to the large size of the power switch MOS tube, each switch tube needs a progressively amplified inverter chain as a drive. As shown in Figure 2, the PWM control module is connected to other modules as follows: the input terminal is connected to the output feedback signal b·V _out , and the signal b·V _out is obtained by dividing the output voltage of the converter through resistors R _b1 and R _b2 ; The output end is connected with the dead time control module through the PWM_C signal. Its main function is to obtain a PWM control signal with a fixed frequency and an adjustable duty cycle according to the output feedback signal b·V _out to control the power switch MOS tube.

如图2所示，模式选择模块V_in端口与电源输入端相连接，V_out端口与变换器电压输出端相连，通过S_Mode信号分别与死区时间控制模块和开关管栅宽控制模块相连接。模式选择模块是根据输入电压V_in和输出电压V_out的比较获得模式选择信号S_Mode，实现系统工作模式的选择。As shown in Figure 2, the V _in port of the mode selection module is connected to the input terminal of the power supply, the V _out port is connected to the voltage output terminal of the converter, and is connected to the dead time control module and the switch gate width control module respectively through the S _Mode signal . The mode selection module obtains the mode selection signal S _Mode according to the comparison of the input voltage V _in and the output voltage V _out to realize the selection of the working mode of the system.

如图2所示，片内电流检测模块是实现本发明的一个主要模块。其V_in端口与电源输入端相连接，V_x端口与功率级主电路及其驱动模块相连接，通过V_sense信号与延迟线ADC模块和死区时间控制模块相连接。其主要功能是通过检测功率开关管M_P1两端的电压信号，获得电感电流的变化信息，经过片内电流检测模块，以电压信号V_sense的形式输出。信号V_sense随负载电流I_out线性变化，因此可以准确的反应负载的变化情况。V_sense信号同时提供给延迟线ADC和死区时间控制模块。As shown in Fig. 2, the on-chip current detection module is a main module for realizing the present invention. Its V _in port is connected to the power supply input terminal, its V _x port is connected to the main circuit of the power stage and its drive module, and is connected to the delay line ADC module and the dead time control module through the V _sense signal. Its main function is to obtain the change information of the inductor current by detecting the voltage signal at both ends of the power switch tube _MP1 , and output it in the form of a voltage signal V _sense through the on-chip current detection module. The signal V _sense changes linearly with the load current I _out , so it can accurately reflect the change of the load. The V _sense signal is provided to the delay line ADC and the dead time control module at the same time.

如图2所示，延迟线ADC模块是实现本发明的一个主要模块。延迟线ADC模块通过V_sense信号与片内电流检测模块连接，通过数字码Q₀～Q_m-1与开关管栅宽控制模块相连接。其主要功能在于实现将由片内电流检测模块输出的变化微小的V_sense信号转换成温度数字码，即输出码中“1”的个数随采样得到的V_sense电平增加而连续增加。得到m位数字码Q_m-1...Q₂Q₁Q₀只可能为如下数据中的一组(00…000，10…000，11…000，……，11…100，111…10，1111…1)，并且随着负载电流的增加，数字码按照上述的顺序依次变化。这样的温度数字码不用再进行编码而可以直接通过加入驱动电路中。由于数字码从Q_m-1到Q₀所控制的开关管的尺寸逐渐增加，即可以实现非均匀栅宽的调整。As shown in Fig. 2, the delay line ADC module is a main module for realizing the present invention. The delay line ADC module is connected with the on-chip current detection module through the V _sense signal, and connected with the switching tube grid width control module through the digital codes Q ₀ ~Q _m-1 . Its main function is to convert the slightly changing V _sense signal output by the on-chip current detection module into a temperature digital code, that is, the number of "1" in the output code increases continuously with the increase of the sampled V _sense level. The m-digit digital code Q _m-1 ...Q ₂ Q ₁ Q ₀ can only be a set of the following data (00...000, 10...000, 11...000,..., 11...100, 111...10 , 1111...1), and with the increase of the load current, the digital code changes sequentially according to the above sequence. Such temperature digital codes can be directly added to the drive circuit without encoding. Since the size of the switching tube controlled by the digital code from Q _m-1 to Q ₀ increases gradually, the adjustment of the non-uniform grid width can be realized.

如图2所示，开关管栅宽控制模块通过数字码Q₀～Q_m-1与开关管栅宽控制模块相连接，通过模式选择信号S_Mode与模式选择模块相连接，通过栅宽数字选择码D₀～D_m-1，D_extra与功率级主电路及其驱动模块相连接。其主要功能是根据不同的工作模式对延迟线ADC输出的数字码进行调整，并加载入功率级主电路及其驱动电路模块中实现非均匀栅宽的调整。As shown in Figure 2, the switching tube grid width control module is connected to the switching tube grid width control module through digital codes Q ₀ ~ Q _m-1 , connected to the mode selection module through the mode selection signal S _Mode , and selected through the grid width digital Codes D ₀ ˜D _m-1 , D _extra are connected to the main circuit of the power stage and its driving module. Its main function is to adjust the digital code output by the delay line ADC according to different working modes, and load it into the main circuit of the power stage and its driving circuit module to realize the adjustment of the non-uniform gate width.

如图2所示，所述死区时间控制模块，通过模式选择信号S_Mode与模式选择模块相连接，通过PWM_C信号与PWM控制模块相连接，通过V_sense信号与片内电流检测模块相连接，通过四路PWM信号(PWM_P1，PWM_N1，PWM_P2，PWM_N2)与功率级主电路及其驱动模块相连接。死区时间控制模块主要功能是将提供给PMOS开关管和NMOS开关管开关的控制信号中加入死区时间来避免PMOS和NMOS开关管同时导通造成穿通。此模块通过对PWM_C信号加入死区时间获得四路PWM信号(PWM_P1，PWM_N1，PWM_P2，PWM_N2)，同时，死区时间的大小由V_sense信号调节，实现死区时间随负载电流减小而增大的自适应控制，以减少开关管的损耗。上述技术方案中，图2中功率级主电路及其驱动模块具体实现M_N1、M_P1、M_N2和M_P2四个开关MOS管非均匀调整如图3(a-d)所示。对于负载电流变化范围为(I_min，I_max)的四开关Buck-Boost变换器，将四个开关管M_N1、M_P1、M_N2和M_P2的尺寸进行分成不等长的m+1段。任何一段并联MOS管都有独立的与其尺寸相适应的驱动电路与其栅极相连接，用于驱动开关管正常工作。组成四个开关管M_N1、M_P1、M_N2和M_P2并联开关管的驱动电路输入端分别与上述死区时间控制模块输出信号PWM_N1，PWM_P1，PWM_N2，PWM_P2相连接。同时，每段并联MOS管的驱动电路都有使能端口，分别与栅宽数字选择码D₀～D_m-1，D_extra相连接。以图3(a)中开关管M_P1为例，它由M_P1(0)到M_P1(m)共m+1个不等长的MOS管并联而成，其中，一个MOS管M_P1(m)始终保持可工作状态，而其它MOS管M_P1(0)-M_P1(m-1)分别由所对应的数字码D₀-D_m-1控制其工作状态，数字码通过驱动使能来控制单个并联MOS管处在工作或关断状态。若某段MOS管对应的数字码D_i(i＝0，1，…，m-1))为“1”，表示相应的PWM信号可以通过驱动电路加载到此段功率MOS管上，即此段功率MOS管起有效的开关管作用；若数字码为“0”，则表示此段MOS管此时保持关断状态，不属于开关管的有效部分。开关管M_N1、M_N2控制和实现栅宽选择方式与M_P1管相同。而MOS管M_P2的情况稍有不同，除了上述m+1段并联MOS管，还需要附加仅用于工作在Buck模式的一个附加管，如图3(c)中的M_P2(extra)管。其连接方式与M_P2其它段并联管一样，只是驱动使能端与D_extra相连接。附加管的加入保证在Buck模式，即使输出电压较小的情况下，M_P2依然具有较低的导通电阻，而在Boost和Buck-Boost模式下，附加管完全关断，不参与M_p2的栅宽调整。As shown in Figure 2, the dead time control module is connected to the mode selection module through the mode selection signal S _Mode , connected to the PWM control module through the PWM_C signal, and connected to the on-chip current detection module through the V _sense signal, It is connected with the power stage main circuit and its driving module through four PWM signals (PWM_P1, PWM_N1, PWM_P2, PWM_N2). The main function of the dead time control module is to add a dead time to the control signal provided to the PMOS switch tube and the NMOS switch tube switch to avoid the PMOS and NMOS switch tubes being turned on at the same time to cause punch-through. This module obtains four PWM signals (PWM_P1, PWM_N1, PWM_P2, PWM_N2) by adding dead time to the PWM_C signal. At the same time, the size of the dead time is adjusted by the V _sense signal, so that the dead time increases as the load current decreases. Adaptive control to reduce the loss of the switching tube. In the above technical solution, the main circuit of the power stage and its driving module in Fig. 2 specifically realize the non-uniform adjustment of the four switch MOS transistors M _N1 , _MP1 , M _N2 and _MP2 , as shown in Fig. 3(ad). For a four-switch Buck-Boost converter with a load current variation range of (I _min , I _max ), divide the size of the four switch tubes M _N1 , M _P1 , M _N2 and M _P2 into m+1 segments of unequal length . Any section of parallel MOS transistors has an independent drive circuit that is suitable for its size and is connected to its gate to drive the switch tubes to work normally. The input terminals of the drive circuit forming the four switching tubes M _N1 , _MP1 , M _N2 and _MP2 connected in parallel are respectively connected to the output signals PWM_N1 , PWM_P1 , PWM_N2 and PWM_P2 of the dead time control module. At the same time, the driving circuit of each parallel MOS transistor has an enabling port, which is respectively connected to the gate width digital selection codes D ₀ -D _m-1 and D _extra . Taking the switching tube M _P1 in Figure 3(a) as an example, it is composed of m+1 MOS tubes of different lengths from M _P1 (0) to M _P1 (m) connected in parallel, wherein one MOS tube M _P1 ( m) Always maintain a working state, while other MOS tubes M _P1 (0)-M _P1 (m-1) are controlled by the corresponding digital codes D ₀ -D _m-1 respectively, and the digital codes are enabled through the drive To control a single parallel MOS tube in the working or off state. If the digital code D _i (i=0, 1, ..., m-1) corresponding to a certain section of MOS tube is "1", it means that the corresponding PWM signal can be loaded to this section of power MOS tube through the driving circuit, that is, The section power MOS tube acts as an effective switch tube; if the digital code is "0", it means that the section MOS tube remains off at this time and is not an effective part of the switch tube. The switching tubes M _N1 and M _N2 are controlled and realized in the same way as the M _P1 tube for gate width selection. The situation of MOS tube M _P2 is slightly different. In addition to the above-mentioned m+1 parallel MOS tubes, an additional tube that is only used to work in Buck mode is required, such as the M _P2 (extra) tube in Figure 3(c). . Its connection method is the same as that of other parallel tubes _{of MP2} , except that the drive enabling terminal is connected with D _extra . The addition of the additional tube ensures that in the Buck mode, even when the output voltage is small, _MP2 still has a low on-resistance, while in the Boost and Buck-Boost modes, the additional tube is completely turned off and does not participate in the _Mp2 Grid width adjustment.

一种前述的非均匀栅宽优化方法，基于上述四开关Buck-Boost变换器系统获得组成功率开关管M_N1、M_P1、M_N2和M_P2的并联开关管的数目m+1和各自尺寸W_M(0)-W_M(m)。由于M_N1、M_P1、M_N2和M_P2四个开关管设计完全一样，为了方便描述，这里用M管代替。设M管的总栅宽大小为W_total，由m+1个不等长的并联MOS管M(0)-M(m)组成(如图3所示)，对应尺寸分别为W_M(0)-W_M(m)。如前所述，控制M管调整栅宽大小的是数字码，从M(0)到M(m)随着负载电流依次关断，可以依次实现W_opt(0)到W_opt(m)共m+1种栅宽尺寸。设I_out(0)到I_out(m)为分别对应W_opt(0)到W_opt(m)不同尺寸达到最高效率的最优负载电流。A method for optimizing the aforementioned non-uniform gate width, based on the above-mentioned four-switch Buck- _Boost converter system _to obtain the number m+ ₁ and _the respective sizes W _M (0)-W _M (m). Since M _N1 , M _P1 , M _N2 and M _P2 are of the same design, for the convenience of description, M tubes are used here instead. Assuming that the total gate width of the M tube is W _total , it is composed of m+1 parallel MOS tubes M(0)-M(m) of unequal length (as shown in Figure 3), and the corresponding dimensions are W _M (0 )-W _M (m). As mentioned above, it is the digital code that controls the M tube to adjust the grid width. From M(0) to M(m), it is turned off sequentially with the load current, and the total of W _opt (0) to W _opt (m) can be realized sequentially. m+1 kinds of grid width sizes. Let I _out (0) to I _out (m) be the optimal load currents corresponding to different sizes of W _opt (0) to W _opt (m) respectively to achieve the highest efficiency.

基于如图2所示的整体四开关Buck-Boost变换器系统和所需负载电流变化范围(I_min，I_max)设计并联开关管数目m+1和尺寸大小W_M(0)-W_M(m)，从而实现非均匀栅宽调整的具体方法如下：Based on the overall four-switch Buck-Boost converter system shown in Figure 2 and the required load current variation range (I _min , I _max ), the number of parallel switch tubes m+1 and the size W _M (0)-W _M ( m), so as to realize the specific method of non-uniform grid width adjustment as follows:

1)按照上述连接方式搭建四开关Buck-Boost变换器系统框架如图2所示。1) Build the system framework of the four-switch Buck-Boost converter according to the above connection method, as shown in Figure 2.

2)根据所需最大负载电流I_max确定如图2中功率开关管M_N1、M_P1、M_N2和M_P2总尺寸。基于1)所搭建的系统，暂时关断延迟线ADC和开关管栅宽控制模块的功能，选择并确定I_out(0)≈0.6×I_max时对应的最优尺寸W_opt(0)，也就是开关MOS管的总尺寸W_total。2) Determine the overall size of the power switch tubes M _N1 , M _P1 , M _N2 and M _P2 as shown in Figure 2 according to the required maximum load current I _max . Based on the system built in 1), temporarily turn off the functions of the delay line ADC and the gate width control module of the switch tube, select and determine the optimal size W _opt (0) corresponding to I _out (0)≈0.6×I _max , and also It is the total size W _total of the switch MOS tube.

3)根据总尺寸W_total和所需最小负载电流I_min，采用栅宽变化值ΔW＝0.5×W_opt的方法来确定M(0)-M(m)的尺寸，来实现非均匀可变栅宽调整。确定开关管M(0)的尺寸的同时可以确定除去M(0)管外剩余的开关管的尺寸W_opt(1)，3) According to the total size W _total and the required minimum load current I _min , use the gate width change value ΔW=0.5×W _opt to determine the size of M(0)-M(m) to realize the non-uniform variable gate wide adjustment. While determining the size of the switching tube M (0), the size W _opt (1) of the remaining switching tube outside the M (0) tube can be determined,

依次按照上述的方法推导可以得到所需的并联各管的尺寸M(i-1)，i＝1，2，3，…，直到i＝m，使得I_out(m+1)＜I_min，确定并联开关管的个数m+1。According to the derivation of the above-mentioned method in turn, the required size M(i-1) of each parallel tube can be obtained, i=1, 2, 3, ..., until i=m, so that I _out (m+1)<I _min , Determine the number m+1 of parallel switch tubes.

${W W}_{M m} ((i i - - 11)) = = {W W}_{opt opt} ((i i)) = = \frac{{W W}_{opt opt} ((i i - - 11))}{22} = = \frac{{W W}_{opt opt} ((00))}{22^{i i}},, i i = = 1,2,3 1,2,3,, \cdot \cdot,, m m - - - - - - ((1313))$

W_opt(0)到W_opt(m)为变换器中可通过数字码实现的不同的栅宽尺寸，它们各自效率达到最优时，对应的负载电流I_out(0)到I_out(m)可以计算如下：W _opt (0) to W _opt (m) are the different grid width sizes that can be realized by digital codes in the converter. When their respective efficiency reaches the optimum, the corresponding load current I _out (0) to I _out (m) can be calculated as follows:

${I I}_{out out} ((n no)) = = \frac{{I I}_{out out} ((n no - - 11))}{22} = = \frac{{I I}_{out out} ((00))}{22^{m m}} - - - - - - ((1515))$

4)根据如图3所示结构和步骤3)中设计好的各个并联开关管的尺寸，确定非均匀变化的各个栅宽值对应的负载电流范围以使变换器的转换效率保持最优。关断如图2所示变换器系统中的延迟线ADC模块的功能，向开关管栅宽控制模块直接加入不同的数字码对应不同的栅宽，获得随负载电流变化的效率曲线。对于所有负载电流范围内，选取达到效率最高时的数字码，也就是确定了各个栅宽值对应的负载电流范围。4) According to the structure shown in FIG. 3 and the size of each parallel switch tube designed in step 3), determine the load current range corresponding to each grid width value that varies non-uniformly so as to keep the conversion efficiency of the converter optimal. Turn off the function of the delay line ADC module in the converter system as shown in Figure 2, and directly add different digital codes corresponding to different gate widths to the gate width control module of the switch tube to obtain the efficiency curve changing with the load current. For all load current ranges, select the digital code when the efficiency is the highest, that is, determine the load current range corresponding to each grid width value.

5)调节延迟线ADC输出数字码与检测电压V_sense的变化关系，使得ADC输出数字码与步骤4)中计算得到的负载电流范围对应。5) Adjust the change relationship between the delay line ADC output digital code and the detection voltage V _sense , so that the ADC output digital code corresponds to the load current range calculated in step 4).

6)完成整体电路设计。电路可以按照如图2中所示实现栅宽随负载电流非均匀变化的自适应调整。6) Complete the overall circuit design. The circuit can realize the self-adaptive adjustment of the grid width with the non-uniform change of the load current as shown in FIG. 2 .

上述发明方法本身不依赖于具体实现的工艺。本发明以一个输出负载电流范围(10mA，650mA)的DC-DC变换器为例，利用以上方法进行设计，得到需要并联的开关MOS管个数m+1为6，各管尺寸与总尺寸的比例(归一化等效栅宽)也可相应得到如表2。表2同时给出了最终得到的不同栅宽尺寸对应的栅宽选择数字码，以及各尺寸下对应的负载电流范围。其中，由于M_P2的附加管不参与M_p2的栅宽调整，因此不计入其总栅宽中。The above-mentioned inventive method itself does not depend on the specific realized process. The present invention takes a DC-DC converter with an output load current range (10mA, 650mA) as an example, uses the above method to design, and obtains that the number m+1 of switch MOS tubes that need to be connected in parallel is 6, and the size of each tube and the total size The ratio (normalized equivalent gate width) can also be correspondingly obtained as shown in Table 2. Table 2 also shows the finally obtained gate width selection digital codes corresponding to different gate width sizes, and the corresponding load current ranges under each size. Wherein, since the additional tube of M _P2 does not participate in the adjustment of the gate width of M _p2 , it is not counted in its total gate width.

表2不同负载电流范围内对应的栅宽选择数字码和归一化等效栅宽Table 2 Corresponding gate width selection digital code and normalized equivalent gate width in different load current ranges

本发明采用本发明设计的高频非均匀栅宽变化方法的Buck-Boost变换器，采用CSMC0.5μm CMOS工艺库设计，实现除无源滤波器件外的全电路集成，外接滤波电感为2.2μH，滤波电容为1μF。根据对输入输出电压的要求，变换器可以工作在Buck、Buck-Boost、Boost三种模式下，输入电压范围2.5V-4.2V，输出电压范围1.5V-5V，工作频率5MHz。在整个负载电流范围10mA-650mA内采用非均匀的栅宽调制方法，电路工作在Buck和Boost模式下仿真曲线如图4。图4(a)为Buck模式下转换效率随负载电流变化仿真曲线；图4(b)为Boost模式下转换效率随负载电流变化仿真曲线。可以看到变换器5MHz高频工作时，中等负载及重负载效率始终保持在90％以上，而轻载效率得到了大幅度的提高，尤其对于Boost变换，负载电流为10mA时效率可达到84％以上。The present invention adopts the Buck-Boost converter of the high-frequency non-uniform gate width variation method designed by the present invention, adopts the CSMC0.5μm CMOS process library design, realizes the whole circuit integration except the passive filter device, and the external filter inductance is 2.2μH, The filter capacitor is 1μF. According to the requirements for input and output voltage, the converter can work in three modes: Buck, Buck-Boost, and Boost, with an input voltage range of 2.5V-4.2V, an output voltage range of 1.5V-5V, and an operating frequency of 5MHz. In the entire load current range of 10mA-650mA, a non-uniform grid width modulation method is used. The simulation curves of the circuit working in Buck and Boost modes are shown in Figure 4. Figure 4(a) is the simulation curve of conversion efficiency changing with load current in Buck mode; Figure 4(b) is the simulation curve of conversion efficiency changing with load current in Boost mode. It can be seen that when the converter operates at a high frequency of 5MHz, the efficiency of medium load and heavy load is always above 90%, while the efficiency of light load has been greatly improved, especially for Boost conversion, the efficiency can reach 84% when the load current is 10mA above.

此发明通过对高频开关变换器的功耗分析，得出不同负载条件下，开关管栅宽调制的规律和方法，从而制定出完整的解决方案。实现了对轻载效率的显著提高。由于只是改变了开关管的栅宽，并不采取额外开关管工作频率的控制环节，从根本上消除了变频控制带来的不良后果。By analyzing the power consumption of the high-frequency switching converter, the invention obtains the law and method of the grid width modulation of the switching tube under different load conditions, thereby formulating a complete solution. A significant increase in light load efficiency is achieved. Because only the grid width of the switch tube is changed, and no additional control link of the working frequency of the switch tube is adopted, the adverse consequences brought by the frequency conversion control are fundamentally eliminated.

以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施方式仅限于此，对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单的推演或替换，都应当视为属于本发明由所提交的权利要求书确定专利保护范围。The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments. It cannot be determined that the specific embodiments of the present invention are limited thereto. Under the circumstances, some simple deduction or replacement can also be made, all of which should be regarded as belonging to the scope of patent protection determined by the submitted claims of the present invention.

Claims

1. A method for improving the light-load efficiency of integrated switching DC-DC converter non-uniform variation gate width, characterized in that, according to the following steps:

(a) Build a four-switch Buck-Boost converter system;

(b) Determine the total size of the power switch tubes M _N1 , M _P1 , M _N2 and M _P2 according to the required maximum load current I _max ; determine the corresponding optimal size W _opt (0 when I _out (0)≈0.6×I _max ), that is, the total size W _total of the switch MOS tube;

(c) According to the total size W _total and the required minimum load current I _min , use the method of non-uniform variable gate width to determine the number m+1 and the size W _M (0) to W of each parallel switch tube that constitutes the power switch tube _M (m);

(d) According to the size of each parallel switch tube designed in step c), determine the load current range corresponding to each grid width value of non-uniform change so that the conversion efficiency of the converter remains optimal; turn off the function of the delay line ADC , directly add different digital codes corresponding to different grid widths to the switch gate width control module, and obtain the efficiency curve changing with the load current; for all load current ranges, select the digital code when the efficiency is the highest, that is, determine The load current range corresponding to the grid width value;

(e) Adjust the relationship between the delay line ADC output digital code and the detection voltage V _sense , so that the ADC output digital code corresponds to the load current range calculated in step (d);

(f) Realize the self-adaptive adjustment of the gate width with the non-uniform change of the load current.

2. A kind of method for improving the light-load efficiency non-uniform change gate width of integrated switching DC-DC converter as claimed in claim 1, it is characterized in that, the structure of four switching converter systems in the described step a is as follows:

The wide load current range high-efficiency DC-DC converter includes: power stage main circuit and its drive module, PWM control module, mode selection module, on-chip current detection module, delay line ADC module, switch gate width control module and dead zone time control module;

The power stage main circuit and its driving module realize the power transmission function of different voltage conversion types of Buck, Boost and Buck-Boost; the power stage main circuit and its driving module are connected with other modules as follows: V _in and power input terminal V _out is connected to the output terminal of the power supply, GND is connected to the external ground; V _x and V _y are connected to the two ends of the external inductor L, and the V _x terminal is connected to the current detection module at the same time; the gate width digital selection code D ₀ ~ D _{m -1} , D _extra is connected to the gate width control module of the switching tube; it is connected to the dead-time control module through four PWM signals of PWM_P1, PWM_N1, PWM_P2 and PWM_N2, and the four internal M _N1 , M _N2 , _MP1 and _MP2 are used The basic connection method of the gate width adjustable switch MOS tube is as follows: the source and drain of M _P1 tube are respectively connected to V _in and V _x ports, the source and drain of M _N1 are connected to GND and V _x ports respectively, and the source and drain of M _P2 tube are connected to V in and V x ports respectively. _out and V _y ports, the source and drain of the M _N2 tube are respectively connected to the GND and V _y ports; the M _N1 and M _N2 are NMOS, and the M _P1 and M _P2 are PMOS. The basic control modes are divided into the following three types: if the switch M _N2 keeps off, _MP2 keeps on, M _N1 and M _P1 are controlled by PWM, and the converter works in Buck mode; if the switch M _N1 keeps off, _MP1 keeps on, M _N2 and _MP2 are controlled by PWM , the converter works in Boost mode; if the four switch MOS tubes are controlled by PWM signal at the same time, it works in Buck-Boost mode; because the size of the power switch MOS tube is large, each switch tube needs a step-by-step inverter chain as drive;

The input terminal of the PWM control module is connected to the output feedback signal b V _out , and the signal b V _out is obtained by dividing the output voltage of the converter through resistors R _b1 and R _b2 ; the output terminal is connected to the dead time control module through the PWM_C signal ;

The V _in port of the mode selection module is connected to the power supply input terminal, the V _out port is connected to the voltage output terminal of the converter, and is connected to the dead time control module and the switch tube gate width control module respectively through the S _Mode signal; the mode selection module is based on The comparison of the input voltage V _in and the output voltage V _out obtains the mode selection signal S _Mode to realize the selection of the system working mode;

The V _in port of the on-chip current detection module is connected to the input terminal of the power supply, the V _x port is connected to the main circuit of the power stage and its drive module, and is connected to the delay line ADC module and the dead-time control module through the V _sense signal; the signal V _{The sense} changes linearly with the load current I _out , so it can accurately reflect the change of the load; the V _sense signal is provided to the delay line ADC and the dead time control module at the same time;

The input port of the delay line ADC module is connected to the on-chip current detection module through the V _sense signal; the delay line ADC module converts the analog voltage signal V _sense into m-bit temperature digital codes Q ₀ ~ Q _m-1 , and passes the digital code Connected with the grid width control module of the switching tube;

The switching tube grid width control module is connected to the switching tube grid width control module through digital codes Q ₀ to Q _m-1 , connected to the mode selection module through the mode selection signal S _Mode , and connected to the switching tube grid width control module through the grid width digital selection code D ₀ ～D _m-1 , D _extra is connected with the power stage main circuit and its drive module;

The dead time control module is connected to the mode selection module through the mode selection signal S _Mode , connected to the PWM control module through the PWM_C signal, connected to the on-chip current detection module through the V _sense signal, through; PWM_P1, PWM_N1, The four PWM signals of PWM_P2 and PWM_N2 are connected with the main circuit of the power stage and its driving module;

The main circuit of the power stage and its drive module realize the non-uniform adjustment of four switch MOS transistors M _N1 , _MP1 , M _N2 and _MP2 through parallel connection of switch tubes of different sizes; for the load current variation range of (I _min , I _max ) In the four-switch Buck-Boost converter, the sizes of the four switching tubes M _N1 , _MP1 , M _N2 and _MP2 are divided into m+1 sections of unequal length through the non-uniform gate width optimization method; any section of parallel MOS tubes can be There is an independent drive circuit suitable for its size connected to its gate, and the drive switch tube is normally turned on and off; the input terminal of the drive circuit composed of four switch tubes M _N1 , _MP1 , M _N2 and _MP2 parallel switch tubes They are respectively connected to the output signals PWM_N1, PWM_P1, PWM_N2, and PWM_P2 of the above-mentioned dead-time control module; at the same time, the driving circuit of each parallel MOS transistor has an enable port, which is respectively connected to the gate width digital selection code D ₀ ~D _m-1 , D _extra is connected.

3. A kind of method for improving the light load efficiency of integrated switching DC-DC converter as claimed in claim 1, it is characterized in that, described step c refers to:

According to the total size W _total and the required minimum load current I _min , the gate width change value ΔW=0.5×W _opt is used to determine the size of each parallel switch tube M(0)-M(m) to achieve non-uniformity. variable grid width adjustment;

Determine the size W _opt (1) of the remaining switch tube outside the _M (0) tube while determining the size W M (0) of the switch tube M (0),

{W W}_{M m} ((00)) = = {W W}_{opt opt} ((11)) = = \frac{{W W}_{opt opt} ((00))}{22} - - - - - - ((1111));;

W _opt (1) is the load current I _out (1) at which its efficiency reaches its optimum value,

{I I}_{out out} ((11)) = = \frac{{I I}_{out out} ((00))}{22} - - - - - - ((1212));;

According to the derivation of the above-mentioned method in turn, the required size M(i-1) of each parallel tube can be obtained, i=1, 2, 3, ..., until i=m, so that I _out (m+1)<I _min , Determine the number m+1 of parallel switch tubes;

{W W}_{M m} ((i i - - 11)) = = {W W}_{opt opt} ((i i)) = = \frac{{W W}_{opt opt} ((i i - - 11))}{22} = = \frac{{W W}_{opt opt} ((00))}{22^{i i}},, i i = = 1,2,3 1,2,3,, \cdot &Center Dot;,, m m - - - - - - ((1313));;

And the remaining part is the size of the last switch tube M(m),

{W W}_{M m} ((m m)) = = {W W}_{opt opt} ((m m)) = = {W W}_{opt opt} ((00)) - - {Σ Σ}_{i i = = 11}^{m m - - 11} {W W}_{M m} ((i i)) = = \frac{{W W}_{opt opt} ((00))}{22^{m m}} - - - - - - ((1414));;

W _opt (0) to W _opt (m) are the different grid width sizes that can be realized by digital codes in the converter. When their respective efficiency reaches the optimum, the corresponding load current I _out (0) to I _out (m) can be calculated as follows:

{I I}_{out out} ((n no)) = = \frac{{I I}_{out out} ((n no - - 11))}{22} = = \frac{{I I}_{out out} ((00))}{22^{m m}} - - - - - - ((1515)) . .