CN102169888B - Strain geoi structure and forming method thereof - Google Patents

Abstract

The present invention proposes a strained GeOI structure, comprising: a silicon substrate with an oxide insulating layer on the surface; a Ge layer formed on the oxide insulating layer, wherein a Ge layer is formed between the oxide insulating layer There is a first passivation thin layer; a gate stack formed on the Ge layer, and a channel region under the gate stack and a drain region and a source region on both sides of the channel region; and covering the The SiN stress cap layer of the gate stack is used to strain the channel region. In the embodiment of the present invention, the passivation thin layer formed by strontium germanide or barium germanide belongs to semiconductor, and in the embodiment of the present invention, the interface state problem between the Ge material and the insulating oxide can be improved through the first passivation layer, thereby Reduce leakage and scattering at this interface. In addition, the SiN stress cap layer of the embodiment of the present invention can generate strain in the channel region, thereby improving device performance.

Description

Strained GeOI structure and its formation method

technical field

The invention relates to the technical field of semiconductor design and manufacture, in particular to a strained GeOI (Ge on insulator) structure and a forming method thereof.

Background technique

For a long time, the feature size of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been following the so-called Moore's law (Moore's law) to keep scaling down, and its working speed is getting faster and faster. However, for Si-based material itself As far as it is concerned, it is already close to the double limit of physics and technology. Therefore, various methods have been proposed in order to continuously improve the performance of MOSFET devices, and thus the development of MOSFET devices has entered a so-called post-Moore (More-Than-Moore) era. High-mobility channel engineering based on heterogeneous material structures, especially high-carrier mobility material systems such as Si-based Ge materials, is one of the effective technologies. For example, the direct bonding of Ge and Si sheet with SiO2 insulating layer to form GeOI structure is a Si-based Ge material with high hole mobility, which has a good application prospect.

In the existing GeOI structure, Ge is directly bonded to insulating oxides such as SiO ₂ , or GeO ₂ is formed on Ge and then bonded to silicon wafers. The disadvantage of the prior art is that if the Ge material is directly formed on the insulating oxide substrate in the GeOI technology, the contact interface between the Ge material and the insulating oxide is relatively poor, especially the interface state density is very high, thus It causes serious scattering and leakage, which ultimately affects the performance of the device. In addition, since the Ge layer is very thin, it is difficult for the Ge layer to be strained.

Contents of the invention

The purpose of the present invention is to solve at least one of the above-mentioned technical defects, especially the defect that the interface state between Ge and the oxide insulator in the current GeOI structure is very poor, and the defect that the Ge layer is difficult to form strain.

In order to achieve the above object, the present invention proposes a strained GeOI structure on the one hand, comprising: a silicon substrate with an oxide insulating layer on the surface; a Ge layer formed on the oxide insulating layer, wherein the Ge layer and A first passivation thin layer is formed between the oxide insulating layers; a gate stack is formed on the Ge layer, and a channel region and drains on both sides of the channel region are formed under the gate stack. region and source region; and a SiN stress cap layer covering the gate stack to strain the channel region.

In one embodiment of the present invention, the gate stack includes: a gate dielectric layer on the Ge layer; a gate electrode on the gate dielectric layer; The side walls on both sides of the electrode, wherein the height of the side walls is 0.5-0.8 times the height of the gate electrode.

In one embodiment of the present invention, the first passivation thin layer is a strontium germanide thin layer, a barium germanide thin layer, a GeSi passivation thin layer or a Si thin layer.

In one embodiment of the present invention, it also includes: a second passivation thin layer formed on the Ge layer, and the second passivation thin layer is a strontium germanide thin layer, a barium germanide thin layer or a GeSi Thin layer of passivation.

In an embodiment of the present invention, the oxide insulating layer and the Ge layer are connected by bonding.

Another aspect of the present invention also proposes a method for forming a strained GeOI structure, comprising the following steps: forming a Ge layer on a first substrate; processing the first surface of the Ge layer to form a first passivation thin film layer; turn the first substrate, the Ge layer, and the first passivation thin layer over and transfer them to a silicon substrate with an oxide insulating layer on the surface; remove the first substrate; form a A gate stack above the Ge layer, and form a channel region under the gate stack, and a drain region and a source region on both sides of the channel region; and form a gate stack covering the The SiN stress cap layer of the gate stack is used to strain the channel region.

In an embodiment of the present invention, the forming a gate stack on the Ge layer further includes: forming a gate dielectric layer on the Ge layer; forming a gate electrode on the gate dielectric layer; A spacer is formed on both sides of the dielectric layer and the gate electrode; the spacer is etched so that the height of the sidewall is 0.5-0.8 times the height of the gate electrode.

In one embodiment of the present invention, the first passivation thin layer is a strontium germanide thin layer, a barium germanide thin layer, a GeSi passivation thin layer or a Si thin layer.

In one embodiment of the present invention, after removing the first substrate, further comprising: processing the second surface of the Ge layer to form a second passivation thin layer, the second passivation thin layer It is a thin layer of strontium germanide, a thin layer of barium germanide or a thin passivation layer of GeSi.

In one embodiment of the present invention, after removing the first substrate, further comprising: performing silicide treatment on the second surface of the Ge layer to form a GeSi passivation thin layer.

In one embodiment of the present invention, the first passivation thin layer is connected to the oxide insulating layer by bonding.

In the embodiment of the present invention, the problem of the interface state between the Ge material and the insulating oxide can be improved through the first passivation layer, thereby reducing leakage and scattering at the interface. In a preferred embodiment of the present invention, the passivation thin layer formed by strontium germanide or barium germanide or GeSi belongs to semiconductor, so it can not only improve the interface state problem between the Ge material and the insulating oxide, but also reduce the leakage and leakage at the interface. scattering without unduly degrading the mobility properties of the Ge material. In addition, the SiN stress cap layer of the embodiment of the present invention can generate strain in the channel region, thereby improving device performance. In an effective embodiment of the present invention, when the height of the sidewall is 0.5-0.8 times the height of the gate electrode, the stress of the SiN stress cap layer can be more effectively transferred to the channel region, thereby more effectively improving device performance.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

Fig. 1 is the schematic diagram of the strained GeOI structure of the embodiment of the present invention;

2-6 are schematic diagrams of intermediate steps of a method for forming a strained GeOI structure according to an embodiment of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. For example, such that the first and second features may not be in direct contact.

As shown in FIG. 1 , it is a schematic diagram of a strained GeOI structure according to an embodiment of the present invention. The GeOI structure includes a silicon substrate 1100 with an oxide insulating layer 1200 on its surface and a Ge layer 1300 formed on the oxide insulating layer 1200, wherein a first passivation is formed between the Ge layer 1300 and the oxide insulating layer 1200 TLC 1400. In the embodiment of the present invention, the first thin passivation layer 1300 is strontium germanide _GeSrx or barium germanide _GeBax formed by treating the first surface of the Ge layer 1200 with strontium Sr or barium Ba. Of course, in other embodiments of the present invention, the first passivation thin layer 1400 may also be a GeSi passivation thin layer or a Si thin layer. In one embodiment of the present invention, the silicon substrate 1100 with an oxide insulating layer on its surface includes a Si substrate, and an SiO ₂ insulating layer formed on the Si substrate. Since the passivation thin layer formed by strontium germanide or barium germanide is a semiconductor, it can not only improve the interface state problem between the Ge material and the insulating oxide, reduce the leakage and scattering at the interface, but also not excessively reduce the Ge Material mobility properties. In the embodiment of the present invention, in order to generate a strained Ge channel device, the strained GeOI structure further includes forming a SiN stress cap layer 1900 covering the gate stack (gate dielectric layer 1600 and gate electrode 1700) on the gate stack so that The channel region is strained. In the embodiment of the present invention, the composition of N in the SiN stress cap layer 1900 can be adjusted to cause compressive strain or tensile strain in the channel region, thereby improving device performance.

In one embodiment of the present invention, the strained GeOI structure further includes a second thin passivation layer 1500 formed on the Ge layer. Wherein, similarly, the second passivation thin layer 1500 is strontium germanide or barium germanide formed by treating the second surface of the Ge layer 1400 with strontium Sr or barium Ba. Of course, in other embodiments of the present invention, the second passivation thin layer 1500 may also be formed in other ways, that is, the second passivation thin layer 1500 is GeSi.

In one embodiment of the present invention, the GeOI structure further includes a gate dielectric layer 1600 formed on the second passivation thin layer 1500, a gate electrode 1700 formed on the gate dielectric layer 1600, and a gate electrode 1700 formed on the Ge layer 1400 The source and drain 1800 among them.

As shown in FIGS. 2-6 , they are schematic diagrams of the intermediate steps of the method for forming the strained GeOI structure according to the embodiment of the present invention. The method includes the following steps:

Step S101, providing a first substrate 2000, wherein the first substrate 2000 is a Si substrate or a Ge substrate. Of course, other substrates may also be used in other embodiments of the present invention. In the embodiment of the present invention, the first substrate 2000 can be reused, thereby reducing the manufacturing cost.

Step S102 , forming a Ge layer 1300 on the first substrate 2000 , as shown in FIG. 2 .

Step S103, treating the first surface of the Ge layer 1300 with strontium Sr or barium Ba to form a first passivation thin layer 1400, the first passivation thin layer 1400 is strontium germanide or barium germanide, as shown in FIG. 3 Show. Of course, in other embodiments of the present invention, the first passivation thin layer 1400 can also be a GeSi passivation thin layer or a Si thin layer, for example, Si oxidizes the Ge layer 1300, or deposits a Si thin layer on the Ge layer 1300. layer.

In step S104 , the first substrate 2000 , the Ge layer 1300 and the first passivation thin layer 1400 are turned over and transferred to a silicon substrate 1100 with an oxide insulating layer 1200 on its surface, as shown in FIG. 4 . In one embodiment of the present invention, the first passivation thin layer 1300 is connected to the oxide insulating layer 1200 by bonding.

Step S105 , removing the first substrate 2000 , as shown in FIG. 5 .

Step S106, optionally, the second surface of the Ge layer 1400 is treated with strontium or barium to form a second passivation thin layer 1500, the second passivation thin layer 1500 is strontium germanide or barium germanide, as shown in the figure 6. Likewise, in other embodiments of the present invention, the second passivation thin layer 1500 may also be formed in other ways, that is, the second passivation thin layer 1500 is GeSi.

Step S107, forming a gate stack (i.e. gate dielectric layer 1600 and gate electrode 1700) on the second passivation thin layer 1500 and spacers on both sides of the gate stack, and forming a channel region under the gate stack, and Drain and source regions 1800 located on both sides of the channel region. . In the embodiment of the present invention, the formation of the gate stack and the source region and the drain region can be formed by either a gate-first process or a gate-last process.

In a preferred embodiment of the present invention, the sidewall can also be etched to a height of about 0.5-0.8 times the height of the gate electrode.

Step S108 , depositing a SiN layer and performing etching to form a SiN stress cap layer 1900 , as shown in FIG. 1 .

In the embodiment of the present invention, the problem of the interface state between the Ge material and the insulating oxide can be improved through the first passivation layer, thereby reducing leakage and scattering at the interface. In a preferred embodiment of the present invention, the passivation thin layer formed by strontium germanide or barium germanide belongs to semiconductor, so it can not only improve the interface state problem between Ge material and insulating oxide, but also reduce the leakage and scattering at the interface, In addition, the mobility performance of the Ge material will not be excessively reduced. In addition, the SiN stress cap layer of the embodiment of the present invention can generate strain in the channel region, thereby improving device performance. In an effective embodiment of the present invention, when the height of the sidewall is 0.5-0.8 times the height of the gate electrode, the stress of the SiN stress cap layer can be more effectively transferred to the channel region, thereby more effectively improving device performance.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications and substitutions can be made to these embodiments without departing from the principle and spirit of the present invention. and modifications, the scope of the invention is defined by the appended claims and their equivalents.

Claims (8)

1. A strained GeOI structure, characterized in that, comprising: A silicon substrate with an oxide insulating layer on the surface; a Ge layer formed on the oxide insulating layer, wherein a first passivation thin layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed over the Ge layer, and a channel region under the gate stack and drain and source regions formed on both sides of the channel region; and a SiN stress cap layer covering the gate stack to generate strain in the channel region, Wherein, the first passivation thin layer is a strontium germanide thin layer or a barium germanide thin layer. 2. The strained GeOI structure of claim 1, wherein the gate stack comprises: a gate dielectric layer located on the Ge layer; a gate electrode located on the gate dielectric layer; and The side walls located on both sides of the gate dielectric layer and the gate electrode, wherein the height of the side walls is 0.5-0.8 times the height of the gate electrode. 3. The strained GeOI structure according to claim 1, further comprising: A second passivation thin layer formed on the Ge layer, the second passivation thin layer is a strontium germanide thin layer, a barium germanide thin layer or a GeSi passivation thin layer. 4. The strained GeOI structure according to claim 1, wherein the oxide insulating layer and the Ge layer are connected by bonding. 5. A method for forming a strained GeOI structure, comprising the following steps: forming a Ge layer over the first substrate; treating the first surface of the Ge layer to form a first thin passivation layer; Turning over and transferring the first substrate, the Ge layer and the first passivation thin layer to a silicon substrate with an oxide insulating layer on the surface; removing the first substrate; forming a gate stack on the Ge layer, and forming a channel region under the gate stack, and a drain region and a source region on both sides of the channel region; and forming a SiN stress cap layer covering the gate stack on the gate stack to generate strain in the channel region, Wherein, the first passivation thin layer is a strontium germanide thin layer or a barium germanide thin layer. 6. The method for forming the strained GeOI structure according to claim 5, wherein said forming a gate stack on the Ge layer further comprises: forming a gate dielectric layer on the Ge layer; forming a gate electrode on the gate dielectric layer; forming spacers on both sides of the gate dielectric layer and the gate electrode; Etching the sidewalls so that the height of the sidewalls is 0.5-0.8 times the height of the gate electrode. 7. The method for forming the strained GeOI structure according to claim 5, further comprising: The second surface of the Ge layer is treated to form a second passivation thin layer, and the second passivation thin layer is a strontium germanide thin layer, a barium germanide thin layer or a GeSi passivation thin layer. 8. The method for forming the strained GeOI structure according to claim 5, wherein the first passivation thin layer is connected to the oxide insulating layer by bonding.

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