CN102169851B - Thin film transistor array substrate and manufacturing method thereof - Google Patents
Thin film transistor array substrate and manufacturing method thereof Download PDFInfo
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- CN102169851B CN102169851B CN 201110044472 CN201110044472A CN102169851B CN 102169851 B CN102169851 B CN 102169851B CN 201110044472 CN201110044472 CN 201110044472 CN 201110044472 A CN201110044472 A CN 201110044472A CN 102169851 B CN102169851 B CN 102169851B
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- 239000000758 substrate Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000003860 storage Methods 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims description 65
- 239000000463 material Substances 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 21
- 238000000059 patterning Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 15
- 230000002159 abnormal effect Effects 0.000 abstract 3
- 230000000712 assembly Effects 0.000 abstract 1
- 238000000429 assembly Methods 0.000 abstract 1
- 239000004973 liquid crystal related substance Substances 0.000 description 23
- 238000002360 preparation method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000012447 hatching Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
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- 239000011159 matrix material Substances 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- 238000004873 anchoring Methods 0.000 description 1
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- 230000003111 delayed effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
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Abstract
The invention relates to a thin film transistor array substrate, which comprises a base defined with a plurality of abnormal alignment regions, a plurality of normal alignment regions and an assembly region, a plurality of scanning lines, a plurality of data lines, a plurality of storage electrode lines and a plurality of switch assemblies which are arranged in the assembly region on the base, a plurality of alignment structures arranged in the abnormal alignment regions, and an alignment layer arranged on the substrate and the alignment structures. The alignment layer further comprises a plurality of first alignment grooves arranged in the abnormal alignment regions and covering the alignment structure, and a plurality of second alignment grooves arranged in the normal alignment regions; and the depth and the width of the second alignment grooves are equal to those of the first alignment grooves.
Description
Technical field
The invention relates to a kind of thin-film transistor array base-plate (thin film transistor array substrate, TFT array substrate) and preparation method thereof, refer to especially a kind ofly can effectively improve unusual thin-film transistor array base-plate of orientation and preparation method thereof.
Background technology
The LCD device is widely used in running gear such as mobile phone, business machine such as personal computer screen and mobile computer and household appliances such as LCD TV etc. because of advantages such as it is light, thin, low power consumptions.Known LCD panel is to comprise a thin-film transistor array base-plate, colored filter substrate (color filter substrate) and the liquid crystal layer that be arranged at thin-film transistor array base-plate and colored filter substrate between relative with thin-film transistor array base-plate.And thin-film transistor array base-plate is in the face of the surface of liquid crystal layer, and colored filter substrate is to be respectively arranged with a both alignment layers on the surface in the face of liquid crystal layer.The major function of both alignment layers is that the liquid crystal molecule in the liquid crystal layer is carried out orientation, makes liquid crystal molecule present specific arrangement between thin-film transistor array base-plate and colored filter substrate.
See also Fig. 1, Fig. 1 is a known twisted nematic (twisted nematic, TN) schematic diagram of the thin-film transistor array base-plate of type LCD display unit.As shown in Figure 1, known thin-film transistor array base-plate 100 comprises a substrate 101, and be the pixel region 108 that is laid with scan line (scan line) 102, data wire (data line) 104, storage electrode line (storage capacitor line) 106, defines by scan line 102 and data wire 104 in the substrate 101, and the switch module 110 that is positioned at each pixel region 108.Known thin-film transistor array base-plate 100 is after forming above-mentioned lead and switch module 110, can form an alignment materials layer (figure does not show) again.Subsequently, carry out friction (rubbing) orientation of contact, with in a plurality of grooves of alignment materials laminar surface formation rule arrangement by a tweed pair of rollers alignment materials layer.Above-mentioned groove is the grappling energy (anchoring energy) that can provide the liquid crystal molecule one in the liquid crystal layer to arrange along the groove direction, makes the arrangement of liquid crystal molecule have directivity.
Please continue to consult Fig. 1.Known when utilizing tweed to carry out friction matching, be to carry out orientation mostly along an alignment direction 120.For instance, the alignment direction 120 of the thin-film transistor array base-plate 100 of TN type LCD device is to have one 45 ° angle with scan line 102 or data wire 104.And behind friction matching, be on thin-film transistor array base-plate 100, to form the normal district 130 of a plurality of orientations.The normal district 130 of orientation mainly is formed in the pixel region 108, especially scan line 102, storage electrode line 106, data wire 104 and forward side (windward side) 102a, 106a, 104a and the 110a of switch module 110 in the face of alignment direction 120.Yet, because the scan line 102 on the thin-film transistor array base-plate 100, data wire 104, storage electrode line 106 are the surfaces that protrude from substrate 100 with switch module 110, therefore be very easy to the protrusion pattern place that crosses in these leads or assembly when carrying out friction matching, especially reverse side (leeward side) 102b, the 106b, 104b and the 110b place that are scan line 102, storage electrode line 106, data wire 104 and 110 pairs of alignment direction 120 of switch module can't produce the groove that the grappling energy can be provided, and have promptly produced the orientation exceptions area.As shown in Figure 1, producing orientation exceptions area 140 perpendicular to the reverse side 104b of first component direction 120a part, especially data wire 104 of alignment direction 120 and the reverse side 110b of switch module 110; In like manner also producing orientation exceptions area 140 perpendicular to the reverse side 102b of second component direction 120b part, the especially scan line 102 of alignment direction 120 and the reverse side 106b of storage electrode line 106.Briefly, when carrying out friction matching, every lead or assembly all can produce orientation exceptions area 140 to reverse side 102b, 104b, 106b and the 110b of alignment direction 120 on the thin-film transistor array base-plate 100.
As previously mentioned, the alignment materials layer within orientation exceptions area 140 can't produce the orientation groove by the friction matching of tweed roller, causes the liquid crystal molecule of liquid crystal layer to arrange along groove.Because Liquid Crystal Molecules Alignment are in disorder in the orientation exceptions area 140, so thin-film transistor array base-plate 100 forms the dark space when lighting, and understands light leak when closing.In addition, misarranged liquid crystal molecule is also delayed the rotation of the liquid crystal molecule in the normal district 130 of contiguous orientation in the orientation exceptions area 140, has prolonged the response time (response time) of LCD panel, and reduces the performance of LCD panel.For fear of this shortcoming, known technology once had the solution route that black matrix" (black matrix) is set in orientation exceptions area 140, yet this method is to have reduced aperture opening ratio significantly.
Summary of the invention
Therefore, the present invention provides a kind of thin-film transistor array base-plate that improves liquid crystal molecule random arrangement in the orientation exceptions area that friction matching produces and preparation method thereof in this.
According to claim provided by the present invention, a kind of manufacture method of thin-film transistor array base-plate is provided, this manufacture method includes provides a substrate, and be formed with in this substrate a plurality of scan lines, a plurality of data wires, a plurality of storage electrode lines, with a plurality of switch modules.The a plurality of orientations of definition are normal in this substrate subsequently distinguishes and a plurality of orientation exceptions area, wherein the normal district of these orientations is a side that is positioned at these scan lines, these data wires, these storage electrode lines and these switch modules, and these orientation exceptions area are the opposite sides that are positioned at these scan lines, these data wires, these storage electrode lines and these switch modules.Next in this substrate, form an insulating barrier and a transparency conducting layer in regular turn.This manufacture method also comprise to this insulating barrier and this transparency conducting layer wherein at least one carries out a patterning process, in these orientation exceptions area, to form a plurality of alignment structures respectively.After these alignment structures to be formed, in this substrate, form an alignment materials layer, and this alignment materials layer in these orientation exceptions area is to form a plurality of first orientation grooves along these alignment structures.Carry out a friction matching processing procedure at last, form a plurality of second orientation grooves on this alignment materials floor along an alignment direction in this orientation in the normal district.
According to claim provided by the present invention, a kind of thin-film transistor array base-plate also is provided, and this thin-film transistor array base-plate includes a definition the substrate in the normal district of a plurality of orientation exceptions area, a plurality of orientation and an assembly district, be arranged at a plurality of scan lines this suprabasil this assembly district in, a plurality of data wires, a plurality of storage electrode lines, be arranged at both alignment layers on this substrate and these alignment structures with a plurality of switch modules, a plurality of interior alignment structure, of these orientation exceptions area that is arranged at.This both alignment layers also comprises a plurality of first orientation grooves that are arranged in these orientation exceptions area and cover these alignment structures, and a plurality of second orientation groove that is arranged in the normal district of these orientations.One degree of depth of these second orientation grooves and a width are a degree of depth and width that equals these first orientation grooves.
According to thin-film transistor array base-plate provided by the present invention and preparation method thereof, in substrate, define a plurality of orientation exceptions area and orientation is normally distinguished according to alignment direction, and by patterning process in the orientation exceptions area insulating barrier or transparent electrode layer in form alignment structure.Therefore, when follow-up formation alignment materials layer, can obtain the first orientation groove and after the friction matching processing procedure along the surface of alignment structure, can in the normal district of orientation, form the second orientation groove, and the first orientation groove have the identical degree of depth and width with the second orientation groove.In other words, thin-film transistor array base-plate provided by the present invention and preparation method thereof is to overcome the friction matching processing procedure can't produce the orientation groove in the reverse side of alignment direction shortcoming, in substrate, form the required first orientation groove and the second orientation groove, with the grappling energy that provides liquid crystal molecule one to arrange along the groove direction.
Description of drawings
Fig. 1 is the schematic diagram of a known thin-film transistor array base-plate;
The schematic diagram of the manufacture method of the thin-film transistor array base-plate that Fig. 2 to Fig. 6 is provided for one first preferred embodiment of the present invention, wherein Fig. 2 is a top view of this preferred embodiment, and the generalized section that Fig. 3 to Fig. 6 is illustrated for the A-A ' hatching line along Fig. 2; And
The schematic diagram of the manufacture method of the thin-film transistor array base-plate that Fig. 7 to Figure 10 is provided for one second preferred embodiment of the present invention, wherein Fig. 7 is a top view of this preferred embodiment, and the generalized section that Fig. 8 to Figure 10 is illustrated for the B-B ' hatching line along Fig. 7.
Embodiment
In the middle of specification and aforesaid claim scope, used some vocabulary to censure specific assembly.The person with usual knowledge in their respective areas should understand, and same assembly may be called with different nouns by manufacturer.This specification and aforesaid claim scope are not used as distinguishing the mode of assembly with the difference of title, but the benchmark that is used as distinguishing with the difference of assembly on function.Be an open term mentioned " comprising " in the middle of specification and the aforesaid claim in the whole text, so should be construed to " comprise but be not limited to ".In addition, " electric connection " speech is to comprise any indirect means that are electrically connected that directly reach at this.Therefore, be electrically connected at one second device, then represent this first device can be directly connected in this second device, or be connected to this second device indirectly through other device or connection means if describe one first device in the literary composition.
See also Fig. 2 to Fig. 6, the schematic diagram of the manufacture method of the thin-film transistor array base-plate that Fig. 2 to Fig. 6 is provided for one first preferred embodiment of the present invention, wherein Fig. 2 is a top view of this preferred embodiment, and the generalized section that Fig. 3 to Fig. 6 is illustrated for the A-A ' hatching line along Fig. 2.As Fig. 2 and shown in Figure 3, this preferred embodiment at first provides a substrate 202, and be to be formed with thin-film transistor array base-plate 200 required a plurality of scan lines 210, a plurality of data wires 212, a plurality of storage electrode lines 214 and a plurality of switch module 216 in the substrate 202, as TFT switch module etc.Scan line 210 defines a plurality of pixel regions 218 with data wire 212 in substrate 202, a switch module 216 then is set respectively in each pixel region 218.In addition, in this preferred embodiment, any scan line 210, data wire 212, storage electrode line 214 and switch module 216 whereabouts are to be defined as an assembly district 204(to be shown in Fig. 3).
It should be noted that, because when making thin-film transistor array base-plate, it at the beginning of processing procedure the alignment direction 260 of known dawn of friction matching, therefore after forming scan line 210, data wire 212, storage electrode line 214 and switch module 216, can learn the relativeness of the alignment direction 260 of said modules position and friction matching.For instance, on the first component direction 260a perpendicular to alignment direction 260, data wire 212 is to have a data wire forward side (windward side) 212a and the reverse side of a data wire (leeward side) 212b, and switch module 216 then has forward side 216a of a switch module.In like manner on the second component direction 260b perpendicular to alignment direction 260, scan line 210 is to have the one scan line forward side 210a and the reverse side 210b of one scan line, storage electrode line 214 are to have a storage electrode line forward side 214a and the reverse side 214b switch module 216 of a storage electrode line then have forward side 216a of switch module.In other words, any lead in the assembly district 204 and assembly are that alignment direction 260 is obtained forward a side and a reverse side respectively.And the i.e. side forward of these in pixel region 218 of this preferred embodiment, for example scan line forward side 210a, storage electrode line forward side 214a, data wire forward side 212a, switch module forward side 216a define the normal district 206 of a plurality of orientations; And in these reverse sides, for example the reverse side 210b of scan line, the reverse side 214b of storage electrode line and the reverse side 212b of data wire define a plurality of orientation exceptions area 208.Briefly, this preferred embodiment is normally to distinguish 206 in scan line 210, data wire 212, storage electrode line 214 with the side definition orientation of switch module 216; And define orientation exceptions area 208 with the opposite side of switch module 216 in scan line 210, data wire 212, storage electrode line 214.
See also Fig. 2 and Fig. 3.After the making of finishing leads such as scan line 210, data wire 212, storage electrode line 214 and switch module 216 and assembly, in substrate 202, form an insulating barrier 230 that covers scan line 210, data wire 212, storage electrode line 214 and switch module 216.And after forming insulating barrier 230, tool is known usually that the knowledgeable should know and is carried out a patterning process in this technical field, is used to form in the insulating barrier 230 one and electrically connects the contact hole (figure does not show) of the drain electrode of switch module 216 for the later pixel electrode.It should be noted that in this preferred embodiment, is to utilize insulating barrier 230 surfaces of a gray-level mask in each orientation exceptions area 208 to form a plurality of alignment structures 232 respectively in this patterning process.It should be noted that in addition, the alignment direction 260 of known friction matching not only at the beginning of processing procedure, also know that simultaneously a predetermined gash depth of orientation groove is scheduled to groove width with one behind the friction matching, therefore when making alignment structure 232, a degree of depth of alignment structure 232 and a width are greater than predetermined gash depth and predetermined groove width.
See also Fig. 4.After forming alignment structure 232, form a transparency conducting layer (figure does not show) in each pixel region 218 in substrate 202 respectively, and see through another this transparency conducting layer of patterning process patterning, and in each pixel region 218, form a pixel electrode 240 respectively.It should be noted that pixel electrode 240 is to cover insulating barrier 230 in the normal district 206 of orientation and each alignment structure 232 in the orientation exceptions area 208.Therefore, pixel electrode 240 is that the surface along alignment structure 232 obtains a plurality of the 3rd orientation grooves 242 in orientation exceptions area 208, and a degree of depth of the 3rd orientation groove 242 and a width are less than the degree of depth and the width of alignment structure 232, but still greater than the predetermined gash depth and the predetermined groove width of orientation groove behind the friction matching owing to fill up effect.
See also Fig. 5.Next, on substrate 202 and alignment structure 232, form an alignment materials layer 250.It should be noted that the alignment materials layer 250 in the orientation exceptions area 208 is to form a plurality of first orientation grooves 252 along the 3rd orientation groove 242, in other words the first orientation groove 252 is directly to be formed on the 3rd orientation groove 242.Yet the alignment materials floor 250 in the normal district 206 of orientation this moment still has a flat surfaces.It should be noted that, one degree of depth of the first orientation groove 252 and a width be owing to fill up effect less than the degree of depth and the width of alignment structure 232 and the 3rd orientation groove 242, but the degree of depth of the first orientation groove 252 and width are predetermined gash depth and the predetermined groove widths that equals orientation groove behind the friction matching.
See also Fig. 2 and Fig. 6.After forming the alignment materials layer 250 and the first orientation groove 252, substrate 202 is carried out a friction matching processing procedure along alignment direction 260.As previously mentioned, owing to be covered with the clathrate pattern that crosses by scan line 210, data wire 212 and storage electrode line 214 on the thin-film transistor array base-plate 200, and scan line 210, data wire 212 are the surfaces that protrude from substrate 200 with storage electrode line 214, and the orientation instrument only can form a plurality of second orientation grooves 254 as a tweed roller when therefore carrying out friction matching in the normal district 206 of orientation.But in the reverse side 210b of scan line, the reverse side 212b of data wire, the reverse side 214b of storage electrode line, promptly the tweed roller can't produce the orientation groove in orientation exceptions area 208.Yet it should be noted that, because the existence of alignment structure 232 in the orientation exceptions area 208, alignment materials layer 250 does not need friction matching can obtain the first orientation groove 252, and the degree of depth of the first orientation groove 252 and width are the degree of depth and the width that equals the second orientation groove 254 that produces by the friction matching processing procedure.In other words, behind the friction matching processing procedure, this preferred embodiment obtains a both alignment layers 258, and both alignment layers 258 has the second orientation groove 254 in the normal district 206 of orientation; And in orientation exceptions area 208, have a plurality of first orientation grooves 252.
According to first preferred embodiment provided by the present invention, define a plurality of orientation exceptions area 208 and the normal district 206 of orientation according to alignment direction 260 in the pixel region 218 in substrate 202, and by forming width and the degree of depth in the insulating barrier 230 of patterning process in orientation exceptions area 208 all greater than the alignment structure 232 of predetermined gash depth with predetermined groove width, the therefore first orientation groove 252 that when follow-up formation alignment materials layer 250, can equal to be scheduled to groove width and predetermined gash depth along the surface acquisition degree of depth and the width of alignment structure 232.And after the friction matching processing procedure, can in the normal district 206 of orientation, form the second orientation groove 254 with predetermined groove width and predetermined gash depth.In sum, the manufacture method of the thin-film transistor array base-plate that this first preferred embodiment is provided provides a both alignment layers 258, and both alignment layers 258 has the first orientation groove 252 and the second orientation groove 254 of the rough same trench degree of depth and groove width respectively in the normal district 206 of orientation exceptions area 208 and orientation.In addition, because alignment structure 232 is to form in the micro-photographing process of making contact hole 220, so the method that this preferred embodiment provided does not increase the processing procedure number.In other words, the manufacture method of the thin-film transistor array base-plate that this first preferred embodiment is provided is successfully to overcome the friction matching processing procedure can't produce the orientation groove in the reverse side of alignment direction shortcoming, in pixel region 218, form the required width and the first orientation groove 252 and the second orientation groove 254 of deep equality, grappling energy to provide liquid crystal molecule one to arrange along the groove direction makes the arrangement of liquid crystal molecule have directivity.
Next see also Fig. 7 to Figure 10, the schematic diagram of the manufacture method of the thin-film transistor array base-plate that Fig. 7 to Figure 10 is provided for one second preferred embodiment of the present invention, wherein Fig. 7 is a top view of this preferred embodiment, and the generalized section that Fig. 8 to the 10 is illustrated for the B-B ' hatching line along Fig. 8.As Fig. 7 and shown in Figure 8, shown in, this preferred embodiment at first provides a substrate 302, in the substrate 302 is to be formed with thin-film transistor array base-plate 300 required a plurality of scan lines 310, a plurality of data wires 312, a plurality of storage electrode lines 314 and a plurality of switch module 316 as TFT switch module etc.And scan line 310 is to define a plurality of pixel regions 318 in substrate 302 with data wire 312.In addition, in this preferred embodiment, any scan line 310, data wire 312, storage electrode line 314 and switch module 316 whereabouts are to be defined as an assembly district 304(to be shown in Fig. 8).
As previously mentioned, when making thin-film transistor array base-plate 300, be to be an alignment direction 360 of known dawn of friction matching processing procedure at the beginning of processing procedure, therefore after forming scan line 310, data wire 312, storage electrode line 314 and switch module 316, can learn the relativeness of the alignment direction 360 of said modules position and friction matching.For instance, on the first component direction 360a perpendicular to alignment direction 360, data wire 312 is to have a data wire forward side 312a and the reverse side 312b of a data wire, and switch module 316 then has a switch module forward side 316a and the reverse side 316b of a switch module.In like manner on the second component direction 360b perpendicular to alignment direction 360, scan line 310 is to have the one scan line forward side 310a and the reverse side 310b of one scan line, storage electrode line 314 are to have a storage electrode line forward side 314a and the reverse side 314b switch module 316 of a storage electrode line then have switch module forward side 316a and the reverse side 316b of switch module.In other words, any lead in the assembly district 304 and assembly are that alignment direction 360 is obtained forward a side and a reverse side respectively.And the i.e. side forward of these in pixel region 318 of this preferred embodiment, for example scan line forward side 310a, storage electrode line forward side 314a, data wire forward side 312a, switch module forward side 316a define the normal district 306 of a plurality of orientations; And in these reverse sides, for example the reverse side 310b of scan line, the reverse side 314b of storage electrode line, the reverse side 312b of data wire and the reverse side 316b of switch module define a plurality of orientation exceptions area 308.Briefly, this preferred embodiment is normally to distinguish 306 in scan line 310, data wire 312, storage electrode line 314 with the side definition orientation of switch module 316; And define orientation exceptions area 308 with the opposite side of switch module 316 in scan line 310, data wire 312, storage electrode line 314.
See also Fig. 7 and Fig. 8.After the making of finishing leads such as scan line 310, data wire 312, storage electrode line 314 and switch module 316 and assembly, be in form an insulating barrier 330 in the substrate 302 in regular turn, in insulating barrier 330 in, form a contact hole (figure does not show), an and transparency conducting layer (scheming not show).As shown in Figure 8, after forming transparency conducting layer, be to carry out a patterning process patterned transparent conductive layer, and in each pixel region 318, form a pixel electrode 340 respectively.It should be noted that, in this preferred embodiment, be to utilize a gray-level mask in this patterning process, therefore not only in pixel region 318, form pixel electrode 340, the more important thing is and utilize the layer at transparent layer of this gray-level mask in each orientation exceptions area 304, promptly pixel electrode 340 surfaces form a plurality of alignment structures 342 respectively.It should be noted that, the alignment direction 360 of known friction matching not only at the beginning of processing procedure, also know that simultaneously a predetermined gash depth of orientation groove is scheduled to groove width with one behind the friction matching, therefore when making alignment structure 342, a degree of depth of alignment structure 342 and a width are greater than predetermined gash depth and predetermined groove width.
See also Fig. 9.After forming pixel electrode 340 and alignment structure 342, in substrate 302, form an alignment materials layer 350.It should be noted that the alignment materials layer 350 in the orientation exceptions area 308 is to form a plurality of first orientation grooves 352 along alignment structure 342, in other words the first orientation groove 352 is directly to be formed on the alignment structure 342.Yet the alignment materials floor 350 in the normal district 306 of orientation this moment still has a flat surfaces.It should be noted that, one degree of depth of the first orientation groove 352 and a width be owing to fill up effect less than the degree of depth and the width of alignment structure 342, but the degree of depth of the first orientation groove 352 and width are predetermined gash depth and the predetermined groove widths that equals orientation groove behind the friction matching.
See also Fig. 7 and Figure 10.After forming the alignment materials layer 350 and the first orientation groove 352, be that substrate 302 is carried out a friction matching processing procedure along alignment direction 360.As previously mentioned, owing to be to be covered with the clathrate pattern that crosses by scan line 310, data wire 312 and storage electrode line 314 on the thin-film transistor array base-plate 300, and scan line 310, data wire 312, storage electrode line 314 are the surfaces that protrude from substrate 300 with switch module 316, and the orientation instrument only can form a plurality of second orientation grooves 354 as a tweed roller when therefore carrying out friction matching in the normal district 306 of orientation.But in the reverse side 310b of scan line, the reverse side 312b of data wire, the reverse side 314b of storage electrode line and the reverse side 316b of switch module, promptly the tweed roller can't produce the orientation groove in orientation exceptions area 308.Yet it should be noted that, because the existence of alignment structure 342 in the orientation exceptions area 308, alignment materials layer 350 does not need friction matching promptly to obtain the first orientation groove 352, and the degree of depth of the first orientation groove 352 and width equal the degree of depth and the width of the second orientation groove 354 that produces by the friction matching processing procedure.In other words, behind the friction matching processing procedure, this preferred embodiment is to obtain a both alignment layers 358, and both alignment layers 358 has the second orientation groove 354 in the normal district 306 of orientation; And in orientation exceptions area 308, have a plurality of first orientation grooves 352.
According to second preferred embodiment provided by the present invention, be in the pixel region 318 of substrate 302, to go up according to alignment direction 360 to define a plurality of orientation exceptions area 308 and the normal district 306 of orientation, and by forming width and the degree of depth in the pixel electrode 340 of gray-level mask in orientation exceptions area 308 all greater than the alignment structure 342 of predetermined gash depth with predetermined groove width, the therefore first orientation groove 352 that when follow-up formation alignment materials layer 350, can equal to be scheduled to groove width and predetermined gash depth along the surface acquisition degree of depth and the width of alignment structure 342.And after the friction matching processing procedure, can in the normal district 306 of orientation, form the second orientation groove 354 with predetermined groove width and predetermined gash depth.In sum, the manufacture method of the thin-film transistor array base-plate that this second preferred embodiment is provided provides a both alignment layers 358, and both alignment layers 358 comprises the first orientation groove 352 and the second orientation groove 354 with the rough same trench degree of depth and groove width respectively in the normal district 306 of orientation exceptions area 308 and orientation.In addition, because alignment structure 342 is to form in the patterning process of making pixel electrode 340, so the method that this preferred embodiment provided does not increase the processing procedure number.In other words, the manufacture method of the thin-film transistor array base-plate that this second preferred embodiment is provided is successfully to overcome the friction matching processing procedure can't produce the orientation groove in the reverse side of alignment direction shortcoming, in pixel region 318, form the required width and the first orientation groove 352 and the second orientation groove 354 of deep equality, grappling energy to provide liquid crystal molecule one to arrange along the groove direction makes the arrangement of liquid crystal molecule have directivity.
In sum, according to thin-film transistor array base-plate provided by the present invention and preparation method thereof, be in substrate, to define a plurality of orientation exceptions area and orientation is normally distinguished in the opposition side of assembly and lead according to alignment direction, and by patterning process in the orientation exceptions area insulating barrier or pixel electrode layer in form alignment structure.Therefore, when follow-up formation alignment materials layer, can obtain the first orientation groove along the surface of alignment structure; And after the friction matching processing procedure, can form the second orientation groove in the normal district of orientation, and the first orientation groove has the identical degree of depth and width with the second orientation groove.And because alignment structure is to form simultaneously in the processing procedure that forms contact hole or pixel electrode, therefore manufacture method provided by the present invention does not increase the processing procedure number.In other words, thin-film transistor array base-plate provided by the present invention and preparation method thereof is to overcome the friction matching processing procedure can't produce the orientation groove in the reverse side of alignment direction shortcoming, in substrate, form required orientation groove, with the grappling energy that provides liquid crystal molecule one to arrange along the groove direction.Therefore, can avoid for hiding unusual orientation district black matrix" being set in the known technology, and the shortcoming that causes aperture opening ratio to reduce.In addition, the manufacture method of thin-film transistor array base-plate provided by the present invention is to be not limited to TN type liquid crystal indicator, also can be in order to make other type such as plane torsion (in-plane switching, IPS) type liquid crystal indicator.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (17)
1. the manufacture method of a thin-film transistor array base-plate is characterized in that, includes:
One substrate is provided, and forms a plurality of scan lines, a plurality of data wires, a plurality of storage electrode lines and a plurality of switch module in this substrate;
The normal district of a plurality of orientations of definition and a plurality of orientation exceptions area in this substrate, wherein the normal district of these orientations is a side that is positioned at these scan lines, these data wires, these storage electrode lines and these switch modules, and these orientation exceptions area are the opposite sides that are positioned at these scan lines, these data wires, these storage electrode lines and these switch modules;
In this substrate, form an insulating barrier and a transparency conducting layer in regular turn;
To this insulating barrier and this transparency conducting layer wherein at least one carries out a patterning process, in these orientation exceptions area, to form a plurality of alignment structures respectively;
In this substrate, form an alignment materials layer, and this alignment materials layer in these orientation exceptions area is to form a plurality of first orientation grooves along these alignment structures, and a degree of depth of these alignment structures and a width are greater than a degree of depth of these first orientation grooves and a width; And
Carry out a friction matching processing procedure, form a plurality of second orientation grooves on this alignment materials floor along an alignment direction in this orientation in the normal district, one degree of depth of these first orientation grooves and a width are a degree of depth and width that equals these second orientation grooves, and these first orientation grooves are identical with the alignment direction of these second orientation grooves.
2. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is characterized in that, this patterning process is to form these alignment structures in this insulating barrier in this orientation exceptions area.
3. the manufacture method of thin-film transistor array base-plate as claimed in claim 2, it is characterized in that, this transparency conducting layer is to cover this insulating barrier and these alignment structures, and this transparency conducting layer forms a plurality of the 3rd orientation grooves along these alignment structures in these orientation exceptions area.
4. the manufacture method of thin-film transistor array base-plate as claimed in claim 3 is characterized in that, these first orientation grooves are to be formed on these grade in an imperial examination three orientation grooves.
5. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is characterized in that, this patterning process is that this layer at transparent layer in this orientation exceptions area forms these alignment structures.
6. the manufacture method of thin-film transistor array base-plate as claimed in claim 5 is characterized in that, these first orientation grooves are directly to be formed on these alignment structures.
7. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is characterized in that, this patterning process also comprises and utilizes a gray-level mask, in order to form these alignment structures.
8. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, the normal district of these orientations be defined in respectively these scan lines to the one scan line of this alignment direction forward side, these data wires to a data wire of this alignment direction forward side, these storage electrode lines to a storage electrode line of this alignment direction forward side, with these switch modules to a switch module of this alignment direction side forward.
9. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, these orientation exceptions area be defined in respectively these scan lines to the reverse side of one scan line of this alignment direction, these data wires to the reverse side of a data wire of this alignment direction, these storage electrode lines to the reverse side of a storage electrode line of this alignment direction, with a switch module reverse side of these switch modules to this alignment direction.
10. a thin-film transistor array base-plate is characterized in that, includes:
One substrate, and definition has a plurality of orientation exceptions area, a normal district of a plurality of orientation and an assembly district in this substrate;
A plurality of scan lines, a plurality of data wires, a plurality of storage electrode lines, with a plurality of switch modules, be arranged in this suprabasil this assembly district, these scan lines and these data wires are to define a plurality of pixel regions;
One insulating barrier is arranged in this substrate, and covers these scan lines, these data wires, these storage electrode lines and these switch modules;
Plurality of pixel electrodes is arranged at respectively in these pixel regions, and covers this insulating barrier;
A plurality of alignment structures are arranged in these orientation exceptions area, and this insulating barrier comprises these alignment structures; And
One both alignment layers be arranged on this substrate and these alignment structures, and this both alignment layers also comprises:
A plurality of first orientation grooves are arranged in these orientation exceptions area, and cover these alignment structures; One degree of depth of these alignment structures and a width are greater than a degree of depth of these first orientation grooves and a width; And
A plurality of second orientation grooves, be arranged in the normal district of these orientations, and a degree of depth of these second orientation grooves and a width are a degree of depth and width that equals these first orientation grooves, and these first orientation grooves are identical with the alignment direction of these second orientation grooves.
11. thin-film transistor array base-plate as claimed in claim 10 is characterized in that, these pixel electrodes are to comprise a plurality of the 3rd orientation grooves respectively, cover these alignment structures respectively, and these first orientation grooves are to cover this grade in an imperial examination three orientation grooves respectively.
12. thin-film transistor array base-plate as claimed in claim 11 is characterized in that, a degree of depth of these grade in an imperial examination three orientation grooves and a width are this degree of depth and this width less than these alignment structures, but greater than this degree of depth and this width of these first orientation grooves.
13. a thin-film transistor array base-plate is characterized in that, includes:
One substrate, and definition has a plurality of orientation exceptions area, a normal district of a plurality of orientation and an assembly district in this substrate;
A plurality of scan lines, a plurality of data wires, a plurality of storage electrode lines, with a plurality of switch modules, be arranged in this suprabasil this assembly district, these scan lines and these data wires are to define a plurality of pixel regions;
One insulating barrier is arranged in this substrate, and covers these scan lines, these data wires, these storage electrode lines and these switch modules;
Plurality of pixel electrodes is arranged at respectively in these pixel regions, and covers this insulating barrier;
A plurality of alignment structures are arranged in these orientation exceptions area, and this pixel electrode comprises these alignment structures; And
One both alignment layers be arranged on this substrate and these alignment structures, and this both alignment layers also comprises:
A plurality of first orientation grooves are arranged in these orientation exceptions area, and cover these alignment structures; One degree of depth of these alignment structures and a width are greater than this degree of depth of these first orientation grooves and this width; And
A plurality of second orientation grooves, be arranged in the normal district of these orientations, and a degree of depth of these second orientation grooves and a width are a degree of depth and width that equals these first orientation grooves, and these first orientation grooves are identical with the alignment direction of these second orientation grooves.
14. thin-film transistor array base-plate as claimed in claim 13 is characterized in that, these first orientation grooves are directly to cover these alignment structures.
15. as claim 10 or 13 described thin-film transistor array base-plates, it is characterized in that, these scan lines also comprise respectively the one scan line forward side and the reverse side of one scan line, these data wires also comprise respectively a data wire forward side and the reverse side of a data wire, these storage electrode lines also comprise a storage electrode line forward side and the reverse side of a storage electrode line respectively, and this switch module also wraps and comprises a switch module forward side and the reverse side of a switch module respectively.
16. thin-film transistor array base-plate as claimed in claim 15 is characterized in that, the normal district of these orientations be defined in respectively these scan lines forward side, these data wires forward side, these storage electrode lines forward side, with these switch modules side forward.
17. thin-film transistor array base-plate as claimed in claim 15 is characterized in that, these orientation exceptions area be defined in respectively the reverse side of these scan lines, the reverse side of these data wires, the reverse side of these storage electrode lines, with the reverse side of these switch modules.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110044472 CN102169851B (en) | 2011-02-24 | 2011-02-24 | Thin film transistor array substrate and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201110044472 CN102169851B (en) | 2011-02-24 | 2011-02-24 | Thin film transistor array substrate and manufacturing method thereof |
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| CN102169851A CN102169851A (en) | 2011-08-31 |
| CN102169851B true CN102169851B (en) | 2013-07-24 |
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| KR101057851B1 (en) * | 2004-10-19 | 2011-08-19 | 엘지디스플레이 주식회사 | Manufacturing Method Of Liquid Crystal Display |
| CN101425482A (en) * | 2007-10-31 | 2009-05-06 | 中华映管股份有限公司 | Method for manufacturing active element array substrate and structure thereof |
| CN101561602B (en) * | 2008-04-15 | 2011-07-27 | 北京京东方光电科技有限公司 | Array substrate of liquid crystal display device |
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