CN102142279B - semiconductor storage device - Google Patents

Abstract

The present invention provides a semiconductor storage device, wherein the resolution for data readout does not reduce even in verification and a stable readout action can be performed even when the power supply voltage is reduced. The readout circuit (13) of the invention comprises: a current voltage transform circuit (20) for transforming cell current (Icell) of a memory cell (MC) into voltage data (Vdata), and a readout amplifier (30) for comparing the voltage data (Vdata) with a reference voltage (Vref). The current voltage transform circuit (20) is configured to comprise a variable load resistance connected with the memory cell (MC) through a bit line ( BLj). The variable load resistance is configured to comprise a P channel type MOS transistor (T11, T14, T17) used as a load resistance, and a P channel type MOS transistor (T13, T16, T19) forming a switch circuit.

Description

semiconductor storage device

technical field

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that performs readout of data stored in a memory cell by comparing a data voltage corresponding to a cell current of the memory cell with a given reference voltage device.

Background technique

In recent years, electrically programmable and erasable nonvolatile memory (EEPROM) has been widely used in electronic devices such as mobile phones and digital still cameras. EEPROMs are equipped with memory cells with floating gates. Then, two or more values of data are recorded in the memory cell according to whether or not charges are accumulated on the floating gate, between the source and drain according to the presence or absence of charges depending on the floating gate Changes in the current flowing to read data from the memory cell.

In this case, the readout circuit provided in the EEPORM performs a readout of the data stored in the memory cell by converting the cell current flowing in the memory cell into a data voltage and comparing the data voltage with a given reference voltage. Judgment of data ("0", "1").

FIG. 9 is a circuit diagram of a readout circuit of the above-mentioned EEPORM. This read circuit is composed of a current-voltage conversion circuit 1 (pre-sense amplifier) and a sense amplifier 2 (main sense amplifier). The current-voltage conversion circuit 1 is formed by applying a power supply voltage Vdd to the source, and a P-channel MOS transistor T6 whose gate and drain are commonly connected (diode-connected), and communicates with the memory through a bit line BL on the drain. Drain connection of cell MC. The cell current Icell of the memory cell MC flows to the bit line BL, and is converted into a data voltage Vdata by the current-voltage conversion circuit 1 .

The sense amplifier 2 is an ordinary differential amplifier that amplifies the difference between the data voltage Vdata and the reference voltage Vref. The sense amplifier 2 is composed of N-channel type MOS transistors T1, T2 forming a differential pair; P-channel type MOS transistors T3, T4 which are respectively connected in series with the MOS transistors T1, T2 and form a current mirror; An N-channel MOS transistor T5 connected to a common source of T2 is formed.

The power supply voltage Vdd is applied to the common source of the MOS transistors T3 and T4. The data voltage Vdata from the current-voltage conversion circuit 1 is applied to the gate of the MOS transistor T1. A reference voltage Vref is applied to the gate of the MOS transistor T2. A sense enable signal SEN is applied to the gate of the MOS transistor T5.

The operation of this readout circuit will be described below based on FIGS. 9 and 10 . In this case, the source line SL is grounded, and a read voltage is applied to the bit line BL. Then, if the voltage of a word line (WL) WL rises to a high level (for example, Vdd), a cell current Icell corresponding to data stored in the memory MC flows. Usually, the cell current Icell has a value on the order of 0 to several tens of μA. For the case where the memory cell MC is data "0" (writing state), the cell current Icell is a small value (a value close to the minimum value), and for the case where the memory cell MC is data "1" (erasing state), the cell current Icell The current Icell has a larger value (a value closer to the maximum value) than this. The current-voltage conversion circuit 1 converts the cell current Icell into voltage data Vdata.

Thereafter, when the sense enable signal SEN rises to a high level (for example, Vdd), the MOS transistor T5 is turned on, and the sense amplifier 2 becomes active. Thus, the sense amplifier 2 performs determination of the data ("0", "1") stored in the memory cell MC by comparing the voltage data Vdata with the reference voltage Vref.

FIG. 10 is a graph showing the relationship between voltage data Vdata, cell current Icell, and reference voltage Vref. The cell current Icell (=Iref1-3) corresponding to the intersection of the Vdata-Icell curve and the reference voltage Vref (=Vref1-3) is the cell current threshold. That is, if the cell current Icell of the memory cell MC is smaller than the set cell current threshold, the data is determined as "0", and if it is greater than the cell current threshold, the data is determined as "1".

In addition, the input operating voltage range (the gate voltage range of the MOS transistors T1 and T2 ) in which the sense amplifier 2 normally operates is the lower limit voltage Vmin to the upper limit voltage Vmax.

In this case, it is expressed as: Vmin=Vt(T1)+Vds(T5), Vmax=Vdd-Vds(T3)+Vt(T1). Vt(T1) is the threshold value of the MOS transistors T1, T2, Vds(T5) is the source-drain voltage of the MOS transistor T5, and Vds(T3) is the source-drain voltage of the MOS transistor T3 (voltage drop of the diode part).

Therefore, the reference voltage Vref at least needs to fall within the input operating voltage range. As shown in FIG. 10, in the case of normal reading, the cell current threshold is set to Iref1, and accordingly, the reference voltage Vref is set to Vref1 at or near the center of the input operating voltage range.

Generally, an EEPROM has a write data judgment function called verify. In the verification, there are two types of erasure verification (ERASE verification) and program verification. In the erasure verification, it is determined whether or not the data of the memory cell MC has been erased, that is, whether or not the data stored in the memory cell MC is 1 or not. In this case, the cell current threshold is set to a strict condition for data "1", that is, to Iref2 which is larger than Iref1. Along with this, the reference voltage Vref is changed to Vref2 which is lower than Vref1. This is to compensate for the operation of the EEPROM in consideration of the dispersion of the cell current Icell and the change with time.

On the other hand, in program verification, it is determined whether data "0" is correctly written in memory cell MC. In this case, the cell current threshold is set to a strict condition for data "0", that is, to Iref3 which is smaller than Iref1. Along with this, the reference voltage Vref is changed to Vref3 which is higher than Vref1.

Patent Document 1: Japanese Patent Laid-Open No. 2008-140431

Contents of the invention

As described above, in the conventional readout circuit, the reference voltage Vref is changed in order to change the cell current threshold value at the time of verification. Therefore, the program verify reference voltage Vref3 is close to the upper limit voltage Vmax of the input operating voltage range of the sense amplifier 2 , and the erase verify reference voltage Vref2 is close to the lower limit Vmin of the input operating voltage range. Due to the setting of the cell current threshold, it may happen that the reference voltages Vref2 and Vref3 during verification are not included in the input operating voltage range. As a result, the resolving power of data reading may decrease, or a reading malfunction may occur.

In particular, if the power supply voltage Vdd is lowered to about 1.8V, the input operating voltage range of the sense amplifier 2 becomes very narrow to about 0.8V-1.6V. This input operating voltage range will become increasingly difficult.

Therefore, the semiconductor memory device of the present invention has: a bit line; a memory cell connected to the bit line, capable of electrically writing and reading data, and causing a cell current corresponding to the data to be flowing on the bit line; a current-voltage conversion circuit connected to the memory cell via the bit line for converting the cell current flowing on the bit line into voltage data; and a sense amplifier which It is used to compare the voltage data with a reference voltage, wherein the current-voltage conversion circuit is configured to include: a variable load resistor connected to the memory cell via the bit line.

(invention effect)

According to the semiconductor memory device of the present invention, since the current-voltage conversion circuit is configured to include a variable resistor, when changing the threshold value of the cell current, by changing the resistance value of the variable resistor, approximately from the input of the sense amplifier It becomes unnecessary to change the reference voltage at the center of the operating voltage range. Accordingly, even at the time of verification, the resolution of data reading does not decrease.

In particular, even if the input operating voltage range of the sense amplifier is narrowed due to a decrease in the power supply voltage, a stable read operation can be performed.

Description of drawings

FIG. 1 is an overall schematic diagram of a semiconductor memory device according to a first embodiment of the present invention.

2 is a cross-sectional view of a memory cell of the semiconductor memory device according to the first embodiment of the present invention.

3 is a circuit diagram of a readout circuit of the semiconductor memory device according to the first embodiment of the present invention.

4 is a circuit diagram of another readout circuit of the semiconductor memory device according to the first embodiment of the present invention.

5 is an operation timing chart of the semiconductor memory device according to the first embodiment of the present invention.

6 is a diagram illustrating characteristics of a readout circuit of the semiconductor memory device according to the first embodiment of the present invention.

7 is a circuit diagram of a readout circuit of a semiconductor memory device according to a second embodiment of the present invention.

8 is a diagram illustrating characteristics of a readout circuit of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 9 is a circuit diagram of a readout circuit of a conventional semiconductor memory device.

FIG. 10 is a diagram for explaining a readout circuit of a conventional semiconductor memory device.

(Symbol Description)

10 memory area

11 column decoder

12 row decoder

13 readout circuit

14 write circuit

15 control circuit

20, 20A current voltage conversion circuit

30 sense amplifier

100 Semiconductor storage device

101 Semiconductor substrate

105 Gate insulating film

109 floating gate

109a Protrusion

110 Tunnel insulating film

112 Control grid

113 Drain

114 source

115 channel

Detailed ways

A semiconductor memory device 100 according to a first embodiment of the present invention will be described based on the drawings. According to this embodiment, the semiconductor memory device 100 will be described as a serial input/output type EEPROM.

(Overall configuration of semiconductor memory device)

FIG. 1 is a schematic diagram of a semiconductor memory device 100 . As shown in the figure, in the memory array region 10, a plurality of bit lines BL0 to BLn extend in the Y direction, and a plurality of word lines WL0 to WLm and a plurality of source lines SL0 to SLm extend in the X direction perpendicular to the Y direction. extend. A plurality of memory cells MC are provided corresponding to intersections of the plurality of bit lines BL0 to BLn and the plurality of word lines WL0 to WLm.

In addition, a column decoder 11 for selecting one bit line from a plurality of bit lines BL0 to BLn based on a column address signal, and a column decoder 11 for selecting a bit line from a plurality of word lines WL0 to WLm based on a row address signal are provided adjacent to the memory array area 10 . row decoder 12 for a word line. By asserting the column address signal and the row address signal, one memory cell MC is selected.

Furthermore, a readout circuit 13 for reading out data from a memory cell MC appearing in the bit line BLj selected by the column decoder 11 via the data line DL is provided. In this case, the readout circuit 13 performs data "0" by comparing the stabilized reference voltage Vref with the data voltage Vdata obtained by voltage-converting the cell current Icell flowing in the selected memory cell MC. , "1" judgment.

In addition, a write circuit 14 that writes data into the selected memory cell MC via the bit line BLj selected by the column decoder 11 is provided. In addition, a control circuit 15 is provided that controls each sequence of writing, reading, and erasing of the memory cells MC based on various control signals.

(Structure of memory unit)

A specific configuration example of the memory cell MC will be described with reference to FIG. 2 . This memory cell MC is a split gate type, and a channel 115 is formed between a drain 113 and a source 114 formed at a predetermined interval on the semiconductor substrate 101 . A floating gate 109 extending from a part of the channel 115 to a part of the source 114 through the gate insulating film 105 is formed. The upper portion and side portions of the floating gate 109 are covered with a tunnel insulating film 110 , and a control gate 112 extending over a part of the drain 113 is formed.

The drain 113 is connected to the corresponding bit line BL, the control gate 112 is connected to the corresponding word line WL, and the source 114 is connected to the corresponding source line SL.

Next, the operation of the split gate type memory cell MC will be described. First, when writing data "0", a high voltage (for example, 2V on the control gate 112 and 12V on the source region 114) is applied on the control gate 112 and the source 114, due to the current flowing in the channel The hot electrons flow in the channel 115 and inject hot electrons into the floating gate 109 to accumulate them.

In addition, when erasing the written data "0" (that is, when rewriting the data "0" to "1"), by grounding the drain 113 and the source 114 and applying a high voltage to the control gate 112 (for example, 15 V), and the electrons accumulated in the floating gate 109 are extracted to the control gate 112 as a Fowler-Nordheim tunneling current (hereinafter referred to as FN tunneling current). Since the protruding portion 109a is formed on the upper portion of the floating gate 109, the electric field is concentrated here, and the FN tunnel current can flow even at a relatively low voltage.

In addition, when data stored in memory cell MC is read, a predetermined voltage (for example, 3 V on control gate 112 and 1 V on drain 113 ) is applied to control gate 112 and drain 113 . Then, the cell current Icell flows between the source and the drain according to the charge amount of the electrons accumulated in the floating gate 109 . In the case of writing data "0", the threshold value of the memory cell MC becomes high, and the cell current Icell becomes small, while in the case of writing data "1" (when erasing), the threshold value of the memory cell MC becomes low, The cell current Icell becomes larger.

The readout circuit 13 determines whether the data stored in the memory cell MC is “0” or “1” by converting the cell current Icell into a data voltage Vdata and comparing the data voltage Vdata with a reference voltage Vref.

(Structure of readout circuit)

Next, the configuration of the readout circuit 13 that is a feature of the present invention will be described based on FIG. 3 . The read circuit 13 is configured to include a current-voltage conversion circuit 20 (pre-sense amplifier), a sense amplifier 30 (main sense amplifier), and an N-channel MOS transistor T20 for circuit interruption.

The current-voltage conversion circuit 20 is configured to include P-channel MOS transistors T11 , T14 , and T17 as load resistors, and P-channel MOS transistors T13 , T16 , and T19 constituting a switch circuit.

In this case, the power supply voltage Vdd is applied to the source of the MOS transistor T11. The MOS transistor T11 is connected to the voltage data line 21 via the MOS transistor T13. The gate of the MOS transistor T11 is connected to the voltage data line 21 . A load resistance selection signal LOADSEL0 is applied to the gate of the MOS transistor T13. When the load resistance selection signal LOADSEL0 is “1” (high level=Vdd), since the MOS transistor T13 is turned off, the MOS transistor T11 is disconnected from the voltage data line 21 . When the load resistance selection signal LOADSEL0 is “0” (low level=0V), since the MOS transistor T13 is turned on, the MOS transistor T11 is connected to the voltage data line 21 in a diode-connected manner.

Similarly, a power supply voltage Vdd is applied to the source of the MOS transistor T14. The MOS transistor T14 is connected to the voltage data line 21 via the MOS transistor T16. The gate of the MOS transistor T14 is connected to the voltage data line 21 . A load resistor selection signal LOADSEL1 is applied to the gate of the MOS transistor T16. When the load resistance selection signal LOADSEL1 is “1” (high level=Vdd), the MOS transistor T14 is disconnected from the voltage data line 21 . When the load resistance selection signal LOADSEL1 is “0” (low level=0V), the MOS transistor T14 is connected to the voltage data line 21 in a diode-connected manner.

In addition, the power supply voltage Vdd is similarly applied to the source of the MOS transistor T17. The MOS transistor T17 is connected to the voltage data line 21 via the MOS transistor T19. The gate of the MOS transistor T17 is connected to the voltage data line 21 . A load resistor selection signal LOADSEL2 is applied to the gate of the MOS transistor T19. When the load resistance selection signal LOADSEL2 is “1” (high level=Vdd), the MOS transistor T17 is disconnected from the voltage data line 21 . When the load resistance selection signal LOADSEL2 is “0” (low level=0V), the MOS transistor T17 is connected to the voltage data line 21 in a diode-connected manner.

That is, since the MOS transistors T11, T14, and T17 of the current-voltage conversion circuit 20 are connected to the voltage data line 21 according to the load resistance selection signal LOADSEL0-2, the current-voltage conversion circuit 20 becomes a variable load resistance. In order to increase the variable range of the load resistance, it is preferable to weight the ratio of the resistance values of the MOS transistors T11, T14, T17 such as 1:1/2:1/4.

The resistance values of the MOS transistors T11, T14, and T17 are inversely proportional to the ratio W/L of the channel width W to the channel length L. Assuming that the ratio of the channel width W to the channel length L of the MOS transistor T11 is W/L, it becomes 2W/L for the MOS transistor T14 and 4W/L for the MOS transistor T17. Therefore, the resistance value of the current-voltage conversion circuit 20 can be changed into seven types according to the load resistance selection signal LOADSEL0-2.

That is, the total channel widths of the MOS transistors T11 , T14 , and T17 in the current-voltage conversion circuit 20 are as shown in Table 1. For example, in the case of LOADSEL0-2=<0, 1, 1>, the total channel width is W and is the largest as a resistance value. On the other hand, in the case of LOADSEL0-2=<0, 0, 0>, the total channel width is 7W, and the resistance value is the smallest. Here, it is assumed that the resistance values of the MOS transistors T13 , T16 , and T19 are negligibly smaller than the resistance values of the corresponding MOS transistors T11 , T14 , and T17 .

Table 1

LOADSEL0-2 Total channel width <0, 1, 1> W <1, 0, 1> 2W <0, 0, 1> 3W <1, 1, 0> 4W <0, 1, 0> 5W <1,0,0> 6W <0,0,0> 7W

In addition, as shown in FIG. 4 , P-channel MOS transistors T12 , T15 , and T18 may be added to the circuit of FIG. 3 . In this case, the MOS transistor T12 is connected between the gate of the MOS transistor T11 and the voltage data line 21, and the load resistance selection signal LOADSEL0 is applied to the gate.

Likewise, the MOS transistor T15 is connected between the gate of the MOS transistor T14 and the voltage data line 21, and the load resistance selection signal LOADSEL1 is applied to the gate. Likewise, the MOS transistor T18 is connected between the gate of the MOS transistor T17 and the voltage data line 21, and the load resistance selection signal LOADSEL2 is applied to the gate. MOS transistors 12 , 15 , and 18 switch in the same manner as MOS transistors 13 , 16 , and 19 , respectively.

In this way, by providing the MOS transistor 12, when the MOS transistor 13 is turned off and the MOS transistor 11 is disconnected from the data line 21, the gate capacitance of the MOS transistor 11 is connected as the load capacitance of the bit line BLj, so that the memory cell MC can be prevented from being damaged. Data readout speed drops. That is, by turning off the MOS transistor 12, the gate capacity of the MOS transistor 11 can be electrically disconnected from the bit line BLj. The reason for providing the MOS transistors 15 and 18 is the same.

The MOS transistor T20 for circuit disconnection is connected between the voltage data line 21 and the data line DL, and a readout signal SEN is applied to the gate. The data line DL is connected to the selected bit line BLj via the column decoder in FIG. 1 . The selected memory cell MC is connected to the bit line BLj.

During the read operation of the read circuit 13 , the MOS transistor T20 is turned on when the read signal SEN rises to high level, thereby connecting the read circuit 13 to the data line DL. On the other hand, during the write operation of the write circuit 14, the read signal SEN is at low level. The MOS transistor T20 is in an off state, so that the readout circuit 13 is disconnected from the data line DL.

Thus, during the read operation of the read circuit 13, the MOS transistors T11, T14, and T17 are selectively connected as the load resistance of the memory cell MC via the data line DL and the bit line BLj according to the load resistance selection signal LOADSEL0-2. . Furthermore, the cell current Icell of the memory cell MC is converted into voltage data Vdata by the current-voltage conversion circuit 20 .

Since the sense amplifier 30 has the same configuration as the conventional sense amplifier 2, its detailed description is omitted, and a voltage is applied to the gate of the MOS transistor T1 as one of the differential pair via the voltage data line 21. The voltage data Vdata from the current-voltage conversion circuit 20 . The reference voltage Vref is applied to the gate of the other MOS transistor T2 of the differential pair. The output voltage Vout is obtained from the connection node of the MOS transistors T2, T4. That is, when Vdata>Vref, the output voltage Vout is at a high level, and when Vdata<Vref, the output voltage Vout is at a low level.

(Operation of readout circuit)

Next, an example of the operation of the readout circuit 13 will be described based on FIGS. 5 and 6 .

First, if the read command is determined, based on the read command, the load resistance selection signals LOADSEL0-2 are fixed. Thereafter, when the row address signal and the column address signal are determined, the address selected by the row address decoder 12 and the column address decoder 11 is determined. That is, the bit line BLj is connected to the data line DL, and the word line WLi is set to a high level (read voltage level).

Next, when the read signal SEN rises to high level, the current-to-voltage conversion circuit 20 of the read circuit 13 is connected to the data line DL, and the sense amplifier 30 becomes active because the MOS transistor T5 is turned on. Sense amplifier 30 compares reference voltage Vref with voltage data Vdata from current-voltage conversion circuit 20 to determine whether the data stored in memory cell MC is “0” or “1”.

FIG. 6 is a graph showing the relationship of voltage data Vdata, cell current Icell, and reference voltage Vref. The three Vdata-Icell curves (i), (ii), and (iii) correspond to the resistance values (small resistance, medium resistance, and large resistance) of the current-voltage conversion circuit 20 . The cell current Icell corresponding to the intersection of the three Vdata-Icell curves (i), (ii), (iii) and the reference voltage Vref is the threshold current Iref1 , Iref2 , Iref3 .

The Vdata-Icell curve (i) is a curve corresponding to the erase verification for judging whether the data stored in the memory cell MC is "1", and the cell current threshold is set as a strict condition for the data "1", That is, Iref2 is set to be larger than Iref1. Accordingly, the resistance value of the current-voltage conversion circuit 20 is set to be "small". In this case, the load resistance selection signals LOADSEL0-2 are set to such as <0, 0, 0> of Table 1, and the total channel width is 7W. Then, if the cell current Icell of the memory cell MC is smaller than the set cell current threshold Iref2, the data is determined to be "0" because Vdata>Vref. If it is greater than (Vout=H) the cell current threshold Iref2, the data is determined to be "1" because Vdata<Vref. (Vout=L)

The Vdata-Icell curve (ii) is a curve for normal readout, and the cell current threshold is set to Iref1. The resistance value of the current-voltage conversion circuit 20 is set to "medium". In this case, the load resistance selection signals LOADSEL0-2 are set such as <0, 0, 1> of Table 1, and the total channel width is 3W. Then, if the cell current Icell of the memory cell MC is smaller than the set cell current threshold Iref1, the data is determined to be "0". If it is larger than the cell current threshold Iref1, the data is determined to be "1".

The Vdata-Icell curve (iii) is a curve corresponding to program verification for judging whether or not data "0" is correctly written in memory cell MC, and the cell current threshold is set to be strict with respect to data "0". The condition, namely, is set to Iref3 which is smaller than Iref1. In this case, the load resistance selection signals LOADSEL0-2 are set such as <1, 0, 1> of Table 1, and the total channel width is 2W. Then, if the cell current Icell of the memory cell MC is smaller than the set cell current threshold Iref3, the data is determined to be "0". If it is larger than the cell current threshold value Iref3, the data is judged as "1".

In addition, the input operating voltage range (the gate voltage range of the MOS transistors T1 and T2 ) in which the sense amplifier 30 normally operates is the lower limit voltage Vmin to the upper limit voltage Vmax as described above. In this case, the reference voltage Vref is set at the center of the input operating voltage range or near the center.

Thus, according to the present embodiment, when changing the cell current threshold value during verification, the resistance value of the current-voltage conversion circuit 20 is changed instead of changing the reference voltage Vref as before. Accordingly, the reference voltage Vref can be included in the input operating voltage range in which the sense amplifier 2 normally operates, and the resolution of data read is not lowered even during verification. In particular, even if the input operating voltage range of the sense amplifier 30 is narrowed due to a drop in the power supply voltage Vdd, a stable read operation can be performed.

Next, a semiconductor memory device 100 according to a second embodiment of the present invention will be described based on the drawings. The configuration of the current-voltage conversion circuit 20A of the readout circuit 13 of the semiconductor memory device 100 is different from that of the first embodiment, but the other configurations are the same.

FIG. 7 is a circuit diagram of the readout circuit 13 . This current-voltage conversion circuit 20A is configured to include resistors R0 , R1 , and R2 as load resistors, analog switches ASW0 , ASW1 , and ASW2 constituting a switching circuit, and inverters INV0 , INV1 , and INV2 . The other configurations of the readout circuit 13 are the same as those of the first embodiment, so descriptions thereof are omitted.

Resistors R0 , R1 , and R2 are formed of resistive elements (diffusion resistors other than transistors) that have good linearity to voltage application, and are connected to voltage data line 21 via analog switches ASW0 , ASW1 , and ASW2 , respectively. These analog switches ASW0 to ASW2 are configured by connecting P-channel MOS transistors and N-channel MOS transistors in parallel, and have excellent linearity with respect to the voltage of the voltage data line 21 .

The load resistance selection signal LOADSEL0 is applied to the gate of the N-channel MOS transistor of the analog switch ASW0, and the load resistance selection signal LOADSEL0 inverted by the inverter INV0 is applied to the gate of the P-channel MOS transistor. Inverts the load resistor selection signal *LOADSEL0.

Similarly, the load resistance selection signal LOADSEL1 is applied to the gate of the N-channel MOS transistor of the analog switch ASW1, and the load resistance selection signal LOADSEL1 inverted by the inverter INV1 is applied to the gate of the P-channel MOS transistor. Inverted load resistor selection signal *LOADSEL1 after turn.

Similarly, the load resistance selection signal LOADSEL2 is applied to the gate of the N-channel MOS transistor of the analog switch ASW2, and the load resistance selection signal LOADSEL2 inverted by the inverter INV2 is applied to the gate of the P-channel MOS transistor. Inverted load resistor selection signal *LOADSEL2 after turn.

That is, since the resistors R0, R1, and R2 of the current-voltage conversion circuit 20A are connected to the voltage data line 21 according to the load resistance selection signal LOADSEL0-2, the current-voltage conversion circuit 20A becomes a variable load resistance. In order to increase the variable range of the load resistance, it is preferable to weight the ratio of the resistance values of the resistors R0, R1, R2 such as 1:1/2:1/4. That is, assuming that the resistance value of the resistor R0 is R, the resistance value of the resistor R1 is 1/2·R, and the resistance value of the resistor R2 is 1/4·R.

Therefore, the resistance value of the current-voltage conversion circuit 20A can be changed into seven types according to the load resistance selection signal LOADSEL0-2 as shown in Table 2. Here, it is assumed that the on-resistance values of the analog switches ASW0 , ASW1 , and ASW2 are negligibly smaller than the resistance values of the corresponding resistors R0 , R1 , and R2 .

Table 2

LOADSEL0-2 resistance <1,0,0> R <0, 1, 0> R/2 <1, 1, 0> R/3 <0, 0, 1> R/4 <1, 0, 1> R/5 <0, 1, 1> R/6 <1, 1, 1> R/7

FIG. 8 is a graph showing the relationship of voltage data Vdata, cell current Icell, and reference voltage Vref. In this case, as in the first embodiment, the three Vdata-Icell curves (iv), (v), and (vi) correspond to the resistance values (small resistance, medium resistance, and large resistance) of the current-voltage conversion circuit 20A. Since the load resistors R0, R1, and R2 are composed of resistive elements with good linearity, the three Vdata-Icell curves (iv), (v), and (vi) can be approximated by straight lines.

The cell current Icell corresponding to the intersection of the three Vdata-Icell curves (iv), (v), (vi) and the reference voltage Vref is the threshold current Iref1 , Iref2 , Iref3 .

The Vdata-Icell curve (iv) is a curve corresponding to the erase verification for judging whether the data stored in the memory cell MC is "1", and the cell current threshold is set as a strict condition for the data "1", That is, Iref2 is set to be larger than Iref1. Accordingly, the resistance value of the current-voltage conversion circuit 20A is set to be "small". In this case, the load resistance selection signals LOADSEL0-2 are set to <1, 1, 1> such as Table 2, and the resistance value is 1/7·R. Then, if the cell current Icell of the memory cell MC is smaller than the set cell current threshold Iref2, the data is determined to be "0" because Vdata>Vref. If it is larger than the cell current threshold Iref2, the data is determined to be "1" because Vdata<Vref.

The Vdata-Icell curve (v) is a curve for normal readout, and the cell current threshold is set to Iref1. The resistance value of the current-voltage conversion circuit 20A is set to "medium". In this case, the load resistance selection signals LOADSEL0-2 are set to <1, 1, 0> such as Table 2, and the resistance value is 1/3·R. Then, if the cell current Icell of the memory cell MC is smaller than the set cell current threshold Iref1, the data is determined to be "0". If it is larger than the cell current threshold Iref1, the data is determined to be "1".

The Vdata-Icell curve (vi) is a curve corresponding to program verification for judging whether or not data "0" is correctly written in memory cell MC, and the cell current threshold is set to be strict with respect to data "0". The condition, that is, Iref3 is set to be smaller than Iref1. The resistance value of the current-voltage conversion circuit 20A is set to "large". In this case, the load resistance selection signals LOADSEL0-2 are set to <0, 1, 0> such as Table 2, and the resistance value is 1/2·R.

Then, if the cell current Icell of the memory cell MC is smaller than the set cell current threshold Iref3, the data is determined to be "0". If it is larger than the cell current threshold value Iref3, the data is judged as "1".

In addition, the input operating voltage range (the gate voltage range of the MOS transistors T1 and T2 ) in which the sense amplifier 30 normally operates is the lower limit voltage Vmin to the upper limit voltage Vmax as described above. In this case, the reference voltage Vref is set at the center of the input operating voltage range or near the center.

Thus, according to the present embodiment, similar to the first embodiment, it is possible to obtain the effect that the resolution of data read is not lowered even during verification. In addition, according to this embodiment, since the linearity of the Vdata-Icell curve is excellent, the inclination of the Vdata-Icell curve near the cell current threshold value Iref1-3 becomes larger than that of the first embodiment. That is, for a change in the cell current Icell in this region, a change in the data voltage Vdata becomes large. Thereby, there is an advantage that the ability to resolve the cell current Icell in the vicinity thereof is improved.

In addition, this invention is not limited to the said embodiment, Needless to say, it can change in the range which does not deviate from the point. For example, the number of MOS transistors (MOS transistor T11, etc.) serving as load resistors of the current-voltage conversion circuit 20 and the number of load resistors (resistors R0, etc.) of the current-voltage conversion circuit 20A are not limited to three, and can be appropriately changed.

In addition, in the first and second embodiments, the serial input-output type EEPROM was described as an example, but since the present invention is characterized by the readout circuit 13, it can be widely applied to parallel input-output type EEPROMs, equipped with A memory having memory cells that can write and read data electrically.

Claims (3)

1. a semiconductor storage, is characterized in that having:

Bit line;

Memory cell, it is connected with described bit line, can carry out writing and reading of data in electric mode, and the cell current corresponding with these data flowed on described bit line;

Current-voltage conversion circuit, it is connected with described memory cell via described bit line, for the described cell current flowing on described bit line is transformed to voltage data; And

Sensor amplifier, it is for described voltage data and reference voltage are compared,

And described current-voltage conversion circuit is configured to and comprises the variable load resistance being connected with described memory cell via described bit line,

Described variable load resistance has multiple MOS transistor and the on-off circuit for memory cell described in each transistor AND gate of described multiple MOS transistor is optionally connected,

Wherein, described on-off circuit have be connected to the first on-off element between described bit line and the drain electrode of described MOS transistor and be connected to described bit line and the grid of described MOS transistor between second switch element.

2. semiconductor storage according to claim 1, is characterized in that,

Described reference voltage is set near the center or this center of input action voltage range of described sensor amplifier.

3. semiconductor storage according to claim 1, is characterized in that,

In the time of common reading, the resistance value of described variable load resistance is set as to the first resistance value, and in the time determining whether that the checking that has normally write data in described memory cell is read, the resistance value of described variable load resistance is set as to second resistance value different from described the first resistance value.

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