CN102074541B - 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法 - Google Patents
一种无载体无引脚栅格阵列ic芯片封装件及其生产方法 Download PDFInfo
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000003292 glue Substances 0.000 claims abstract description 40
- 239000011159 matrix material Substances 0.000 claims abstract description 6
- 239000012528 membrane Substances 0.000 claims abstract description 4
- 238000003466 welding Methods 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 20
- 238000001746 injection moulding Methods 0.000 claims description 14
- 230000009977 dual effect Effects 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 238000005520 cutting process Methods 0.000 claims description 9
- 238000005452 bending Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 238000012856 packing Methods 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000001035 drying Methods 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 claims description 2
- 230000011664 signaling Effects 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract 2
- 229910052802 copper Inorganic materials 0.000 abstract 2
- 239000010949 copper Substances 0.000 abstract 2
- 238000005476 soldering Methods 0.000 abstract 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 abstract 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 229920003192 poly(bis maleimide) Polymers 0.000 abstract 1
- 238000002360 preparation method Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 33
- 239000005022 packaging material Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 210000000481 breast Anatomy 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
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- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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Abstract
一种无载体栅格阵列IC芯片封装件及其制备方法,包括内引脚、IC芯片、焊盘、键合线及塑封体,所述内引脚在封装件正面设为多排矩阵式,背面为外露的多排近似正方形的圆形镀金触点;所述内引脚上面为IC芯片,内引脚和IC芯片之间由胶膜片粘接,IC芯片上的焊盘通过键合线与内引脚相连,所述塑封体包围胶膜片、IC芯片、键合线及内引脚边缘,构成电路整体。本发明采用近似正方形的圆球状阵列触点,结构简单灵活,散热效果好。铜引线框架(L/F)成品率高并降低了材料成本。采用引线框架(L/F)代替陶瓷基板、PCB基板或BT基板,省去了复杂的版图设计,设计制造周期较短,加快了试制生产进程,促使产品提早上市,取得市场先机。
Description
发明内容
本发明采用的技术方案如下:
一种无载体栅格阵列IC芯片封装件,包括内引脚、IC芯片、焊盘、键合线及塑封体,其特征在于所述内引脚在封装件正面设为多排矩阵式,背面为外露的多排近似正方形的圆形镀金触点;所述多排矩阵式或多排近似正方形的圆形镀金触点的同时为三排×三列或者四排×四列;所述内引脚上面为原IC芯片,内引脚和原IC芯片之间由胶膜片粘接,原 IC芯片上的焊盘通过键合线与内引脚的镀金触点相连,所述塑封体包围胶膜片、原IC芯片、键合线及内引脚边缘,构成封装件的电路整体。
所述多排矩阵式内引脚设为A、B、C三排引脚,其中A排设有3个内引脚,分别为A1、A2、A3,B排左边2个内引脚B1、B2连在一起,右边设1个单独的内引脚B3,C排设有3个单独的内引脚C1、C2、C3。
所述外露的多排近似正方形的圆形镀金触点为所述封装件背面a排引脚上设有3个大小相同近似正方形的圆形独立引脚触点a1、a2、a3;b排也设有3个近似正方形的圆形独立触点b1、b2、b3;其中b2的左上角成0.10×45°斜角,其斜角正对的a排触点为该电路Pin 1脚;c排也设有3个大小相同的近似正方形圆形独立触点c1、c2、c3。
所述封装件有单芯片封装形式;
所述封装件有多芯片封装形式;
所述封装件设有双芯片堆叠封装形式,在原IC芯片上端设有另一IC芯片,原IC芯片和另一IC芯片之间设有胶膜片粘接,原IC芯片上的焊盘通过键合线与内引脚的镀金触点或原IC芯片相连,原IC芯片上的另一焊盘再利用另一键合线与其上端的另一IC芯片相连,构成电路的电流和信号通道,塑封体包围胶膜片、IC芯片、键合线、内引脚边缘,构成电路整体。
所述单芯片封装件的生产方法包括晶圆减薄、划片、上芯、压焊、塑封、后固化、打印、切割分离、检验、包装、入库,其中后固化、打印、包装、入库同普通QFN生产,其余的操作按下述工艺步骤进行:
减薄、划片
先将晶圆减薄到150μm~200μm,清洗干净并烘干后,背面贴上胶膜片,去掉减薄胶膜,然后将贴有胶膜片的晶圆切成单个芯片,只划透胶膜层,不划胶膜片的最下层,即保护层;
上芯
在胶膜片专用上芯机上,将芯片自动放置到L/F设置位置的正中央,加热后IC芯片粘在B排内引脚和其余几个内引脚边缘,通过烘烤达到牢固性粘贴;
压焊
本封装IC芯片上焊盘距离内引脚的镀金触点较近,采用小折弯焊线;
塑封
塑封采用全自动包封系统:Y-series E60T, CEL9220HF10TS系列环保塑封料。其工艺条件如下:
模温(℃):165~185,合模式压力(Ton):35~55;注塑压力(Ton):
0.75~1.33;注塑时间(s):6~15;固化时间(s):90~120。
后固化采用QFN固化烘箱,150℃,7小时。
切割
采用本产品NLGA1/NLGA2专用切割夹具,按正常QFN切割工艺切割。
所述多芯片封装的减薄、划片,塑封,打印,切割与单芯片封装相同,其它步骤方法如下:
上芯、
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片粘在中间排内引脚和其余几个内引脚边缘,通过烘烤达到牢固性粘贴;
压焊
采用小折弯焊线。
所述双芯片堆叠封装的的减薄、划片,打印,切割与单芯片封装相同,其它步骤的生产方法如下:
上芯、
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后原IC芯片粘在中间排内引脚和其余几个内引脚边缘,完成全部第一次上芯后,在原IC芯片上采用同样方法,将带胶膜片的另一IC芯片粘在原IC芯片上,通过烘烤达到牢固性粘贴;
压焊
采用小折弯焊线;
塑封
塑封采用全自动包封系统:Y-series E60T, CEL9220HF10TS系列环保塑封料。其工艺条件如下:
模温(℃):165~185,合模式压力(Ton):35~55;注塑压力(Ton):
0.75~1.33;注塑时间(s):6~15;固化时间(s):90~120。
后固化采用QFN固化烘箱, 150℃,7小时。
附图说明
图中,1.第一列引脚(凸点),2. 第二列引脚(凸点),3. 第三列引脚(凸点),4.第四列引脚(凸点);5.胶膜片,6. 原IC芯片,7.键合线,8.塑封体,9. 另一IC芯片,10. 芯片与芯片间键合线,11. 第二胶膜片;A为第一行内引脚,B为第二行内引脚,C为第三行内引脚,D为第四行内引脚;a第一行金凸点,b 为第二行金凸点,c为第三行金凸点,d为第四行金凸点。
具体实施方式
3、压焊
由于原IC芯片6粘在内引脚上,原IC芯片6上焊盘距离内引脚焊点较近,不能按正常QFN键合工艺,只能采用短焊线低弧度键合,其压焊参数如下:
预热温度:130℃,加热温度:150℃。
2、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后原IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的芯片粘在B排和C排引脚(如NLGA16L,B2、B3、C2、C3)的边缘。完成全部第一次上芯后,采用同样方法,将另一IC芯片9粘在B4和C4引脚上,通过烘烤达到牢固性粘贴。
3、压焊
由于原IC芯片6粘在内引脚上,焊盘距离内引脚焊点较近,另外,双芯片堆叠封装,另一IC芯片9粘在原IC芯片6上,另一IC芯片9与原IC芯片6之间还要焊线,所以,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
4、塑封
由于双芯片堆叠封装,另一IC芯片9与原IC芯片6之间还要焊线,塑封的注塑过程,塑封料流动和冲线与单芯片差别较大,要通过工艺试验,不断调整和优化注塑工艺参数才能达到塑封不冲丝、不断线和无离层的最佳结果。
1、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后原IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的原IC芯片6粘在B排和C排引脚(如NLGA16L:B2、B3和C2、C3)上,带胶膜片的另一IC芯片9粘在B4和C4引脚的边缘。
2、压焊
由于原IC芯片6粘在内引脚上,IC芯片上焊盘距离内引脚焊点较近,不能按正常QFN键合工艺,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
3、塑封
由于双芯片堆叠封装,另一IC芯片9与原IC芯片6之间还要焊线,塑封的注塑过程,塑封料流动和冲线与单芯片差别较大,要通过工艺试验,不断调整和优化注塑工艺参数才能达到塑封不冲丝、不断线和无离层的最佳结果。其塑工艺参数如下:
模具温度(℃):175±10; 合模压力(MPa);40~120;
注塑压强(Ton):0.80~1.33; 注塑时间(sec):10±2;
固化时间(sec):90±30。
3、压焊
由于原IC芯片6粘在内引脚上,原IC芯片6上焊盘距离内引脚焊点较近,采用短焊线低弧度键合。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
2、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后原IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的芯片粘在B排和C排引脚(如NLGA16L,B2、B3、C2、C3)的边缘。完成全部第一次上芯后,采用同样方法,将另一IC芯片9粘在B4和C4引脚上,通过烘烤达到牢固性粘贴。
3、压焊
由于原IC芯片6粘在内引脚上,焊盘距离内引脚焊点较近,另外,双芯片堆叠封装,另一IC芯片9粘在原IC芯片6上,另一IC芯片9与原IC芯片6之间还要焊线,所以,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):8;
第一焊点焊接力 ( mN) :110(一般QFN压焊120~300);
第一焊点焊接功率(%): 20;
第二焊点(内引线脚)焊接时间(ms):6;
第二焊点(内引线脚)焊接力(mN):550 (一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):130;
4、塑封
由于双芯片堆叠封装,另一IC芯片9与原IC芯片6之间还要焊线,塑封的注塑过程。塑封工艺参数如下;
模具温度(℃):175; 合模压力(MPa);45;
注塑压强(Ton):0.90; 注塑时间(sec):9;
固化时间(sec):90。
1、减薄、划片
同实施例1
2、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后原IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的原IC芯片6粘在B排和C排引脚(如NLGA16L:B2、B3和C2、C3)上,带胶膜片的另一IC芯片9粘在B4和C4引脚的边缘。
3、压焊
由于原IC芯片6粘在内引脚上,原IC芯片上焊盘距离内引脚焊点较近,不能按正常QFN键合工艺,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
第一焊点(芯片上的焊盘)焊接时间(ms):9;
第一焊点焊接力 ( mN) :125(一般QFN压焊120~300);
第一焊点焊接功率(%):23;
第二焊点(内引线脚)焊接时间(ms):8;
第二焊点(内引线脚)焊接力(mN):650 (一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):140;
4、塑封
由于双芯片堆叠封装,另一IC芯片9与原IC芯片6之间还要焊线,塑封的注塑过程。塑封工艺参数如下:
模具温度(℃):175; 合模压力(MPa);50;
注塑压强(Ton):1.1; 注塑时间(sec):12;
固化时间(sec):90;
后固化:150℃,7h。
3、压焊
由于原IC芯片6粘在内引脚上,原IC芯片6上焊盘距离内引脚焊点较近,不能按正常QFN键合工艺,只能采用短焊线低弧度键合(是本发明方法采用的特殊焊线,),难度较大,需要攻关,必须与塑封工序合作试验解决。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
2、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后原IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的芯片粘在B排和C排引脚(如NLGA16L,B2、B3、C2、C3)的边缘。完成全部第一次上芯后,采用同样方法,将另一IC芯片9粘在B4和C4引脚上,通过烘烤达到牢固性粘贴。
3、压焊
由于原IC芯片6粘在内引脚上,焊盘距离内引脚焊点较近,另外,双芯片堆叠封装,另一IC芯片9粘在原IC芯片6上,另一IC芯片9与原IC芯片6之间还要焊线,所以,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):9;
第一焊点焊接力 ( mN) : 135(一般QFN压焊120~300);
第一焊点焊接功率(%):25;
第二焊点(内引线脚)焊接时间(ms):10;
第二焊点(内引线脚)焊接力(mN):700 (一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):145;
4、塑封
由于双芯片堆叠封装,另一IC芯片9与原IC芯片6之间还要焊线,塑封的注塑过程,塑封料流动和冲线与单芯片差别较大,要通过工艺试验,不断调整和优化注塑工艺参数才能达到塑封不冲丝、不断线和无离层的最佳结果。塑封工艺参数如下;
模具温度(℃):180; 合模压力(MPa);110;
注塑压强(Ton):1.23; 注塑时间(sec):8;
固化时间(sec):11
后固化:150℃,7h。
1、减薄、划片
同实施例5
2、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后原IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的原IC芯片6粘在B排和C排引脚(如NLGA16L:B2、B3和C2、C3)上,带胶膜片的另一IC芯片9粘在B4和C4引脚的边缘。
3、压焊
由于原IC芯片6粘在内引脚上,IC芯片上焊盘距离内引脚焊点较近,不能按正常QFN键合工艺,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):9;
第一焊点焊接力 ( mN) :138(一般QFN压焊120~300);
第一焊点焊接功率(%):25;
第二焊点(内引线脚)焊接时间(ms):9;
第二焊点(内引线脚)焊接力(mN):450~800(一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):150;
4、塑封
由于双芯片堆叠封装,另一IC芯片9与原IC芯片6之间还要焊线,塑封的注塑过程,塑封料流动和冲线与单芯片差别较大,要通过工艺试验,不断调整和优化注塑工艺参数才能达到塑封不冲丝、不断线和无离层的最佳结果。其塑工艺参数如下:
模具温度(℃): 165; 合模压力(MPa);100;
注塑压强(Ton):1.20; 注塑时间(sec):9;
固化时间(sec):100;
后固化:150℃,7h 。
Claims (4)
1.一种无载体栅格阵列IC芯片封装件,包括内引脚、IC芯片、焊盘、键合线及塑封体,其特征在于所述内引脚在封装件正面设为多排矩阵式,背面为外露的多排近似正方形的圆形镀金触点,所述外露的多排近似正方形的圆形镀金触点为封装件背面的引脚上设有近似正方形的圆形独立引脚触点;所述多排矩阵式或多排近似正方形的圆形镀金触点的同时为三排×三列或者四排×四列;所述三排×三列时,上表面设为A、B、C三排内引脚,其中A排内引脚有A1、A2、A3,B排内引脚有B1、B2、B3,其中B1、B2连接在一起,C排内引脚有C1、C2、C3;所述内引脚上面为第一IC芯片(6),所述内引脚上面为原IC芯片(6),内引脚和原IC芯片(6)之间由胶膜片(5)粘接,原 IC芯片(6)上的焊盘通过键合线(7)与内引脚的镀金触点相连,所述塑封体(8)包围胶膜片(5)、原IC芯片(6)、键合线(7)及内引脚边缘,构成封装件的电路整体;所述外露的多排近似正方形的圆形镀金触点为所述封装件背面a排引脚上设有3个大小相同近似正方形的圆形独立引脚触点a1、a2、a3;b排也设有3个近似正方形的圆形独立触点b1、b2、b3,其中b2的左上角成0.10×45°斜角,其斜角正对的a排触点为该电路Pin 1脚;c排也设有3个大小相同的近似正方形圆形独立触点c1、c2、c3。
2.根据权利要求1所述的一种无载体栅格阵列IC芯片封装件,其特征在于所述封装件设有双芯片堆叠封装形式,在原IC芯片(6)上端设有另一IC芯片(9),原IC芯片(6)和另一IC芯片(9)之间设有胶膜片(5)粘接, 原IC芯片(6)上的焊盘通过键合线(7)与内引脚的镀金触点或另一IC芯片(9)相连,构成电路的电流和信号通道,塑封体包围胶膜片、IC芯片、键合线、内引脚边缘,构成电路整体。
3.根据权利要求1或2所述的一种无载体栅格阵列IC芯片封装件的生产方法,其特征在于所述封装件为单芯片封装形式时的生产方法包括:晶圆减薄、划片、上芯、压焊、塑封、后固化、打印、切割分离、检验、包装、入库,按下述工艺步骤进行:
减薄、划片
先将晶圆减薄到150μm~-200μm,清洗干净并烘干后,背面贴上胶膜片,去掉减薄胶膜,然后将贴有胶膜片的晶圆切成单个芯片,只划透胶膜层,不划胶膜片的最下层,即保护层;
上芯
在胶膜片专用上芯机上,将芯片自动放置到L/F设置位置的正中央,加热后IC芯片粘在B排内引脚和其余几个内引脚边缘,通过烘烤达到牢固性粘贴;
压焊
本封装件IC芯片上焊盘距离内引脚的镀金触点较近,采用小折弯焊线;
塑封
由于键合采用小折弯焊线,且焊线拉得较紧,塑封时要调整工艺参数,防止脱球;其塑封工艺参数如下:
模具温度(℃):175±10; 合模压力(MPa);40~120;
注塑压强(Ton):0.80~1.33; 注塑时间(sec):10±2;
固化时间(sec):90±30;
后固化:150℃,7h;
切割
采用本产品NLGA1/NLGA2专用切割夹具进行。
4.根据权利要求3所述一种无载体栅格阵列IC芯片封装件的生产方法 ,包括晶圆减薄、划片、上芯、压焊、塑封、后固化、打印、切割分离、检验、包装、入库,其特征在于所述封装件为双芯片堆叠封装形式时的减薄、划片,打印,切割与单芯片封装相同,其它步骤的生产方法如下:
上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后原IC芯片(6)粘在中间排内引脚和其余几个内引脚边缘,完成全部第一次上芯后,在原IC芯片(6)上采用同样方法,将带胶膜片的另一IC芯片(9)粘在原IC芯片(6)上,通过烘烤达到牢固性粘贴;
压焊
采用小折弯焊线;
塑封
塑封的注塑过程中,其塑封工艺参数如下:
模具温度(℃):175±10; 合模压力(MPa);40~120;
注塑压强(Ton):0.80~1.33; 注塑时间(sec):10±2;
固化时间(sec):90±30;
后固化:150℃,7h。
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