CN102074540B - Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages - Google Patents
Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000011159 matrix material Substances 0.000 title claims abstract description 22
- 230000009977 dual effect Effects 0.000 title claims abstract description 20
- 238000003466 welding Methods 0.000 claims abstract description 10
- 229910052802 copper Inorganic materials 0.000 claims description 38
- 239000010949 copper Substances 0.000 claims description 38
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 38
- 229910052737 gold Inorganic materials 0.000 claims description 38
- 239000010931 gold Substances 0.000 claims description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 36
- 238000004806 packaging method and process Methods 0.000 claims description 27
- 239000003292 glue Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 19
- 238000005516 engineering process Methods 0.000 claims description 15
- 241000218202 Coptis Species 0.000 claims description 12
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 12
- 238000005538 encapsulation Methods 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 238000000465 moulding Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 7
- 230000002238 attenuated effect Effects 0.000 claims description 6
- 241000216843 Ursus arctos horribilis Species 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000012536 packaging technology Methods 0.000 claims description 5
- 238000007639 printing Methods 0.000 claims description 5
- 230000000630 rising effect Effects 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 241000196324 Embryophyta Species 0.000 claims description 4
- 239000004568 cement Substances 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 230000001105 regulatory effect Effects 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000000969 carrier Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 10
- 230000008901 benefit Effects 0.000 abstract description 3
- 230000015654 memory Effects 0.000 abstract description 2
- 238000004134 energy conservation Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 239000005022 packaging material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 210000003205 muscle Anatomy 0.000 description 3
- 238000007493 shaping process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000010835 comparative analysis Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000003203 everyday effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000009753 muscle formation Effects 0.000 description 1
- 230000010181 polygamy Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2924/181—Encapsulation
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- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention provides a matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on the frame and a production method of the IC packages. The matrix DIP lead frame comprises a frame and a plurality of unit frames in the frame, wherein the unit frames are distributed on the frame in a matrix manner and are in odd-numbered lines; the base islands of the adjacent unit frames in the 2n-1<th> line and the 2n<th> line are connected with the borders of the frame via connecting bars; and the outer lead pins of the adjacent unit frames in the 2n-1<th> line and the 2n<th> line are arranged in a staggered manner and are connected with the borders of the frame via grids. The invention improves the use ratio of the frame materials, has simple and reasonable structure, has the advantages of low cost, energy conservation and emission reduction and the like, can be widely applied in the fields such as LED tubes, computer interface types, power supply modules, network transformers, DIP switches, pressure sensors, standard logic ICs, large-scale integration (LSI) of memories and the like and is convenient for implementing printed circuit board (PCB) perforating and welding.
Description
Technical field
The present invention relates to the DIP lead frame of semiconductor packages, based on IC chip package and the production method thereof of this lead frame.
Background technology
For a long time, the encapsulation of DIP series of products is made and is limited by the lead frame pattern that develops the early stage eighties always, at that time because being subjected to the impact of lead frame rolled copper foil manufacturing technology, diel and stamping technology, the encapsulation aspect is subjected to plastic package die, electroplate and to select coating technology, cut the Restricted requirements such as the accuracy of identification of muscle shaping dies technology, upper core/pressure welding device and operation window scope, lead frame generally designs at 10mm～30mm with interior width, be double or single design, every 10～20 unit do not wait.This framework adopts traditional plastic package die, and Automatic-rack Line is electroplated, manually Trim Molding.Such mode of production not only production efficiency is low, and security risk is large when using traditional plastic package die, Automatic-rack Line to electroplate, manually cut muscle shaping dies configuration converted products, and the product design dimensional uniformity is poor, the encapsulation rate of finished products is low, the quality of product is checked on by the polygamy inspector, causes that production cost is high, efficient is low.
Through the development in more than 20 years, huge variation all occured in the manufacturing technology that above-mentioned material manufacturing technology and production equipment supporting technology, encapsulation are produced and package application technology and standardization level thereof.The wall scroll framework can accomplish that 70mm～80mm is wide, if be designed to many rows, denumerable multiple can improve the utilance of material in available frame (single/double) quantity concerning lead frame manufactory.
Because at present list/double DIP series of products belong to people intensive encapsulating products, have that production efficiency is low, stock utilization is low, course of processing error rate is high, use equipment is many, cause the problems such as floor space is large, energy resource consumption is large, the manual processing mold security risk of DIP is large.
Unit framework on the circuit lead frame is the single file distribution at present, and outer pin and the Ji Dao of each unit framework both sides are connected in respectively on the framework border of both sides.Since the progress of integrated circuit technique, electronic product level and functional promotion trend multifunction, high speed, high capacity, densification, lightweight.Therefore carrier structure technology and the material of many novelties are developed, owing to need to increase the quantity of integrated circuit modules when the integrated circuit volume reduces, just need to further reduce the volume of integrated antenna package module, namely dwindle the volume of integrated antenna package.Therefore, the lead frame volume potential must also require to dwindle.
Summary of the invention
One of purpose of the present invention is to provide a kind of matrix form DIP lead frame;
Two of purpose is to provide the IC packaging part based on described matrix form DIP lead frame;
Three of purpose is to provide the production technology of described IC packaging part;
Thereby reach the consumption that reduces frame material and improve the plastic packaging material utilance, improve production efficiency and product quality reduces error rate, reduces security risk, is a kind of effective way that reduces cost, energy-saving and emission-reduction.
The present invention is achieved in that a kind of matrix form DIP lead frame, formed by framework and several unit frameworks of being located in the framework, described unit framework is at described framework that matrix form distributes and line number is odd-numbered line, wherein the capable Ji Dao with the capable adjacent cells framework of 2n of 2n-1 links to each other with described framework border by intercell connector, 2n-1 is capable and the outer lead pin of the adjacent cells framework that 2n is capable is staggered, and is connected with described framework border by grizzly bar.
Described unit framework drops into and the output benefit comparative analysis is that 5 row are optimum.
A kind of dual chip IC packaging part, comprise that carrier on the described unit framework and this stack of carriers place first, the second chip, be specially: put first an IC chip on this carrier, pad on the one IC chip links to each other with interior pin by bonding line, afterwards, put again the 2nd IC chip on the one IC chip, first, the 2nd IC chip is linked by copper or gold solder line, adopt copper or gold thread by ball bonding the terminal pin of the 2nd IC chip and unit framework to be linked to each other, at last, plastic-sealed body has covered first, the terminal pin of the 2nd IC chip bonding gold or copper cash and unit framework and to have consisted of circuit whole.
A kind of packaging technology flow process of dual chip IC packaging part is as follows:
A. attenuate/scribing
The wafer thickness thinning that lower floor's chip is corresponding is: 200 μ m+10 μ m, roughness Ra 0.10mm～0.05mm, the wafer thickness thinning that the upper strata chip is corresponding is: 180 μ m+10 μ m, and the ultra-thin attenuated polishing function in standby 8 "～12 " of attenuate facility adopts the anti-thin attenuated polishing technique of warpage;
B, once go up core
Adopt single carrier element framework, use special-purpose upper feed collet, Glue dripping head uniformly with adhesive dots on lead frame carrier, lower floor's chip (large chip) is bonded on the carrier, and the adjustable height of core is 4000-6500step on the suction nozzle, and the thimble lifting height is 100-160 step, the thimble rising delay time is 5-10ms, point glue height is 1400-2000step, and bonding die glue THICKNESS CONTROL is solidified baking nitrogen flow＞0.8 l/h in 8-38um;
Core on c, the secondary
Put first insulating cement (QMI538NB) in the ground floor chip front side, again second chip aimed at stick on top, be placed on the front of one deck chip.One-step solidification behind the core on twice, baking temperature: 150-175 ℃, stoving time: 180min;
D, pressure welding
The dual chip stacked package generally speaking, connects first the up and down bonding wire of chip chamber, next connects line between lower floor's chip and pin, welds at last between upper strata chip and pin to be connected, and the bonding wire height will strictly be controlled, camber is controlled at 150um-300um, prevents short circuit between the levels bonding wire.Distance between centers of tracks is bad less than 2 times wire diameter;
Plastic packaging, printing, plating, Trim Molding method are with DIP single-chip package part.
The present invention is because the adjacent leads of adjacent cells framework adopts interior staggered design, frame size is controlled in 255mm * 80mm, take DIP8L-5P as example, can make adjacent cells only be 13.716mm in the step pitch of directions X, and the pin of the adjacent frame of existing single or double lead frame is parallel continuous design, and take DIP8L-2P as example, its adjacent cells is 18.288mm in the step pitch of directions X, the DIP8L-5P step pitch has reduced 4.572mm than DIP8L-2P, has improved the utilance of frame material.Compare with existing double framework, the blaster fuse frame material utilance has improved 26.93%(and has seen Table 1);
Table 1 DIP8L-5P and DIP8L-2P framework consumption contrast
| Project | Every frame size (mm) | Average every area (mm) 2 | Area Ratio (%) |
| DIP8L-2P | 182.88×24.638 | 225.8 | S 2p/S 5p: 136.36 |
| DIP8L-5P | 251.3076×59.436 | 165 | S 5p/S 2p: 73.07 |
The structure of matrix form DIP lead frame of the present invention is so that produce allocation plan and more optimize, can adopt MGP plastic package die, automatic arranging machine and swash of wave road machine, automatically cut muscle formation system (cutting muscle, shaping, each secondary mould of separation), the high-speed line plating line is electroplated, take DIP8L as example, the production efficiency of 5 row's frameworks is double framework 2.25 times (seeing Table 2), saves plastic packaging material 42.26%(and sees Table 3).
Table 2 DIP8L-5P and the contrast of DIP8L-2P plastic packaging production efficiency
| Project | Every modulus amount (only) | Modulus every day (inferior) | Encapsulation quantity (only) | Production efficiency contrast (%) |
| DIP8L-2P | 320 | 400 | 128000 | S 2p/S 5p: 56.14 |
| DIP8L-5P | 720 | 400 | 288000 | S 5p/S 2p: 2.25 |
Table 3 DIP8L-5P and DIP8L-2P plastic packaging material consumption contrast
| Project | Every modulus amount only | Weight * piece is counted g | Average every quantity g/ only | Every amount ratio (%) |
| DIP8L-2P | 320 | 80×3 | 0.75 | C2P/C5P：173.2 |
| DIP8L-5P | 720 | 6.5×48 | 0.433 | C5P /C2P：55.73 |
The structure of matrix form DIP lead frame of the present invention can be selected bonding die glue, the plastic packaging material of domestic brand common material and environment-friendly materials, the selection application that can realize lower cost materials reaches take copper wire bonding technique as main, and the gold thread bonding is auxiliary low-cost production scheme and technology.
The present invention is simple and reasonable, have the advantages such as cost is low, energy-saving and emission-reduction, be widely used in LED fluorescent tube, computer interfaceJi Suanjijiekou type, supply power module, network transformer, DIP switch, pressure sensor, the convenient piercing welding that realizes pcb board, and the fields such as standard logic IC, memory LSI.
Description of drawings
Fig. 1 is matrix form DIP lead frame structure schematic diagram of the present invention;
Fig. 2 is the I enlarged drawing among Fig. 1, is adjacent encapsulation unit framework list carrier structure schematic diagram;
Fig. 3 is the I enlarged drawing among Fig. 1, is the two carrier structure schematic diagrames of adjacent encapsulation unit framework;
Fig. 4 is the single carrier dual chip of the present invention planar package part generalized section;
Fig. 5 is the two carrier dual chip planar package part generalized sections of the present invention;
Fig. 6 is dual chip stack package generalized section of the present invention.
Embodiment
The present invention is further illustrated below in conjunction with accompanying drawing.
Embodiment 1, with reference to Fig. 1, Fig. 2, a kind of single carrier matrix formula DIP lead frame, its unit framework is that single carrier structure and line number are odd-numbered line, wherein the capable Ji Dao with the capable adjacent cells framework of 2n of 2n-1 links to each other with described framework border by intercell connector 18,2n-1 is capable and the outer lead pin of the adjacent cells framework that 2n is capable is staggered, and is connected with described framework border by grizzly bar 19.For example: framework A unit and framework B unit are two adjacent unit frameworks, wherein B8 is clipped between A1, the A2 terminal pin, A2 is clipped between B8 and the B7 terminal pin, B7 is clipped between A2 and the A3 terminal pin, A3 is clipped between B7 and the B6 terminal pin, B6 is clipped between A3 and the A4 terminal pin, and A4 is clipped between B6 and the B5 terminal pin, other the like.
Embodiment 4, with reference to Fig. 1, Fig. 2, Fig. 6, a kind of dual chip IC stack package of the unit framework based on embodiment 1, comprise first of carrier 1 on the described encapsulation unit and the 1 stacking placement of this carrier, the second chip 13,14, be specially: put first an IC chip 13 on this carrier 1, pad on the one IC chip 13 links to each other with interior pin 4 by bonding line 5, afterwards, put again the 2nd IC chip 14 on the one IC chip 13, first, the 2nd IC chip 13,14 are linked by copper or gold solder line 15, adopt copper or gold thread 16 by ball bonding the terminal pin 4 of the 2nd IC chip 14 and unit framework to be linked to each other, at last, plastic-sealed body 6 has covered first, the 2nd IC chip 13,14, bonding gold or copper cash 5,15,16 and the terminal pin 4 of unit framework and to have consisted of circuit whole.
Can realize 3 chips or 4 chips or 5 chips or 6 chip-stacked multi-chip IC packaging parts after chip process corase grind in the present embodiment, fine grinding, the polishing.
The packaging technology flow process of the dual chip IC packaging part of embodiment 3 and embodiment 5 is as follows:
A. wafer attenuate/scribing
The wafer attenuate speed of mainshaft is 2400 rpm-3000 rpm, wafer thickness thinning 380um ± 20um;
The equipment and process of wafer attenuate, scribing is with common double framework encapsulation wafer attenuate, scribing process;
B, upper core
Adopt single carrier element framework or two carrier element framework, first put bonding die glue (conducting resinl or insulating cement) at single or two carrier, chip is bonded on the carrier, if different chip, glue first little chip, glued behind all little chips again the chip on sticking another carrier, die Bonder adopts AD829A and two kinds of die Bonder of AD828 usually, select the shape and size of suction nozzle and Glue dripping head according to the size of chip size and chip size, the adjustable height of core is 4000-6500step on the suction nozzle, the thimble lifting height is 100-160step, and the thimble rising delay time is 5-10ms, and some glue height is 1400-2000step, bonding die glue THICKNESS CONTROL is in 8-38um, solidify baking nitrogen flow＞0.8 l/h, baking temperature 175-180 ℃, 3 hours;
C, pressure welding
Substrate heating temperature is 228 ℃-235 ℃, regulating the sparking flow is 2600mA-3100mA, regulating the discharge time of striking sparks is 630us-710us, make the gold goal head melt to obtain the round and smooth flawless gold goal FAB in surface, the time that adds on the wiring chopper is ultrasonic wave and the pressure of 10ms ± 3ms, and supersonic frequency is 120KHZ ± 10 KHZ, and the way of output is electric current, power is 41mw ± 3mw, and Output pressure is 32gf ± 2gf;
D, plastic packaging, rear curing
Many row's matrix form framework plastic packagings use the MGP plastic package die, injection pressure: (1200-1800) Psi, injection time: 7-15S, mold temperature: 160-180 ℃, matched moulds pressure welding: 8-20Mpa, curing time: 120-150s, rear curing temperature 175-180 ℃, 7 hours;
E, printing
With common DIP plastic packaged integrated circuit production technology;
F, plating
Electroplating device from before the rack plating plating mode change the high-speed line plating mode into, first the product behind the plastic packaging is sent the High-speed Electric plate wire to electroplate, bath temperature: 35-45 ℃, electroplating current: 95 ± 5A/ groove, thickness of coating is controlled at: 7.0-20.32um;
G, Trim Molding
Adopt automatic Trim Molding system, automatic feed enters pipe automatically.
The packaging technology flow process of the dual chip IC stack package of embodiment 4 is as follows:
A. attenuate/scribing
The wafer thickness thinning that lower floor's chip is corresponding is: 200 μ m+10 μ m, roughness Ra 0.10mm～0.05mm, the wafer thickness thinning that the upper strata chip is corresponding is: 180 μ m+10 μ m, and the ultra-thin attenuated polishing function in standby 8 "～12 " of attenuate facility adopts the anti-thin attenuated polishing technique of warpage;
B, once go up core
Adopt single carrier element framework, use special-purpose upper feed collet, Glue dripping head uniformly with adhesive dots on lead frame carrier, lower floor's chip (large chip) is bonded on the carrier, and the adjustable height of core is 4000-6500step on the suction nozzle, and the thimble lifting height is 100-160step, the thimble rising delay time is 5-10ms, point glue height is 1400-2000step, and bonding die glue THICKNESS CONTROL is solidified baking nitrogen flow＞0.8 l/h in 8-38um;
Core on c, the secondary
Put first insulating cement (QMI538NB) in the ground floor chip front side, again second chip aimed at stick on top, be placed on the front of one deck chip.One-step solidification behind the core on twice, baking temperature: 150-175 ℃, stoving time: 180min;
D, pressure welding
The dual chip stacked package generally speaking, connects first the up and down bonding wire of chip chamber, next connects line between lower floor's chip and pin, welds at last between upper strata chip and pin to be connected, and the bonding wire height will strictly be controlled, camber is controlled at 150um-300um, prevents short circuit between the levels bonding wire.Distance between centers of tracks is bad less than 2 times wire diameter;
Plastic packaging, printing, plating, Trim Molding method are with DIP single-chip package part.
Utilize the production technology of single-chip IC packaging part of embodiment 1 the same with the production procedure of conventional DIP plastic packaged integrated circuit.
Claims (1)
1. production method based on the IC packaging part of matrix form DIP lead frame, it is characterized in that: described matrix form DIP lead frame is comprised of framework and several unit frameworks of being located in the framework, described unit framework is at described framework that matrix form distributes and line number is odd-numbered line, these odd number behavior 5 row; Wherein 2n-1 is listed as with the Ji Dao of the adjacent cells framework of 2n row and links to each other with described framework border by intercell connector, the 2n-1 row are staggered with the outer lead pin of the adjacent cells framework of 2n row, and be connected with described framework border by grizzly bar, n is the natural number more than or equal to 1; Described unit framework is single carrier structure or two carrier structure, and line number is odd-numbered line; Described pair of carrier structure is: each unit framework has two carriers; Wherein pin A7, the A8 of unit framework A link to each other with carrier Z2, pin A3 links to each other with carrier Z1, and the pin B7 of adjacent cells framework B links to each other with carrier Z4 with B8, pin B3 is connected with carrier Z3; The structure of the dual chip IC packaging part that described unit framework forms when being single carrier structure is: comprise the carrier on the described unit framework, parallel first, second IC chip of placing on the carrier of this unit framework, each plants a gold or copper ball in advance first on the pad on the one IC chip and the 2nd IC chip, then use gold or copper cash stacking gold thread or copper wire bonding ball on the gold of an IC chip or copper ball, the arcing of arch silk is stacking gold thread or copper wire bonding ball on the gold of the pad on the 2nd IC chip or copper ball, and first, second IC chip is linked to each other; The outer pad of described first, second IC chip links to each other with the interior pin of unit framework by copper or gold solder line bonding; At last, plastic-sealed body has covered first, second IC chip, bonding gold or copper cash, gold or copper ball, bond ball and unit framework terminal pin fully and has consisted of circuit integral body; The structure of the dual chip IC packaging part that described unit framework forms when being two carrier structure is: comprise the carrier on the described unit framework, split first, second IC chip on this carrier, each plants a gold or copper ball in advance first on the pad on the one IC chip or the 2nd IC chip, then use gold or copper cash stacking gold thread or copper wire bonding ball on the gold of an IC chip or copper ball, the arcing of arch silk is stacking gold thread or copper wire bonding ball on the gold of the pad on the 2nd IC chip or copper ball, and an IC chip is linked to each other with the 2nd IC chip; The outer pad of described first, second IC chip links to each other with the interior pin of described unit framework by gold or copper-weld wire bonding, at last, plastic-sealed body has covered the terminal pin of first, second IC chip, bonding gold or copper cash, gold or copper ball, bond ball and unit framework fully and has consisted of circuit integral body; The packaging technology flow process of the dual chip IC packaging part that described unit framework forms when being single carrier or two carrier structure is as follows:
A. wafer attenuate/scribing
The wafer attenuate speed of mainshaft is 2400 rpm-3000 rpm, wafer thickness thinning 380 μ m ± 20 μ m;
The equipment and process of wafer attenuate, scribing is with common double framework encapsulation wafer attenuate, scribing process;
B, upper core
Adopt single carrier element framework or two carrier element framework, first put bonding die glue at single or two carrier, chip is bonded on the carrier, if different chip, glue first little chip, glued behind all little chips again the chip on sticking another carrier, die Bonder adopts AD829A and two kinds of die Bonder of AD828 usually, select the shape and size of suction nozzle and Glue dripping head according to the size of chip form and chip size, the adjustable height of core is 4000-6500step on the suction nozzle, the thimble lifting height is 100-160 step, and the thimble rising delay time is 5-10ms, and some glue height is 1400-2000step, bonding die glue THICKNESS CONTROL is in 8-38 μ m, solidify baking nitrogen flow＞0.8 l/h, baking temperature 175-180 ℃, 3 hours;
C, pressure welding
Substrate heating temperature is 228 ℃-235 ℃, regulating the sparking flow is 2600mA-3100mA, regulating the discharge time of striking sparks is 630 μ s-710 μ s, make the gold goal head melt to obtain the round and smooth flawless gold goal FAB in surface, the time that adds on the wiring chopper is ultrasonic wave and the pressure of 10ms ± 3ms, and supersonic frequency is 120KHZ ± 10 KHZ, and the way of output is electric current, power is 41mw ± 3mw, and Output pressure is 32gf ± 2gf;
D, plastic packaging, rear curing
Many row's matrix form framework plastic packagings use the MGP plastic package die, injection pressure: (1200-1800) Psi, injection time: 7-15s, mold temperature: 160-180 ℃, matched moulds pressure welding: 8-20Mpa, curing time: 120-150s, rear curing temperature 175-180 ℃, 7 hours;
E, printing
With common DIP plastic packaged integrated circuit production technology;
F, plating
Electroplating device from before the rack plating plating mode change the high-speed line plating mode into, first the product behind the plastic packaging is sent the High-speed Electric plate wire to electroplate, bath temperature: 35-45 ℃, electroplating current: 95 ± 5A/ groove, thickness of coating is controlled at: 7.0-20.32 μ m;
G, Trim Molding
Adopt automatic Trim Molding system, automatic feed enters pipe automatically.
2
.A kind of production method of the IC packaging part based on matrix form DIP lead frame, it is characterized in that: described matrix form DIP lead frame is comprised of framework and several unit frameworks of being located in the framework, described unit framework is at described framework that matrix form distributes and line number is odd-numbered line, these odd number behavior 5 row; Wherein 2n-1 is listed as with the Ji Dao of the adjacent cells framework of 2n row and links to each other with described framework border by intercell connector, the 2n-1 row are staggered with the outer lead pin of the adjacent cells framework of 2n row, and be connected with described framework border by grizzly bar, n is the natural number more than or equal to 1; Described unit framework is single carrier structure, and line number is odd-numbered line; The structure of the dual chip IC packaging part that described unit framework forms when being single carrier structure is: comprise carrier on the described unit framework, and this carrier in first, second IC chip of stacking placement; Be specially: put first an IC chip on this carrier, pad on the one IC chip links to each other with interior pin by bonding line, afterwards, put again the 2nd IC chip on the one IC chip, first, second IC chip is linked by copper or gold solder line, adopt copper or gold thread by ball bonding the terminal pin of the 2nd IC chip and unit framework to be linked to each other, last, plastic-sealed body has covered the terminal pin of first, second IC chip, bonding gold or copper cash and unit framework and has consisted of circuit integral body; The packaging technology flow process of the dual chip IC packaging part that this unit framework forms when being single carrier structure is as follows:
A. attenuate/scribing
The wafer thickness thinning that lower floor's chip is corresponding is: 200 μ m+10 μ m, roughness Ra 0.10mm～0.05mm, the wafer thickness thinning that the upper strata chip is corresponding is: 180 μ m+10 μ m, and the ultra-thin attenuated polishing function in standby 8 "～12 " of attenuate facility adopts the anti-thin attenuated polishing technique of warpage;
B, once go up core
Adopt single carrier element framework, use special-purpose upper feed collet, Glue dripping head uniformly with adhesive dots on the unit framework carrier, lower floor's chip is bonded on the carrier, and the adjustable height of core is 4000-6500step on the suction nozzle, and the thimble lifting height is 100-160 step, the thimble rising delay time is 5-10ms, point glue height is 1400-2000step, and bonding die glue THICKNESS CONTROL is solidified baking nitrogen flow＞0.8 l/h in 8-38 μ m;
Core on c, the secondary
Put first insulating cement in the ground floor chip front side, again second chip aimed at stick on top, be placed on the front of ground floor chip; One-step solidification behind the core on twice, baking temperature: 150-175 ℃, stoving time: 180min;
D, pressure welding
Dual chip stacked package: connect first the up and down bonding wire of chip chamber, next connects line between lower floor's chip and pin, welds at last between upper strata chip and pin to be connected, and the bonding wire height will strictly be controlled, camber is controlled at 150 μ m-300 μ m, prevents short circuit between the levels bonding wire; Distance between centers of tracks is bad less than 2 times wire diameter; Plastic packaging, printing, plating, Trim Molding method are with existing DIP single-chip package part.
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| US9129237B2 (en) * | 2011-12-28 | 2015-09-08 | Elitetech Technology Co., Ltd. | Integrated interfacing system and method for intelligent defect yield solutions |
| CN102515082A (en) * | 2011-12-31 | 2012-06-27 | 天水华天科技股份有限公司 | Single-carrier MEMS (micro-electro-mechanical system) device package and production method thereof |
| CN102431950B (en) * | 2011-12-31 | 2015-10-07 | 天水华天科技股份有限公司 | A kind of double-deck MEMS stack package and production method thereof |
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