CN102074540A - Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages - Google Patents
Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages Download PDFInfo
- Publication number
- CN102074540A CN102074540A CN2010105613032A CN201010561303A CN102074540A CN 102074540 A CN102074540 A CN 102074540A CN 2010105613032 A CN2010105613032 A CN 2010105613032A CN 201010561303 A CN201010561303 A CN 201010561303A CN 102074540 A CN102074540 A CN 102074540A
- Authority
- CN
- China
- Prior art keywords
- chip
- framework
- gold
- carrier
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention provides a matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on the frame and a production method of the IC packages. The matrix DIP lead frame comprises a frame and a plurality of unit frames in the frame, wherein the unit frames are distributed on the frame in a matrix manner and are in odd-numbered lines; the base islands of the adjacent unit frames in the 2n-1<th> line and the 2n<th> line are connected with the borders of the frame via connecting bars; and the outer lead pins of the adjacent unit frames in the 2n-1<th> line and the 2n<th> line are arranged in a staggered manner and are connected with the borders of the frame via grids. The invention improves the use ratio of the frame materials, has simple and reasonable structure, has the advantages of low cost, energy conservation and emission reduction and the like, can be widely applied in the fields such as LED tubes, computer interface types, power supply modules, network transformers, DIP switches, pressure sensors, standard logic ICs, large-scale integration (LSI) of memories and the like and is convenient for implementing printed circuit board (PCB) perforating and welding.
Description
Technical field
The present invention relates to the DIP lead frame of semiconductor packages, based on the IC chip package and the production method thereof of this lead frame.
Background technology
For a long time, the encapsulation of DIP series of products is made and is limited by the lead frame pattern that develops the early stage eighties always, at that time because of being subjected to the influence of lead frame rolled copper foil manufacturing technology, diel and stamping technology, the encapsulation aspect is subjected to plastic package die, electroplate the restriction select coating technology, to cut muscle shaping dies technology, go up conditions such as the accuracy of identification of core/pressure welding equipment and operation window scope, lead frame generally designs at 10mm～30mm with interior width, be double or single design, every 10～20 unit do not wait.This framework adopts traditional plastic package die, and the rack plating line is electroplated, manually Trim Molding.Such mode of production not only production efficiency is low, and security risk is big when using traditional plastic package die, rack plating line to electroplate, manually cut muscle shaping dies configuration converted products, and the product design dimensional uniformity is poor, the encapsulation rate of finished products is low, the quality of product is checked on by the polygamy inspector, causes production cost height, efficient low.
Through 20 years of development, huge variation has all taken place in manufacturing technology that above-mentioned material manufacturing technology and production equipment supporting technology, encapsulation are produced and package application technology and standardization level thereof.The wall scroll framework can accomplish that 70mm～80mm is wide, if be designed to many rows, denumerable multiple can improve the utilance of material in available frame (single/double) quantity concerning lead frame manufactory.
Because at present list/double DIP series of products belong to people intensive encapsulating products, have that production efficiency is low, stock utilization is low, course of processing error rate height, use equipment are many, cause problems such as floor space is big, energy resource consumption is big, the manual processing mold security risk of DIP is big.
Unit framework on the circuit lead frame is the single file distribution at present, and the outer pin and the Ji Dao of each unit framework both sides are connected in respectively on the framework border of both sides.Since the progress of integrated circuit technique, electronic product level and functional promotion trend multifunction, high speed, high capacity, densification, lightweight.Therefore the carrier structure technology and the material of many novelties are developed, because the integrated circuit volume need increase the quantity of integrated circuit modules when reducing, just need further reduce the volume of integrated circuit package module, promptly dwindle the volume of integrated circuit encapsulation.Therefore, the lead frame volume potential must also require to dwindle.
Summary of the invention
One of purpose of the present invention is to provide a kind of matrix form DIP lead frame;
Two of purpose is to provide the IC packaging part based on described matrix form DIP lead frame;
Three of purpose is to provide the production technology of described IC packaging part;
Thereby reach the consumption that reduces frame material and improve the plastic packaging material utilance, improve production efficiency and product quality reduces error rate, reduces security risk, be a kind ofly reduce cost, the effective way of energy-saving and emission-reduction.
The present invention is achieved in that a kind of matrix form DIP lead frame, form by framework and several unit frameworks of being located in the framework, described unit framework is the matrix form distribution on described framework and line number is an odd-numbered line, wherein the capable Ji Dao with the capable adjacent cells framework of 2n of 2n-1 links to each other with described framework border by intercell connector, 2n-1 is capable and the outer lead pin of the adjacent cells framework that 2n is capable is staggered, and is connected with described framework border by grizzly bar.
Described unit framework input and output benefit comparative analysis are that 5 row are optimum.
A kind of pair of chip IC packaging part, comprise that carrier on the described unit framework and this stack of carriers place first, second chip, be specially: put an IC chip on this carrier earlier, pad on the one IC chip links to each other with interior pin by bonding line, afterwards, put the 2nd IC chip on the one IC chip again, first, the 2nd IC chip is linked by copper or gold solder line, adopt copper or gold thread the terminal pin of the 2nd IC chip and unit framework to be linked to each other by ball bonding, at last, plastic-sealed body has covered first, the terminal pin of the 2nd IC chip bonding gold or copper cash and unit framework and constituted circuit integral body.
The packaging technology flow process of a kind of pair of chip IC packaging part is as follows:
A. attenuate/scribing
The wafer thickness thinning of lower floor's chip correspondence is: 200 μ m+10 μ m, roughness Ra 0.10mm～0.05mm, the wafer thickness thinning of upper strata chip correspondence is: 180 μ m+10 μ m, and the attenuate facility are equipped with the ultra-thin attenuated polishing function in 8 "～12 ", adopt the thin attenuated polishing technology of anti-warpage;
B, once go up core
Adopt single carrier element framework, use the special-purpose feed collet of going up, Glue dripping head uniformly with adhesive dots on lead frame carrier, lower floor's chip (large chip) is bonded on the carrier, and the adjustable height of core is 4000-6500step on the suction nozzle, and the thimble lifting height is 100-160 step, the thimble rising delay time is 5-10ms, point glue height is 1400-2000step, and bonding die glue THICKNESS CONTROL is solidified baking nitrogen flow＞0.8 l/h in 8-38um;
Core on c, the secondary
Put insulating cement (QMI538NB) earlier in the ground floor chip front side, again second chip aimed at stick on top, be placed on the front of one deck chip.One-step solidification behind the core on twice, baking temperature: 150-175 ℃, stoving time: 180min;
D, pressure welding
Twin-core sheet stacked package generally speaking, connects the bonding wire of chip chamber up and down earlier, next connects line between lower floor's chip and pin, welds at last between upper strata chip and pin to be connected, and the bonding wire height is wanted strict control, camber is controlled at 150um-300um, prevents short circuit between the levels bonding wire.Distance between centers of tracks directly is bad less than 2 times line;
Plastic packaging, printing, plating, Trim Molding method are with DIP single-chip package part.
The present invention is because the adjacent leads of adjacent cells framework adopts interior staggered design, frame size is controlled in 255mm * 80mm, with DIP8L-5P is example, can make adjacent cells only be 13.716mm in the step pitch of directions X, and the pin of the adjacent frame of existing single or double lead frame is parallel continuous design, is example with DIP8L-2P, and its adjacent cells is 18.288mm in the step pitch of directions X, the DIP8L-5P step pitch has reduced 4.572mm than DIP8L-2P, has improved the utilance of frame material.Compare with existing double framework, the blaster fuse frame material utilance has improved 26.93%(and has seen Table 1);
Table 1 DIP8L-5P and DIP8L-2P framework consumption contrast
| Project | Every frame size (mm) | Average every area (mm) 2 | Area is than (%) |
| DIP8L-2P | 182.88×24.638 | 225.8 | S 2p/S 5p: 136.36 |
| DIP8L-5P | 251.3076×59.436 | 165 | S 5p/S 2p: 73.07 |
The structure of matrix form DIP lead frame of the present invention makes that producing allocation plan optimizes more, can adopt MGP plastic package die, automatic screening machine and swash of wave road machine, automatically cut muscle formation system (cutting muscle, shaping, each secondary mould of separation), the high-speed line plating line is electroplated, with DIP8L is example, the production efficiency of 5 row's frameworks is double framework 2.25 times (seeing Table 2), saves plastic packaging material 42.26%(and sees Table 3).
Table 2 DIP8L-5P and the contrast of DIP8L-2P plastic packaging production efficiency
| Project | Every modulus amount (only) | Modulus every day (inferior) | Encapsulation quantity (only) | Production efficiency contrast (%) |
| DIP8L-2P | 320 | 400 | 128000 | S 2p/S 5p: 56.14 |
| DIP8L-5P | 720 | 400 | 288000 | S 5p/S 2p: 2.25 |
Table 3 DIP8L-5P and DIP8L-2P plastic packaging material consumption contrast
| Project | Every modulus amount only | Weight * piece is counted g | Average every quantity g/ only | Every amount ratio (%) |
| DIP8L-2P | 320 | 80×3 | 0.75 | C2P/C5P：173.2 |
| DIP8L-5P | 720 | 6.5×48 | 0.433 | C5P?/C2P：55.73 |
The structure of matrix form DIP lead frame of the present invention can be selected bonding die glue, the plastic packaging material of domestic brand common material and environment-friendly materials for use, the selection application that can realize lower cost materials reaches based on copper wire bonding technology, and the gold thread bonding is the low-cost production scheme and the technology of assisting.
The present invention is simple and reasonable, have advantages such as cost is low, energy-saving and emission-reduction, be widely used in LED fluorescent tube, computer interface type, power supply module, network transformer, DIP switch, pressure sensor, the convenient piercing welding that realizes pcb board, and fields such as standard logic IC, memory LSI.
Description of drawings
Fig. 1 is a matrix form DIP lead frame structure schematic diagram of the present invention;
Fig. 2 is the I enlarged drawing among Fig. 1, is adjacent encapsulation unit framework list carrier structure schematic diagram;
Fig. 3 is the I enlarged drawing among Fig. 1, is the two carrier structure schematic diagrames of adjacent encapsulation unit framework;
Fig. 4 is the single carrier twin-core of a present invention plate plane packaging part generalized section;
Fig. 5 is the two carrier twin-core plate plane packaging part generalized sections of the present invention;
Fig. 6 is a twin-core sheet stack package generalized section of the present invention.
Embodiment
The present invention is further illustrated below in conjunction with accompanying drawing.
Embodiment 1, with reference to Fig. 1, Fig. 2, a kind of single carrier matrix formula DIP lead frame, its unit framework is that single carrier structure and line number are odd-numbered line, wherein the capable Ji Dao with the capable adjacent cells framework of 2n of 2n-1 links to each other with described framework border by intercell connector 18,2n-1 is capable and the outer lead pin of the adjacent cells framework that 2n is capable is staggered, and is connected with described framework border by grizzly bar 19.For example: framework A unit and framework B unit are two adjacent unit frameworks, wherein B8 is clipped between A1, the A2 terminal pin, A2 is clipped between B8 and the B7 terminal pin, B7 is clipped between A2 and the A3 terminal pin, A3 is clipped between B7 and the B6 terminal pin, B6 is clipped between A3 and the A4 terminal pin, and A4 is clipped between B6 and the B5 terminal pin, other and the like.
Can realize 3 chips or 4 chips or 5 chips or 6 chip-stacked many chip IC packaging parts after chip process corase grind in the present embodiment, fine grinding, the polishing.
The packaging technology flow process of two chip IC packaging parts of embodiment 3 and embodiment 5 is as follows:
A. wafer attenuate/scribing
The wafer attenuate speed of mainshaft is 2400 rpm-3000 rpm, wafer thickness thinning 380um ± 20um;
The equipment of wafer attenuate, scribing and technology are with common double framework encapsulation wafer attenuate, scribing process;
B, last core
Adopt single carrier element framework or two carrier element framework, earlier putting bonding die glue (conducting resinl or insulating cement) on single or two carrier, chip is bonded on the carrier, if different chip, earlier sticking little chip, glued the chip on sticking again another carrier behind all little chips, die Bonder adopts AD829A and two kinds of die Bonder of AD828 usually, select the shape and size of suction nozzle and Glue dripping head according to the size of chip size and chip size, the adjustable height of core is 4000-6500step on the suction nozzle, the thimble lifting height is 100-160step, and the thimble rising delay time is 5-10ms, and some glue height is 1400-2000step, bonding die glue THICKNESS CONTROL is in 8-38um, solidify baking nitrogen flow＞0.8 l/h, baking temperature 175-180 ℃, 3 hours;
C, pressure welding
Substrate heating temperature is 228 ℃-235 ℃, regulating the sparking flow is 2600mA-3100mA, regulating the discharge time of striking sparks is 630us-710us, the gold goal head is melted to obtain the slick and sly flawless gold goal FAB in surface, the time that adds on the wiring chopper is ultrasonic wave and the pressure of 10ms ± 3ms, and supersonic frequency is 120KHZ ± 10 KHZ, and the way of output is an electric current, power is 41mw ± 3mw, and pressure is output as 32gf ± 2gf;
Solidify d, plastic packaging, back
Many row's matrix form framework plastic packagings use the MGP plastic package die, injection pressure: (1200-1800) Psi, injection time: 7-15S, mold temperature: 160-180 ℃, matched moulds pressure welding: 8-20Mpa, curing time: 120-150s, back curing temperature 175-180 ℃, 7 hours;
E, printing
With common DIP plastic packaged integrated circuit production technology;
F, plating
Electroplating device from before the rack plating plating mode change the high-speed line plating mode into, earlier the product behind the plastic packaging is sent the high speed electrodeposition line to electroplate, bath temperature: 35-45 ℃, electroplating current: 95 ± 5A/ groove, thickness of coating is controlled at: 7.0-20.32um;
G, Trim Molding
Adopt automatic Trim Molding system, pipe is gone in automatic feed automatically.
The packaging technology flow process of two chip IC stack package of embodiment 4 is as follows:
A. attenuate/scribing
The wafer thickness thinning of lower floor's chip correspondence is: 200 μ m+10 μ m, roughness Ra 0.10mm～0.05mm, the wafer thickness thinning of upper strata chip correspondence is: 180 μ m+10 μ m, and the attenuate facility are equipped with the ultra-thin attenuated polishing function in 8 "～12 ", adopt the thin attenuated polishing technology of anti-warpage;
B, once go up core
Adopt single carrier element framework, use the special-purpose feed collet of going up, Glue dripping head uniformly with adhesive dots on lead frame carrier, lower floor's chip (large chip) is bonded on the carrier, and the adjustable height of core is 4000-6500step on the suction nozzle, and the thimble lifting height is 100-160step, the thimble rising delay time is 5-10ms, point glue height is 1400-2000step, and bonding die glue THICKNESS CONTROL is solidified baking nitrogen flow＞0.8 l/h in 8-38um;
Core on c, the secondary
Put insulating cement (QMI538NB) earlier in the ground floor chip front side, again second chip aimed at stick on top, be placed on the front of one deck chip.One-step solidification behind the core on twice, baking temperature: 150-175 ℃, stoving time: 180min;
D, pressure welding
Twin-core sheet stacked package generally speaking, connects the bonding wire of chip chamber up and down earlier, next connects line between lower floor's chip and pin, welds at last between upper strata chip and pin to be connected, and the bonding wire height is wanted strict control, camber is controlled at 150um-300um, prevents short circuit between the levels bonding wire.Distance between centers of tracks directly is bad less than 2 times line;
Plastic packaging, printing, plating, Trim Molding method are with DIP single-chip package part.
Utilize the production technology of single-chip IC packaging part of embodiment 1 the same with the production procedure of conventional DIP plastic packaged integrated circuit.
Claims (9)
1. matrix form DIP lead frame, form by framework and several unit frameworks of being located in the framework, it is characterized in that: described unit framework is the matrix form distribution on described framework and line number is an odd-numbered line, wherein the capable Ji Dao with the capable adjacent cells framework of 2n of 2n-1 links to each other with described framework border by intercell connector (18), 2n-1 is capable and the outer lead pin of the adjacent cells framework that 2n is capable is staggered, and is connected with described framework border by grizzly bar (19).
2. matrix form DIP lead frame according to claim 1, it is characterized in that: described unit framework is that single carrier structure and line number are odd-numbered line, wherein the capable Ji Dao with the capable adjacent cells framework of 2n of 2n-1 links to each other with described framework border by intercell connector (18), 2n-1 is capable and the outer lead pin of the adjacent cells framework that 2n is capable is staggered, and is connected with described framework border by grizzly bar (19).
3. matrix form DIP lead frame according to claim 1 is characterized in that: described unit framework is that two carrier structures and line number are odd-numbered line, and promptly each unit framework has two carriers; Wherein pin A7, the A8 of unit framework A link to each other with carrier Z2, pin A3 links to each other with carrier Z1, and the pin B7 of adjacent cells framework B links to each other with carrier Z4 with B8, pin B3 is connected with carrier Z3; Wherein the capable Ji Dao with the capable adjacent cells framework of 2n of 2n-1 links to each other with described framework border by intercell connector (18), 2n-1 is capable and the outer lead pin of the adjacent cells framework that 2n is capable is staggered, and is connected with described framework border by grizzly bar (19).
4. according to claim 1 or 2 or 3 described matrix form DIP lead frames, it is characterized in that: described unit framework is 5 row.
5. two chip IC packaging parts according to claim 2, it is characterized in that: comprise the carrier (1) on the described unit framework, the carrier of this unit framework (1) is gone up parallel placement first, the 2nd IC chip (11,12), each plants a gold or copper ball (10) in advance earlier on the pad on the one IC chip (11) and the 2nd IC chip (12), use gold or copper cash on the gold of an IC chip (11) or copper ball (10), to pile up gold thread or copper wire bonding ball then, the arcing of arch silk is piled up gold thread or copper wire bonding ball on the gold of the pad on the 2nd IC chip (12) or copper ball, form bond ball (20), this bond ball (20) makes first, the 2nd IC chip (11,12) link to each other; The outer pad of described first, second IC chip (11,12) links to each other with the interior pin (4) of unit framework by copper or gold solder line (5) bonding; At last, plastic-sealed body (6) has covered first, second IC chip (11,12), bonding gold or copper cash (5,9), gold or copper ball (10), bond ball (20) and unit framework terminal pin (4) fully and has constituted circuit integral body.
6. two chip IC packaging parts according to claim 2, it is characterized in that: comprise the carrier (1) on the described unit framework, and pile up first of placement in this carrier (1), second chip (13,14) be specially: put an IC chip (13) on this carrier (1) earlier, pad on the one IC chip (13) links to each other with interior pin (4) by bonding line (5), afterwards, put the 2nd IC chip (14) on the one IC chip (13) again, first, the 2nd IC chip (13,14) be linked by copper or gold solder line (15), adopt copper or gold thread (16) terminal pin (4) of the 2nd IC chip (14) and unit framework to be linked to each other by ball bonding, at last, plastic-sealed body (6) has covered first, the 2nd IC chip (13,14), bonding gold or copper cash (5,15,16) and the terminal pin of unit framework (4) and constituted circuit integral body.
7. two chip IC packaging parts according to claim 3, it is characterized in that: comprise the carrier (7 on the described unit framework, 8), this carrier (7,8) split first on, the 2nd IC chip (11,12), each plants a gold or copper ball (10) in advance earlier on the pad on the one IC chip (11) or the 2nd IC chip (12), use gold or copper cash on the gold of an IC chip (11) or copper ball (10), to pile up gold thread or copper wire bonding ball then, the arcing of arch silk is piled up gold thread or copper wire bonding ball on the gold of the pad on the 2nd IC chip (12) or copper ball, form bond ball (20), this bond ball (20) makes an IC chip (11) link to each other with the 2nd IC chip (12); The outer pad of described first, second IC chip (11,12) links to each other with the interior pin (4) of described unit framework by gold or copper-weld wire (5) bonding, at last, plastic-sealed body (6) has covered the terminal pin (4) of first, second IC chip (11,12), bonding gold or copper cash (5,9), gold or copper ball (10), bond ball (20) and unit framework fully and has constituted circuit integral body.
8. the packaging technology flow process according to two chip IC packaging parts of claim 5 or 7 is as follows:
The wafer attenuate speed of mainshaft is 2400 rpm-3000 rpm, wafer thickness thinning 380um ± 20um;
The equipment of wafer attenuate, scribing and technology are with common double framework encapsulation wafer attenuate, scribing process;
B, last core
Adopt single carrier element framework or two carrier element framework, earlier putting bonding die glue (conducting resinl or insulating cement) on single or two carrier, chip is bonded on the carrier, if different chip, earlier sticking little chip, glued the chip on sticking again another carrier behind all little chips, die Bonder adopts AD829A and two kinds of die Bonder of AD828 usually, select the shape and size of suction nozzle and Glue dripping head according to the size of chip size and chip size, the adjustable height of core is 4000-6500step on the suction nozzle, the thimble lifting height is 100-160 step, and the thimble rising delay time is 5-10ms, and some glue height is 1400-2000step, bonding die glue THICKNESS CONTROL is in 8-38um, solidify baking nitrogen flow＞0.8 l/h, baking temperature 175-180 ℃, 3 hours;
C, pressure welding
Substrate heating temperature is 228 ℃-235 ℃, regulating the sparking flow is 2600mA-3100mA, regulating the discharge time of striking sparks is 630us-710us, the gold goal head is melted to obtain the slick and sly flawless gold goal FAB in surface, the time that adds on the wiring chopper is ultrasonic wave and the pressure of 10ms ± 3ms, and supersonic frequency is 120KHZ ± 10 KHZ, and the way of output is an electric current, power is 41mw ± 3mw, and pressure is output as 32gf ± 2gf;
Solidify d, plastic packaging, back
Many row's matrix form framework plastic packagings use the MGP plastic package die, injection pressure: (1200-1800) Psi, injection time: 7-15s, mold temperature: 160-180 ℃, matched moulds pressure welding: 8-20Mpa, curing time: 120-150s, back curing temperature 175-180 ℃, 7 hours;
E, printing
With common DIP plastic packaged integrated circuit production technology;
F, plating
Electroplating device from before the rack plating plating mode change the high-speed line plating mode into, earlier the product behind the plastic packaging is sent the high speed electrodeposition line to electroplate, bath temperature: 35-45 ℃, electroplating current: 95 ± 5A/ groove, thickness of coating is controlled at: 7.0-20.32um;
G, Trim Molding
Adopt automatic Trim Molding system, pipe is gone in automatic feed automatically.
9. the packaging technology flow process according to two chip IC packaging parts of claim 6 is as follows:
A. attenuate/scribing
The wafer thickness thinning of lower floor's chip correspondence is: 200 μ m+10 μ m, roughness Ra 0.10mm～0.05mm, the wafer thickness thinning of upper strata chip correspondence is: 180 μ m+10 μ m, and the attenuate facility are equipped with the ultra-thin attenuated polishing function in 8 "～12 ", adopt the thin attenuated polishing technology of anti-warpage;
B, once go up core
Adopt single carrier element framework, use the special-purpose feed collet of going up, Glue dripping head uniformly with adhesive dots on the unit framework carrier, lower floor's chip (large chip) is bonded on the carrier, and the adjustable height of core is 4000-6500step on the suction nozzle, and the thimble lifting height is 100-160 step, the thimble rising delay time is 5-10ms, point glue height is 1400-2000step, and bonding die glue THICKNESS CONTROL is solidified baking nitrogen flow＞0.8 l/h in 8-38um;
Core on c, the secondary
Put insulating cement (QMI538NB) earlier in the ground floor chip front side, again second chip aimed at stick on top, be placed on the front of one deck chip; One-step solidification behind the core on twice, baking temperature: 150-175 ℃, stoving time: 180min;
D, pressure welding
Twin-core sheet stacked package generally speaking, connects the bonding wire of chip chamber up and down earlier, next connects line between lower floor's chip and pin, welds at last between upper strata chip and pin to be connected, and the bonding wire height is wanted strict control, camber is controlled at 150um-300um, prevents short circuit between the levels bonding wire; Distance between centers of tracks directly is bad less than 2 times line; Plastic packaging, printing, plating, Trim Molding method are with existing DIP single-chip package part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105613032A CN102074540B (en) | 2010-11-26 | 2010-11-26 | Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105613032A CN102074540B (en) | 2010-11-26 | 2010-11-26 | Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102074540A true CN102074540A (en) | 2011-05-25 |
| CN102074540B CN102074540B (en) | 2013-01-09 |
Family
ID=44033017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105613032A Active CN102074540B (en) | 2010-11-26 | 2010-11-26 | Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102074540B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102431950A (en) * | 2011-12-31 | 2012-05-02 | 天水华天科技股份有限公司 | Double-layer MEMS device stacked package and production method thereof |
| CN102515082A (en) * | 2011-12-31 | 2012-06-27 | 天水华天科技股份有限公司 | Single-carrier MEMS (micro-electro-mechanical system) device package and production method thereof |
| CN103035607A (en) * | 2012-12-29 | 2013-04-10 | 福建福顺半导体制造有限公司 | Method and framework for DIP (Double In-line Package) arrangement in integrated block package frame |
| CN103186657A (en) * | 2011-12-28 | 2013-07-03 | 敖翔科技股份有限公司 | Intelligent Defect Yield Overview Interface System and Method |
| CN104253103A (en) * | 2013-06-26 | 2014-12-31 | 深圳赛意法微电子有限公司 | Base-pin-staggering-mode-based lead frame structure and semiconductor device manufacturing method |
| CN104752386A (en) * | 2013-12-25 | 2015-07-01 | 天水华天科技股份有限公司 | High reliability small outline package (SOP) lead frame and production method of packaging piece |
| CN104900624A (en) * | 2015-05-28 | 2015-09-09 | 天水华天科技股份有限公司 | System-level MEMS dual-carrier chip encapsulation component and production method thereof |
| CN104952755A (en) * | 2015-06-10 | 2015-09-30 | 江苏杰进微电子科技有限公司 | Integrated circuit chip feeding device |
| CN105870094A (en) * | 2015-01-05 | 2016-08-17 | 广东气派科技有限公司 | Multi-chip packaging structure |
| CN106449517A (en) * | 2016-11-22 | 2017-02-22 | 华蓥旗邦微电子有限公司 | Stack type single base island SIP (System in Package) packaging process |
| CN109983574A (en) * | 2016-11-23 | 2019-07-05 | Abb瑞士股份有限公司 | The manufacture of power semiconductor modular |
| CN110491854A (en) * | 2019-07-31 | 2019-11-22 | 江苏明微电子有限公司 | The encapsulating structure and method of power semiconductor |
| CN110571307A (en) * | 2019-09-16 | 2019-12-13 | 无锡中微晶园电子有限公司 | Bonding wire coating process for photoelectric detection products |
| CN110797269A (en) * | 2019-11-07 | 2020-02-14 | 温州胜泰智能科技有限公司 | Integrated chip packaging method |
| CN110828413A (en) * | 2018-08-07 | 2020-02-21 | 株洲中车时代电气股份有限公司 | Lead frame and method for manufacturing rotary die power module by using lead frame |
| CN113643989A (en) * | 2021-10-13 | 2021-11-12 | 北京炬玄智能科技有限公司 | Bonding and routing method of flip crystal for integrated circuit with high stability |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1474453A (en) * | 2002-06-27 | 2004-02-11 | �뵼��Ԫ����ҵ�������ι�˾ | Integrated circuit and layered lead frame package |
| CN1649115A (en) * | 2004-01-19 | 2005-08-03 | 上海集通数码科技有限责任公司 | Package method and its structure for multiple chip integrated circuit |
| CN2935471Y (en) * | 2006-07-18 | 2007-08-15 | 天水华天科技股份有限公司 | Two-chip packaging |
| CN201215802Y (en) * | 2008-10-07 | 2009-04-01 | 宁波华龙电子股份有限公司 | Double-row-in-parallel integrated circuit lead frame plate piece |
| CN101626008A (en) * | 2009-05-11 | 2010-01-13 | 天水华天科技股份有限公司 | Production method of encapsulated component of copper wire bonding IC chip |
| CN201629330U (en) * | 2010-04-16 | 2010-11-10 | 宁波华龙电子股份有限公司 | Densely arranged integrated circuit lead frame piece |
| CN201853700U (en) * | 2010-11-26 | 2011-06-01 | 天水华天科技股份有限公司 | Array type double in-line package (DIP) lead frame and integrated circuit (IC) encapsulating piece of frame |
-
2010
- 2010-11-26 CN CN2010105613032A patent/CN102074540B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1474453A (en) * | 2002-06-27 | 2004-02-11 | �뵼��Ԫ����ҵ�������ι�˾ | Integrated circuit and layered lead frame package |
| CN1649115A (en) * | 2004-01-19 | 2005-08-03 | 上海集通数码科技有限责任公司 | Package method and its structure for multiple chip integrated circuit |
| CN2935471Y (en) * | 2006-07-18 | 2007-08-15 | 天水华天科技股份有限公司 | Two-chip packaging |
| CN201215802Y (en) * | 2008-10-07 | 2009-04-01 | 宁波华龙电子股份有限公司 | Double-row-in-parallel integrated circuit lead frame plate piece |
| CN101626008A (en) * | 2009-05-11 | 2010-01-13 | 天水华天科技股份有限公司 | Production method of encapsulated component of copper wire bonding IC chip |
| CN201629330U (en) * | 2010-04-16 | 2010-11-10 | 宁波华龙电子股份有限公司 | Densely arranged integrated circuit lead frame piece |
| CN201853700U (en) * | 2010-11-26 | 2011-06-01 | 天水华天科技股份有限公司 | Array type double in-line package (DIP) lead frame and integrated circuit (IC) encapsulating piece of frame |
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103186657B (en) * | 2011-12-28 | 2016-04-06 | 敖翔科技股份有限公司 | Intelligent defect yield overview interface system and method |
| CN103186657A (en) * | 2011-12-28 | 2013-07-03 | 敖翔科技股份有限公司 | Intelligent Defect Yield Overview Interface System and Method |
| CN102431950B (en) * | 2011-12-31 | 2015-10-07 | 天水华天科技股份有限公司 | A kind of double-deck MEMS stack package and production method thereof |
| CN102515082A (en) * | 2011-12-31 | 2012-06-27 | 天水华天科技股份有限公司 | Single-carrier MEMS (micro-electro-mechanical system) device package and production method thereof |
| CN102431950A (en) * | 2011-12-31 | 2012-05-02 | 天水华天科技股份有限公司 | Double-layer MEMS device stacked package and production method thereof |
| CN103035607B (en) * | 2012-12-29 | 2016-04-13 | 福建福顺半导体制造有限公司 | The method of DIP arrangement in a kind of integrated block package framework and framework |
| CN103035607A (en) * | 2012-12-29 | 2013-04-10 | 福建福顺半导体制造有限公司 | Method and framework for DIP (Double In-line Package) arrangement in integrated block package frame |
| CN104253103A (en) * | 2013-06-26 | 2014-12-31 | 深圳赛意法微电子有限公司 | Base-pin-staggering-mode-based lead frame structure and semiconductor device manufacturing method |
| CN104253103B (en) * | 2013-06-26 | 2018-04-03 | 深圳赛意法微电子有限公司 | The staggeredly lead frame structure and method, semi-conductor device manufacturing method of pin |
| CN104752386A (en) * | 2013-12-25 | 2015-07-01 | 天水华天科技股份有限公司 | High reliability small outline package (SOP) lead frame and production method of packaging piece |
| CN105870094A (en) * | 2015-01-05 | 2016-08-17 | 广东气派科技有限公司 | Multi-chip packaging structure |
| CN104900624A (en) * | 2015-05-28 | 2015-09-09 | 天水华天科技股份有限公司 | System-level MEMS dual-carrier chip encapsulation component and production method thereof |
| CN104900624B (en) * | 2015-05-28 | 2017-10-03 | 天水华天科技股份有限公司 | A kind of system-level MEMS complex carries chip package and its production method |
| CN104952755A (en) * | 2015-06-10 | 2015-09-30 | 江苏杰进微电子科技有限公司 | Integrated circuit chip feeding device |
| CN106449517A (en) * | 2016-11-22 | 2017-02-22 | 华蓥旗邦微电子有限公司 | Stack type single base island SIP (System in Package) packaging process |
| CN106449517B (en) * | 2016-11-22 | 2018-08-28 | 华蓥旗邦微电子有限公司 | A kind of islands stack Dan Ji SIP packaging technologies |
| CN109983574A (en) * | 2016-11-23 | 2019-07-05 | Abb瑞士股份有限公司 | The manufacture of power semiconductor modular |
| CN109983574B (en) * | 2016-11-23 | 2023-05-12 | 日立能源瑞士股份公司 | Manufacture of power semiconductor modules |
| CN110828413A (en) * | 2018-08-07 | 2020-02-21 | 株洲中车时代电气股份有限公司 | Lead frame and method for manufacturing rotary die power module by using lead frame |
| CN110828413B (en) * | 2018-08-07 | 2022-03-18 | 株洲中车时代半导体有限公司 | Lead frame and method for manufacturing rotary die power module by using lead frame |
| CN110491854A (en) * | 2019-07-31 | 2019-11-22 | 江苏明微电子有限公司 | The encapsulating structure and method of power semiconductor |
| CN110571307A (en) * | 2019-09-16 | 2019-12-13 | 无锡中微晶园电子有限公司 | Bonding wire coating process for photoelectric detection products |
| CN110797269A (en) * | 2019-11-07 | 2020-02-14 | 温州胜泰智能科技有限公司 | Integrated chip packaging method |
| CN110797269B (en) * | 2019-11-07 | 2021-02-05 | 温州胜泰智能科技有限公司 | Integrated chip packaging method |
| CN113643989A (en) * | 2021-10-13 | 2021-11-12 | 北京炬玄智能科技有限公司 | Bonding and routing method of flip crystal for integrated circuit with high stability |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102074540B (en) | 2013-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102074540B (en) | Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages | |
| CN104934405B (en) | Lead frame based on DIP Duo Ji islands and manufacture the method for packaging part with it | |
| CN101694837B (en) | Packaging part with double-row pins and four flat and pin-free surfaces and production method thereof | |
| CN110690189B (en) | EHSOP5L lead frame of high-power driving circuit, packaging piece and production method thereof | |
| CN103337483B (en) | A kind of ultrathin VSOP packaging part and production method thereof | |
| CN102163591B (en) | Spherical grating array IC (integrated circuit) chip packaging part and production method thereof | |
| CN102044517B (en) | Production method of super-high-power IC chip package | |
| CN102074541A (en) | Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof | |
| CN102263078A (en) | WLCSP (Wafer Level Chip Scale Package) packaging component | |
| CN201853700U (en) | Array type double in-line package (DIP) lead frame and integrated circuit (IC) encapsulating piece of frame | |
| CN103594447B (en) | IC chip stacked packaging piece that the big high frequency performance of packaging density is good and manufacture method | |
| CN204596785U (en) | Based on the lead frame on DIP Duo Ji island | |
| CN110783209B (en) | Production method of digital isolation core packaging part | |
| CN102263077A (en) | Double flat carrier-free pin-free IC chip packaging part | |
| CN203026496U (en) | Multi-power supply IC (Integrated Circuit) chip packaging piece | |
| CN102044445B (en) | Method for manufacturing lead frame of no-lead semiconductor package (QFN) | |
| CN215220716U (en) | Multi-base-island chip packaging structure | |
| CN110176440B (en) | Ultrasonic wave manufactured integrated circuit chip packaging structure and welding process thereof | |
| CN209447207U (en) | A kind of smart card module | |
| CN102237323A (en) | Printed circuit board (PCB) carrier tape for packaging miniature radio frequency module with load capacitor | |
| CN202196776U (en) | Flat carrier-free leadless pin exposed packaging part | |
| CN206412351U (en) | A kind of packaging part of integrated electric power system | |
| CN106783649A (en) | A kind of method for packing of integrated electric power system packaging part | |
| CN207009431U (en) | The staggeredly lead frame of pin | |
| CN115172318B (en) | A SOP300mil 8L isolation structure frame package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |